yosys.git
6 years agoYosys can now parse https://github.com/verilog-to-routing/vtr-verilog-to-routing...
Udi Finkelstein [Sun, 19 Aug 2018 21:08:08 +0000 (00:08 +0300)]
Yosys can now parse https://github.com/verilog-to-routing/vtr-verilog-to-routing/blob/master/vtr_flow/primitives.v ,
(specify block ignored).
Must use 'read_verilog -defer' due to a parameter not assigned a default value.

6 years agoA few minor enhancements to specify block parsing.
Udi Finkelstein [Wed, 15 Aug 2018 16:56:30 +0000 (19:56 +0300)]
A few minor enhancements to specify block parsing.
Just remember specify blocks are parsed but ignored.

6 years agoMerge pull request #605 from mmicko/master
Clifford Wolf [Wed, 15 Aug 2018 17:12:38 +0000 (19:12 +0200)]
Merge pull request #605 from mmicko/master

Changes for MXE configuration in order to compile

6 years agoChanges for MXE configuration in order to compile
Miodrag Milanovic [Wed, 15 Aug 2018 17:08:45 +0000 (19:08 +0200)]
Changes for MXE configuration in order to compile

6 years agoMerge pull request #573 from cr1901/msys-64
Clifford Wolf [Wed, 15 Aug 2018 12:20:10 +0000 (14:20 +0200)]
Merge pull request #573 from cr1901/msys-64

Add support for 64-bit builds using msys2 environment, use msys-provided `libpthread`.

6 years agoMerge pull request #591 from hzeller/virtual-override
Clifford Wolf [Wed, 15 Aug 2018 12:05:38 +0000 (14:05 +0200)]
Merge pull request #591 from hzeller/virtual-override

Consistent use of 'override' for virtual methods in derived classes.

6 years agoMerge pull request #590 from hzeller/remaining-file-error
Clifford Wolf [Wed, 15 Aug 2018 12:01:34 +0000 (14:01 +0200)]
Merge pull request #590 from hzeller/remaining-file-error

Fix remaining log_file_error(); emit dependent file references in new…

6 years agoMerge pull request #576 from cr1901/no-resource
Clifford Wolf [Wed, 15 Aug 2018 12:00:19 +0000 (14:00 +0200)]
Merge pull request #576 from cr1901/no-resource

Gate POSIX-only signals and resource module to only run on POSIX Pyth…

6 years agoMerge pull request #592 from japm48/master
Clifford Wolf [Wed, 15 Aug 2018 11:37:25 +0000 (13:37 +0200)]
Merge pull request #592 from japm48/master

fix basys3 example

6 years agoMerge pull request #513 from udif/pr_reg_wire_error
Clifford Wolf [Wed, 15 Aug 2018 11:35:41 +0000 (13:35 +0200)]
Merge pull request #513 from udif/pr_reg_wire_error

Add error checking for reg/wire/logic misuse - PR now passes 'make test' (plus a new test)

6 years agoMerge pull request #562 from udif/pr_fix_illegal_port_decl
Clifford Wolf [Wed, 15 Aug 2018 11:14:23 +0000 (13:14 +0200)]
Merge pull request #562 from udif/pr_fix_illegal_port_decl

Detect illegal port declaration, e.g input/output/inout keyword must …

6 years agoFix use of signed integers in JSON back-end
Clifford Wolf [Tue, 14 Aug 2018 21:31:25 +0000 (23:31 +0200)]
Fix use of signed integers in JSON back-end

Signed-off-by: Clifford Wolf <clifford@clifford.at>
6 years agoMerge pull request #602 from litghost/add_eblif_extension
Clifford Wolf [Tue, 14 Aug 2018 10:47:41 +0000 (12:47 +0200)]
Merge pull request #602 from litghost/add_eblif_extension

Map .eblif extension as blif.

6 years agoMap .eblif extension as blif.
litghost [Mon, 13 Aug 2018 21:02:53 +0000 (14:02 -0700)]
Map .eblif extension as blif.

Signed-off-by: litghost <537074+litghost@users.noreply.github.com>
6 years agoFixed use of char array for string in blifparse error handling
Clifford Wolf [Wed, 8 Aug 2018 17:41:47 +0000 (19:41 +0200)]
Fixed use of char array for string in blifparse error handling

Signed-off-by: Clifford Wolf <clifford@clifford.at>
6 years agoMerge pull request #596 from litghost/extend_blif_parser
Clifford Wolf [Wed, 8 Aug 2018 17:39:23 +0000 (19:39 +0200)]
Merge pull request #596 from litghost/extend_blif_parser

#565 Add BLIF parsing support for .conn and .cname

6 years agoReport error reason on same line as syntax error.
litghost [Wed, 8 Aug 2018 17:22:55 +0000 (10:22 -0700)]
Report error reason on same line as syntax error.

Signed-off-by: litghost <537074+litghost@users.noreply.github.com>
6 years agoMerge pull request #600 from jpathy/patch-1
Clifford Wolf [Mon, 6 Aug 2018 08:44:21 +0000 (10:44 +0200)]
Merge pull request #600 from jpathy/patch-1

Use `realpath`

6 years agoMerge pull request #599 from kbeckmann/kbeckmann/fix_readme_quotes
Clifford Wolf [Mon, 6 Aug 2018 08:41:53 +0000 (10:41 +0200)]
Merge pull request #599 from kbeckmann/kbeckmann/fix_readme_quotes

readme: Fix formatting of a keyword

6 years agoUse `realpath`
jpathy [Mon, 6 Aug 2018 06:51:07 +0000 (06:51 +0000)]
Use `realpath`

Use `os.path.realpath` instead to make sure symlinks are followed. This is also required to work for nix package manager.

6 years agoreadme: Fix formatting of a keyword
Konrad Beckmann [Mon, 6 Aug 2018 04:30:33 +0000 (13:30 +0900)]
readme: Fix formatting of a keyword

Single quotes were used instead of backticks leading to
incorrect formatting.

6 years agoUse log_warning which does not immediately terminate.
litghost [Fri, 3 Aug 2018 15:02:49 +0000 (08:02 -0700)]
Use log_warning which does not immediately terminate.

6 years agoAdd BLIF parsing support for .conn and .cname
litghost [Thu, 2 Aug 2018 21:33:39 +0000 (14:33 -0700)]
Add BLIF parsing support for .conn and .cname

6 years agofix basys3 example
japm48 [Sun, 22 Jul 2018 20:29:31 +0000 (22:29 +0200)]
fix basys3 example

Added `CONFIG_VOLTAGE` and `CFGBVS` to constraints file
to avoid warning `DRC 23-20`.

Added `open_hw` needed for programming.

6 years agoVerific: Produce errors for instantiating unknown module
Clifford Wolf [Sun, 22 Jul 2018 16:44:05 +0000 (18:44 +0200)]
Verific: Produce errors for instantiating unknown module

Because if the unknown module is connected to any constants, Verific will
actually break all constants in the same module, even if they have nothing
to do structurally with that instance of an unknown module.

Signed-off-by: Clifford Wolf <clifford@clifford.at>
6 years agoAdd missing <deque> include (MSVC build fix)
Clifford Wolf [Sun, 22 Jul 2018 13:21:59 +0000 (15:21 +0200)]
Add missing <deque> include (MSVC build fix)

Signed-off-by: Clifford Wolf <clifford@clifford.at>
6 years agoUpodate ABC to git rev ae6716b
Clifford Wolf [Sun, 22 Jul 2018 12:35:32 +0000 (14:35 +0200)]
Upodate ABC to git rev ae6716b

Signed-off-by: Clifford Wolf <clifford@clifford.at>
6 years agoAdd missing -lz to MXE build
Clifford Wolf [Sun, 22 Jul 2018 12:28:45 +0000 (14:28 +0200)]
Add missing -lz to MXE build

Signed-off-by: Clifford Wolf <clifford@clifford.at>
6 years agoConsistent use of 'override' for virtual methods in derived classes.
Henner Zeller [Sat, 21 Jul 2018 06:41:18 +0000 (23:41 -0700)]
Consistent use of 'override' for virtual methods in derived classes.

o Not all derived methods were marked 'override', but it is a great
  feature of C++11 that we should make use of.
o While at it: touched header files got a -*- c++ -*- for emacs to
  provide support for that language.
o use YS_OVERRIDE for all override keywords (though we should probably
  use the plain keyword going forward now that C++11 is established)

6 years agoFix remaining log_file_error(); emit dependent file references in new line.
Henner Zeller [Sat, 21 Jul 2018 01:52:52 +0000 (18:52 -0700)]
Fix remaining log_file_error(); emit dependent file references in new line.

There are some places that reference dependent file locations ("this function was
called from ..."). These are now in a separate line for ease of jumping to
it with the editor (behaves similarly to compilers that emit dependent
messages).

6 years agoMerge pull request #586 from hzeller/more-sourcepos-logging
Clifford Wolf [Fri, 20 Jul 2018 17:22:59 +0000 (19:22 +0200)]
Merge pull request #586 from hzeller/more-sourcepos-logging

Convert more log_error() to log_file_error() where possible.

6 years agoConvert more log_error() to log_file_error() where possible.
Henner Zeller [Fri, 20 Jul 2018 16:37:44 +0000 (09:37 -0700)]
Convert more log_error() to log_file_error() where possible.

Mostly statements that span over multiple lines and haven't been
caught with the previous conversion.

6 years agoMerge pull request #585 from hzeller/use-file-warning-error
Clifford Wolf [Fri, 20 Jul 2018 15:46:06 +0000 (17:46 +0200)]
Merge pull request #585 from hzeller/use-file-warning-error

Use log_file_warning(), log_file_error() functions

6 years agoUse log_file_warning(), log_file_error() functions.
Henner Zeller [Fri, 20 Jul 2018 15:11:20 +0000 (08:11 -0700)]
Use log_file_warning(), log_file_error() functions.

Wherever we can report a source-level location.

6 years agoMerge pull request #584 from hzeller/provide-source-location-logging
Clifford Wolf [Fri, 20 Jul 2018 14:36:06 +0000 (16:36 +0200)]
Merge pull request #584 from hzeller/provide-source-location-logging

Provide source-location logging.

6 years agoProvide source-location logging.
Henner Zeller [Thu, 19 Jul 2018 16:40:20 +0000 (09:40 -0700)]
Provide source-location logging.

o Provide log_file_warning() and log_file_error() that prefix the log
  message with <filename>:<lineno>: to be easily picked up by IDEs that
  need to step through errors.
o Simplify some duplicate logging code in kernel/log.cc
o Use the new log functions in genrtlil.

6 years agoAdd async2sync pass
Clifford Wolf [Thu, 19 Jul 2018 13:31:12 +0000 (15:31 +0200)]
Add async2sync pass

Signed-off-by: Clifford Wolf <clifford@clifford.at>
6 years agoFix handling of eventually properties in verific importer
Clifford Wolf [Tue, 17 Jul 2018 10:43:30 +0000 (12:43 +0200)]
Fix handling of eventually properties in verific importer

Signed-off-by: Clifford Wolf <clifford@clifford.at>
6 years agoFix verific -vlog-incdir and -vlog-libdir handling
Clifford Wolf [Mon, 16 Jul 2018 16:46:06 +0000 (18:46 +0200)]
Fix verific -vlog-incdir and -vlog-libdir handling

Signed-off-by: Clifford Wolf <clifford@clifford.at>
6 years agoMerge pull request #581 from daveshah1/ecp5
Clifford Wolf [Mon, 16 Jul 2018 14:58:14 +0000 (16:58 +0200)]
Merge pull request #581 from daveshah1/ecp5

Adding ECP5 synthesis target

6 years agoFix "read -incdir"
Clifford Wolf [Mon, 16 Jul 2018 14:48:09 +0000 (16:48 +0200)]
Fix "read -incdir"

Signed-off-by: Clifford Wolf <clifford@clifford.at>
6 years agoecp5: Fixing miscellaneous sim model issues
David Shah [Mon, 16 Jul 2018 13:56:12 +0000 (15:56 +0200)]
ecp5: Fixing miscellaneous sim model issues

Signed-off-by: David Shah <davey1576@gmail.com>
6 years agoMerge branch 'master' of github.com:YosysHQ/yosys
Clifford Wolf [Mon, 16 Jul 2018 13:32:38 +0000 (15:32 +0200)]
Merge branch 'master' of github.com:YosysHQ/yosys

6 years agoAdd "read -incdir"
Clifford Wolf [Mon, 16 Jul 2018 13:32:26 +0000 (15:32 +0200)]
Add "read -incdir"

Signed-off-by: Clifford Wolf <clifford@clifford.at>
6 years agoecp5: Fixing 'X' issues with LUT simulation models
David Shah [Mon, 16 Jul 2018 13:20:34 +0000 (15:20 +0200)]
ecp5: Fixing 'X' issues with LUT simulation models

Signed-off-by: David Shah <davey1576@gmail.com>
6 years agoecp5: ECP5 synthesis fixes
David Shah [Mon, 16 Jul 2018 12:33:13 +0000 (14:33 +0200)]
ecp5: ECP5 synthesis fixes

Signed-off-by: David Shah <davey1576@gmail.com>
6 years agoecp5: Adding synchronous set/reset support
David Shah [Sat, 14 Jul 2018 13:54:30 +0000 (15:54 +0200)]
ecp5: Adding synchronous set/reset support

Signed-off-by: David Shah <davey1576@gmail.com>
6 years agoecp5: Add DRAM match rule
David Shah [Fri, 13 Jul 2018 14:25:52 +0000 (16:25 +0200)]
ecp5: Add DRAM match rule

Signed-off-by: David Shah <davey1576@gmail.com>
6 years agoecp5: Cells and mappings fixes
David Shah [Fri, 13 Jul 2018 14:14:08 +0000 (16:14 +0200)]
ecp5: Cells and mappings fixes

Signed-off-by: David Shah <davey1576@gmail.com>
6 years agoecp5: Fixing arith_map
David Shah [Fri, 13 Jul 2018 13:49:59 +0000 (15:49 +0200)]
ecp5: Fixing arith_map

Signed-off-by: David Shah <davey1576@gmail.com>
6 years agoecp5: Initial arith_map implementation
David Shah [Fri, 13 Jul 2018 13:46:12 +0000 (15:46 +0200)]
ecp5: Initial arith_map implementation

Signed-off-by: David Shah <davey1576@gmail.com>
6 years agoecp5: Adding basic synth_ecp5 based on synth_ice40
David Shah [Fri, 13 Jul 2018 12:52:25 +0000 (14:52 +0200)]
ecp5: Adding basic synth_ecp5 based on synth_ice40

Signed-off-by: David Shah <davey1576@gmail.com>
6 years agoecp5: Adding DFF maps
David Shah [Fri, 13 Jul 2018 12:32:23 +0000 (14:32 +0200)]
ecp5: Adding DFF maps

Signed-off-by: David Shah <davey1576@gmail.com>
6 years agoMerge pull request #580 from daveshah1/ice40_nx
Clifford Wolf [Fri, 13 Jul 2018 12:31:38 +0000 (14:31 +0200)]
Merge pull request #580 from daveshah1/ice40_nx

ice40: Add CIN_CONST and CIN_SET parameters to ICESTORM_LC

6 years agoecp5: Adding DRAM map
David Shah [Fri, 13 Jul 2018 12:08:42 +0000 (14:08 +0200)]
ecp5: Adding DRAM map

Signed-off-by: David Shah <davey1576@gmail.com>
6 years agoecp5: Adding basic cells_sim and mapper for LUTs up to LUT7
David Shah [Fri, 13 Jul 2018 11:27:24 +0000 (13:27 +0200)]
ecp5: Adding basic cells_sim and mapper for LUTs up to LUT7

Signed-off-by: David Shah <davey1576@gmail.com>
6 years agoice40: Add CIN_CONST and CIN_SET parameters to ICESTORM_LC
David Shah [Fri, 13 Jul 2018 11:09:18 +0000 (13:09 +0200)]
ice40: Add CIN_CONST and CIN_SET parameters to ICESTORM_LC

Signed-off-by: David Shah <davey1576@gmail.com>
6 years agoGate POSIX-only signals and resource module to only run on POSIX Python implementations.
William D. Jones [Fri, 6 Jul 2018 05:36:41 +0000 (01:36 -0400)]
Gate POSIX-only signals and resource module to only run on POSIX Python implementations.

6 years agoFix verific eventually handling
Clifford Wolf [Fri, 29 Jun 2018 17:24:58 +0000 (19:24 +0200)]
Fix verific eventually handling

Signed-off-by: Clifford Wolf <clifford@clifford.at>
6 years agoAdd verific support for eventually properties
Clifford Wolf [Fri, 29 Jun 2018 17:21:04 +0000 (19:21 +0200)]
Add verific support for eventually properties

Signed-off-by: Clifford Wolf <clifford@clifford.at>
6 years agoAdd "verific -formal" and "read -formal"
Clifford Wolf [Fri, 29 Jun 2018 08:02:27 +0000 (10:02 +0200)]
Add "verific -formal" and "read -formal"

Signed-off-by: Clifford Wolf <clifford@clifford.at>
6 years agoAdd "read -sv -D" support
Clifford Wolf [Thu, 28 Jun 2018 21:58:15 +0000 (23:58 +0200)]
Add "read -sv -D" support

Signed-off-by: Clifford Wolf <clifford@clifford.at>
6 years agoAdd "read -undef"
Clifford Wolf [Thu, 28 Jun 2018 21:43:38 +0000 (23:43 +0200)]
Add "read -undef"

Signed-off-by: Clifford Wolf <clifford@clifford.at>
6 years agoFix handling of signed memories
Clifford Wolf [Thu, 28 Jun 2018 14:57:03 +0000 (16:57 +0200)]
Fix handling of signed memories

Signed-off-by: Clifford Wolf <clifford@clifford.at>
6 years agoAdd support for 64-bit builds using msys2 environment.
William D. Jones [Wed, 27 Jun 2018 20:33:34 +0000 (16:33 -0400)]
Add support for 64-bit builds using msys2 environment.

6 years agoUse msys2-provided pthreads instead of abc's.
William D. Jones [Wed, 27 Jun 2018 20:26:36 +0000 (16:26 -0400)]
Use msys2-provided pthreads instead of abc's.

6 years agoAdd YOSYS_NOVERIFIC env variable for temporarily disabling verific
Clifford Wolf [Fri, 22 Jun 2018 18:40:22 +0000 (20:40 +0200)]
Add YOSYS_NOVERIFIC env variable for temporarily disabling verific

Signed-off-by: Clifford Wolf <clifford@clifford.at>
6 years agoAdd simplified "read" command, enable extnets in implicit Verific import
Clifford Wolf [Thu, 21 Jun 2018 14:56:55 +0000 (16:56 +0200)]
Add simplified "read" command, enable extnets in implicit Verific import

Signed-off-by: Clifford Wolf <clifford@clifford.at>
6 years agoMerge branch 'master' of github.com:YosysHQ/yosys
Clifford Wolf [Wed, 20 Jun 2018 21:45:26 +0000 (23:45 +0200)]
Merge branch 'master' of github.com:YosysHQ/yosys

6 years agoAdd automatic verific import in hierarchy command
Clifford Wolf [Wed, 20 Jun 2018 21:45:01 +0000 (23:45 +0200)]
Add automatic verific import in hierarchy command

Signed-off-by: Clifford Wolf <clifford@clifford.at>
6 years agoMerge pull request #572 from q3k/q3k/fix-protobuf-build
Clifford Wolf [Wed, 20 Jun 2018 18:40:59 +0000 (20:40 +0200)]
Merge pull request #572 from q3k/q3k/fix-protobuf-build

Fix protobuf build

6 years agoFix protobuf build
Sergiusz Bazanski [Wed, 20 Jun 2018 18:28:43 +0000 (19:28 +0100)]
Fix protobuf build

6 years agoMerge pull request #571 from q3k/q3k/protobuf-backend
Clifford Wolf [Tue, 19 Jun 2018 13:02:04 +0000 (15:02 +0200)]
Merge pull request #571 from q3k/q3k/protobuf-backend

Add Protobuf backend

6 years agoAdd Protobuf backend
Serge Bazanski [Tue, 19 Jun 2018 12:34:56 +0000 (13:34 +0100)]
Add Protobuf backend

Signed-off-by: Serge Bazanski <q3k@symbioticeda.com>
6 years agoBe slightly less aggressive in "deminout" pass
Clifford Wolf [Tue, 19 Jun 2018 12:29:38 +0000 (14:29 +0200)]
Be slightly less aggressive in "deminout" pass

Signed-off-by: Clifford Wolf <clifford@clifford.at>
6 years agoMerge pull request #570 from edcote/patch-4
Clifford Wolf [Tue, 19 Jun 2018 11:47:39 +0000 (13:47 +0200)]
Merge pull request #570 from edcote/patch-4

Include module name for area summary stats

6 years agoInclude module name for area summary stats
Edmond Cote [Tue, 19 Jun 2018 00:29:01 +0000 (17:29 -0700)]
Include module name for area summary stats

The PR prints the name of the module when displaying the final area count.

Pros:
- Easier for the user to `grep` for area information about a specific module

Cons:
- Arguably more verbose, less "pretty" than author desires

Verification:
~~~~
30c30
<    Chip area for this module: 20616.349000
---
>    Chip area for module '$paramod$d1738fc0bb353d517bc2caf8fef2abb20bced034\picorv32': 20616.349000
70c70
<    Chip area for this module: 88.697700
---
>    Chip area for module '\picorv32_axi_adapter': 88.697700
102c102
<    Chip area for this module: 20705.046700
---
>    Chip area for top module '\picorv32_axi': 20705.046700
~~~~

6 years agoBugfix in liberty parser (as suggested by aiju in #569)
Clifford Wolf [Fri, 15 Jun 2018 16:56:44 +0000 (18:56 +0200)]
Bugfix in liberty parser (as suggested by aiju in #569)

Signed-off-by: Clifford Wolf <clifford@clifford.at>
6 years agoAdd "synth_ice40 -json"
Clifford Wolf [Wed, 13 Jun 2018 11:35:10 +0000 (13:35 +0200)]
Add "synth_ice40 -json"

Signed-off-by: Clifford Wolf <clifford@clifford.at>
6 years agoFix ice40_opt for cases where a port is connected to a signal with width != 1
Clifford Wolf [Mon, 11 Jun 2018 16:10:12 +0000 (18:10 +0200)]
Fix ice40_opt for cases where a port is connected to a signal with width != 1

Signed-off-by: Clifford Wolf <clifford@clifford.at>
6 years agoDetect illegal port declaration, e.g input/output/inout keyword must be the first.
Udi Finkelstein [Wed, 6 Jun 2018 19:27:25 +0000 (22:27 +0300)]
Detect illegal port declaration, e.g input/output/inout keyword must be the first.

6 years agoMerge pull request #561 from udif/pr_skip_typo
Clifford Wolf [Wed, 6 Jun 2018 09:57:41 +0000 (11:57 +0200)]
Merge pull request #561 from udif/pr_skip_typo

Fixed typo (sikp -> skip)

6 years agoFixed typo (sikp -> skip)
Udi Finkelstein [Tue, 5 Jun 2018 14:52:36 +0000 (17:52 +0300)]
Fixed typo (sikp -> skip)

6 years agoModified errors into warnings
Udi Finkelstein [Tue, 5 Jun 2018 14:44:24 +0000 (17:44 +0300)]
Modified errors into warnings
No longer false warnings for memories and assertions

6 years agoreg_wire_error test needs the -sv flag so it is run via a script so it had to be...
Udi Finkelstein [Tue, 5 Jun 2018 09:15:59 +0000 (12:15 +0300)]
reg_wire_error test needs the -sv flag so it is run via a script so it had to be moved out of the tests/simple dir that only runs Verilog files

6 years agoAdd (* gclk *) attribute support
Clifford Wolf [Fri, 1 Jun 2018 11:25:42 +0000 (13:25 +0200)]
Add (* gclk *) attribute support

Signed-off-by: Clifford Wolf <clifford@clifford.at>
6 years agoAdd setundef -anyseq / -anyconst support to -undriven mode
Clifford Wolf [Fri, 1 Jun 2018 09:57:28 +0000 (11:57 +0200)]
Add setundef -anyseq / -anyconst support to -undriven mode

Signed-off-by: Clifford Wolf <clifford@clifford.at>
6 years agoAdd "setundef -anyconst"
Clifford Wolf [Fri, 1 Jun 2018 09:49:58 +0000 (11:49 +0200)]
Add "setundef -anyconst"

Signed-off-by: Clifford Wolf <clifford@clifford.at>
6 years agoBugfix in handling of array instances with empty ports
Clifford Wolf [Thu, 31 May 2018 16:09:31 +0000 (18:09 +0200)]
Bugfix in handling of array instances with empty ports

Signed-off-by: Clifford Wolf <clifford@clifford.at>
6 years agoUpdate examples/cmos/counter.ys to use "synth" command
Clifford Wolf [Wed, 30 May 2018 12:17:36 +0000 (14:17 +0200)]
Update examples/cmos/counter.ys to use "synth" command

Signed-off-by: Clifford Wolf <clifford@clifford.at>
6 years agoMake -nordff the default in "prep"
Clifford Wolf [Wed, 30 May 2018 11:17:09 +0000 (13:17 +0200)]
Make -nordff the default in "prep"

Signed-off-by: Clifford Wolf <clifford@clifford.at>
6 years agoUpdate ABC to git rev 6df1396
Clifford Wolf [Wed, 30 May 2018 11:04:40 +0000 (13:04 +0200)]
Update ABC to git rev 6df1396

Signed-off-by: Clifford Wolf <clifford@clifford.at>
6 years agoDisable memory_dff for initialized FFs
Clifford Wolf [Mon, 28 May 2018 15:16:15 +0000 (17:16 +0200)]
Disable memory_dff for initialized FFs

Signed-off-by: Clifford Wolf <clifford@clifford.at>
6 years agoAdd some cleanup code to memory_nordff
Clifford Wolf [Mon, 28 May 2018 14:42:06 +0000 (16:42 +0200)]
Add some cleanup code to memory_nordff

Signed-off-by: Clifford Wolf <clifford@clifford.at>
6 years agoAdd comment to VIPER #13453 work-around
Clifford Wolf [Mon, 28 May 2018 11:36:35 +0000 (13:36 +0200)]
Add comment to VIPER #13453 work-around

Signed-off-by: Clifford Wolf <clifford@clifford.at>
6 years agoFix Verific handling of single-bit anyseq/anyconst wires
Clifford Wolf [Fri, 25 May 2018 13:41:45 +0000 (15:41 +0200)]
Fix Verific handling of single-bit anyseq/anyconst wires

Signed-off-by: Clifford Wolf <clifford@clifford.at>
6 years agoFix VerificClocking for cases where Verific generates chains of PRIM_SVA_POSEDGE
Clifford Wolf [Thu, 24 May 2018 16:13:38 +0000 (18:13 +0200)]
Fix VerificClocking for cases where Verific generates chains of PRIM_SVA_POSEDGE

Signed-off-by: Clifford Wolf <clifford@clifford.at>
6 years agoFix verific handling of anyconst/anyseq attributes
Clifford Wolf [Thu, 24 May 2018 15:07:06 +0000 (17:07 +0200)]
Fix verific handling of anyconst/anyseq attributes

Signed-off-by: Clifford Wolf <clifford@clifford.at>
6 years agoMerge pull request #454 from rqou/emscripten-and-abc
Clifford Wolf [Sat, 19 May 2018 06:42:45 +0000 (08:42 +0200)]
Merge pull request #454 from rqou/emscripten-and-abc

Add option to statically link abc; emscripten fixes

6 years agoForce abc to align memory to 8 bytes
Robert Ou [Sat, 19 May 2018 05:45:43 +0000 (22:45 -0700)]
Force abc to align memory to 8 bytes

Apparently abc has a memory pool implementation that by default returns
memory that is unaligned. There is a workaround in the abc makefile that
uses uname to look for "arm" specifically and then sets the alignment.
However, ARM is not the only platform that requires proper alignment
(e.g. emscripten does too). For now, pessimistically force the alignment
for 8 bytes all the time (somehow 4 wasn't enough for fixing emscripten
despite being approximately a 32-bit platform).