tree-vect-loop.c (vect_analyze_loop_operations): Also call vectorizable_reduction for vect_double_reduction_def.

2019-09-26  Richard Biener  <rguenther@suse.de>

* tree-vect-loop.c (vect_analyze_loop_operations): Also call
vectorizable_reduction for vect_double_reduction_def.
(vect_transform_loop): Likewise.
(vect_create_epilog_for_reduction): Move double-reduction
PHI creation and preheader argument setting of PHIs ...
(vectorizable_reduction): ... here.  Also process
vect_double_reduction_def PHIs, creating the vectorized
PHI nodes, remembering the scalar adjustment computed for
the epilogue in STMT_VINFO_REDUC_EPILOGUE_ADJUSTMENT.
Remember the original reduction code in STMT_VINFO_REDUC_CODE.
* tree-vectorizer.c (vec_info::new_stmt_vec_info):
Initialize STMT_VINFO_REDUC_CODE.
* tree-vectorizer.h (_stmt_vec_info::reduc_epilogue_adjustment): New.
(_stmt_vec_info::reduc_code): Likewise.
(STMT_VINFO_REDUC_EPILOGUE_ADJUSTMENT): Likewise.
(STMT_VINFO_REDUC_CODE): Likewise.

From-SVN: r276150

Add myself as an aarch64 maintainer

2019-09-26  Richard Sandiford  <richard.sandiford@arm.com>

* MAINTAINERS: Add myself as an aarch64 maintainer.

From-SVN: r276149

driver: Also prune joined switches with negation

When -march=native is passed to host_detect_local_cpu to the backend,
it overrides all command lines after it.  That means

$ gcc -march=native -march=armv8-a

is treated as

$ gcc -march=armv8-a -march=native

Prune joined switches with Negative and RejectNegative to allow
-march=armv8-a to override previous -march=native on command-line.

This is the same fix as was applied for i386 in SVN revision 269164 but for
aarch64 and arm.

2019-09-26  Matt Turner  <mattst88@gmail.com>

PR driver/69471
* config/aarch64/aarch64.opt (march=): Add Negative(march=).
(mtune=): Add Negative(mtune=).
(mcpu=): Add Negative(mcpu=).
* config/arm/arm.opt: Likewise.

From-SVN: r276148

[arm] Implement DImode SIMD32 intrinsics

This patch implements some more SIMD32, but these ones have a DImode result+addend.
Apart from that there's nothing too exciting about them.

Bootstrapped and tested on arm-none-linux-gnueabihf.

* config/arm/arm.md (arm_<simd32_op>): New define_insn.
* config/arm/arm_acle.h (__smlald, __smlaldx, __smlsld, __smlsldx):
Define.
* config/arm/arm_acle.h: Define builtins for the above.
* config/arm/iterators.md (SIMD32_DIMODE): New int_iterator.
(simd32_op): Handle the above.
* config/arm/unspecs.md: Define unspecs for the above.

* gcc.target/arm/acle/simd32.c: Update test.

From-SVN: r276147

[arm] Implement non-GE-setting SIMD32 intrinsics

This patch is part of a series to implement the SIMD32 ACLE intrinsics [1].
The interesting parts implementation-wise involve adding support for setting and reading
the Q bit for saturation and the GE-bits for the packed SIMD instructions.
That will come in a later patch.

For now, this patch implements the other intrinsics that don't need anything special ;
just a mapping from arm_acle.h function to builtin to RTL expander+unspec.

I've compressed as many as I could with iterators so that we end up needing only 3
new define_insns.

Bootstrapped and tested on arm-none-linux-gnueabihf.

[1] https://developer.arm.com/docs/101028/latest/data-processing-intrinsics

* config/arm/arm.md (arm_<simd32_op>): New define_insn.
(arm_<sup>xtb16): Likewise.
(arm_usada8): Likewise.
* config/arm/arm_acle.h (__qadd8, __qsub8, __shadd8, __shsub8,
__uhadd8, __uhsub8, __uqadd8, __uqsub8, __qadd16, __qasx, __qsax,
__qsub16, __shadd16, __shasx, __shsax, __shsub16, __uhadd16, __uhasx,
__uhsax, __uhsub16, __uqadd16, __uqasx, __uqsax, __uqsub16, __sxtab16,
__sxtb16, __uxtab16, __uxtb16): Define.
* config/arm/arm_acle_builtins.def: Define builtins for the above.
* config/arm/unspecs.md: Define unspecs for the above.
* config/arm/iterators.md (SIMD32_NOGE_BINOP): New int_iterator.
(USXTB16): Likewise.
(simd32_op): New int_attribute.
(sup): Handle UNSPEC_SXTB16, UNSPEC_UXTB16.
* doc/sourcebuild.exp (arm_simd32_ok): Document.

* lib/target-supports.exp
(check_effective_target_arm_simd32_ok_nocache): New procedure.
(check_effective_target_arm_simd32_ok): Likewise.
(add_options_for_arm_simd32): Likewise.
* gcc.target/arm/acle/simd32.c: New test.

From-SVN: r276146

[arm] Update FP16 tests

My recent assemble_real patch (r275873) meant that we now output
negative FP16 constants in the same way as we'd output an integer
subreg of them.  This patch updates gcc.target/arm/fp16-* accordingly.

2019-09-26  Richard Sandiford  <richard.sandiford@arm.com>

gcc/testsuite/
* gcc.target/arm/fp16-compile-alt-3.c: Expect (__fp16) -2.0
to be written as a negative short rather than a positive one.
* gcc.target/arm/fp16-compile-ieee-3.c: Likewise.

From-SVN: r276145

[PATCH] Fix quoting in a call to internal_error

2019-09-26  Martin Jambor  <mjambor@suse.cz>

* ipa-sra.c (verify_splitting_accesses): Fix quoting in a call to
internal_error.

From-SVN: r276144

[PATCH] Fix continue condition in IPA-SRA's process_scan_results

2019-09-26  Martin Jambor  <mjambor@suse.cz>

* ipa-sra.c (process_scan_results): Fix continue condition.

From-SVN: r276143

Add myself as aarch64 port maintainer

* MAINTAINERS: Add myself as aarch64 maintainer.

From-SVN: r276142

Add TODO_update_ssa for SLP BB vectorization (PR tree-optimization/91885).

2019-09-26  Martin Liska  <mliska@suse.cz>

PR tree-optimization/91885
* tree-vectorizer.c (try_vectorize_loop_1):
Add TODO_update_ssa_only_virtuals similarly to what slp
pass does.
2019-09-26  Martin Liska  <mliska@suse.cz>

PR tree-optimization/91885
* gcc.dg/pr91885.c: New test.

From-SVN: r276141

[AArch64] Fix cost of (plus ... (const_int -C))

The PLUS handling in aarch64_rtx_costs only checked for nonnegative
constants, meaning that simple immediate subtractions like:

  (set (reg R1) (plus (reg R2) (const_int -8)))

had a cost of two instructions.

2019-09-26  Richard Sandiford  <richard.sandiford@arm.com>

gcc/
* config/aarch64/aarch64.c (aarch64_rtx_costs): Use
aarch64_plus_immediate rather than aarch64_uimm12_shift
to test for valid PLUS immediates.

From-SVN: r276140

Daily bump.

From-SVN: r276139

libgcc: Rebuild autoconf files

        * config.in, configure: Re-rebuild with stock autoconf 2.69,
        not the ubuntu modified 2.69.

From-SVN: r276135

aarch64: Configure for sys/auxv.h in libgcc for lse-init.c

PR target/91833
* config/aarch64/lse-init.c: Include auto-target.h.  Disable
initialization if !HAVE_SYS_AUXV_H.
* configure.ac (AC_CHECK_HEADERS): Add sys/auxv.h.
* config.in, configure: Rebuild.

From-SVN: r276134

aarch64: Fix store-exclusive in load-operate LSE helpers

PR target/91834
* config/aarch64/lse.S (LDNM): Ensure STXR output does not
overlap the inputs.

From-SVN: r276133

Colorize %L and %C text to match diagnostic_show_locus (PR fortran/91426)

gcc/fortran/ChangeLog:
PR fortran/91426
* error.c (curr_diagnostic): New static variable.
(gfc_report_diagnostic): New static function.
(gfc_warning): Replace call to diagnostic_report_diagnostic with
call to gfc_report_diagnostic.
(gfc_format_decoder): Colorize the text of %L and %C to match the
colorization used by diagnostic_show_locus.
(gfc_warning_now_at): Replace call to diagnostic_report_diagnostic with
call to gfc_report_diagnostic.
(gfc_warning_now): Likewise.
(gfc_warning_internal): Likewise.
(gfc_error_now): Likewise.
(gfc_fatal_error): Likewise.
(gfc_error_opt): Likewise.
(gfc_internal_error): Likewise.

From-SVN: r276132

Remove newly unused function and variable in tree-sra

Hi,

Martin and his clang warnings discovered that I forgot to remove a
static inline function and a variable when ripping out the old IPA-SRA
from tree-sra.c and both are now unused.  Thus I am doing that now
with the patch below which I will commit as obvious (after including
it in a round of a bootstrap and testing on an x86_64-linux).

Thanks,

Martin

2019-09-25  Martin Jambor  <mjambor@suse.cz>

* tree-sra.c (no_accesses_p): Remove.
(no_accesses_representant): Likewise.

From-SVN: r276128

PR c++/91877 - ICE with converting member of packed struct.

* call.c (convert_like_real): Use similar_type_p in an assert.

* g++.dg/conversion/packed1.C: New test.

From-SVN: r276127

[AArch64] Use implementation namespace consistently in arm_neon.h

We're somewhat inconsistent in arm_neon.h when it comes to using the implementation namespace for local
identifiers. This means things like:
#define hash_abcd 0
#define hash_e 1
#define wk 2

#include "arm_neon.h"

uint32x4_t
foo (uint32x4_t a, uint32_t b, uint32x4_t c)
{
  return vsha1cq_u32 (a, b, c);
}

don't compile.
This patch fixes these issues throughout the whole of arm_neon.h
Bootstrapped and tested on aarch64-none-linux-gnu.
The advsimd-intrinsics.exp tests pass just fine.

From-SVN: r276125

re PR tree-optimization/91896 (ICE in vect_get_vec_def_for_stmt_copy, at tree-vect-stmts.c:1687)

2019-09-25  Richard Biener  <rguenther@suse.de>

PR tree-optimization/91896
* tree-vect-loop.c (vectorizable_reduction): The single
def-use cycle optimization cannot apply when there's more
than one pattern stmt involved.

* gcc.dg/torture/pr91896.c: New testcase.

From-SVN: r276123

[AARCH64] Add support for new control bits CTR_EL0.DIC and CTR_EL0.IDC

The DCache clean & ICache invalidation requirements for instructions
to be data coherence are discoverable through new fields in CTR_EL0.
Let's support the two bits if they are enabled, the CPU core will
not execute the unnecessary DCache clean or Icache Invalidation
instructions.

2019-09-25  Shaokun Zhang  <zhangshaokun@hisilicon.com>

* config/aarch64/sync-cache.c (__aarch64_sync_cache_range): Add support for
CTR_EL0.IDC and CTR_EL0.DIC.

From-SVN: r276122

Implement LWG 3296 for basic_regex::assign

* include/bits/regex.h
(basic_regex::assign(const C*, size_t, flag_type)): Add default
argument (LWG 3296).
* testsuite/28_regex/basic_regex/assign/char/lwg3296.cc: New test.
* testsuite/28_regex/basic_regex/assign/wchar_t/lwg3296.cc: New test.

From-SVN: r276121

Move a target test-case to generic folder.

2019-09-25  Martin Liska  <mliska@suse.cz>

* gcc.target/s390/pr91014.c: Move to ...
* gcc.dg/pr91014.c: ... this.

From-SVN: r276120

name-lookup.c (check_extern_c_conflict): Use DECL_SOURCE_LOCATION.

/cp
2019-09-25  Paolo Carlini  <paolo.carlini@oracle.com>

* name-lookup.c (check_extern_c_conflict): Use DECL_SOURCE_LOCATION.
(check_local_shadow): Use it in three additional places.

/testsuite
2019-09-25  Paolo Carlini  <paolo.carlini@oracle.com>

* g++.dg/diagnostic/redeclaration-1.C: New.
* g++.dg/lookup/extern-c-hidden.C: Test location(s) too.
* g++.dg/lookup/extern-c-redecl.C: Likewise.
* g++.dg/lookup/extern-c-redecl6.C: Likewise.
* g++.old-deja/g++.other/using9.C: Likewise.

From-SVN: r276119

Fix location of dependent member CALL_EXPR.

The break here was skipping over the code that sets EXPR_LOCATION on the
call expressions, for no good reason.

* parser.c (cp_parser_postfix_expression): Do set location of
dependent member call.

From-SVN: r276112

Daily bump.

From-SVN: r276111

[Darwin, PPC, Mode Iterators 1/n] Use mode iterators in picbase patterns.

This switches the picbase load and reload patterns to use the 'P' mode
iterator instead of writing an SI and DI pattern for each.

gcc/ChangeLog:

2019-09-24  Iain Sandoe  <iain@sandoe.co.uk>

* config/rs6000/rs6000.md (load_macho_picbase_<mode>): New, using
the 'P' mode iterator, replacing the (removed) SI and DI variants.
(reload_macho_picbase_<mode>): Likewise.

From-SVN: r276107

[Darwin, PPC, Mode Iterators 0/n] Make iterators visible to darwin.md.

As a clean-up, we want to be able to use mode iterators in darwin.md.
This patch moves the include point for the Darwin include until after
the definition of the mode iterators and attrs.  No functional change
intended.

gcc/ChangeLog:

2019-09-24  Iain Sandoe  <iain@sandoe.co.uk>

* config/rs6000/rs6000.md: Move darwin.md include until
after the definition of the mode iterators.

From-SVN: r276106

PR tree-optimization/91570 - ICE in get_range_strlen_dynamic on a conditional

PR tree-optimization/91570 - ICE in get_range_strlen_dynamic on a conditional
of two strings

gcc/Changelog:
* tree-ssa-strlen.c (get_range_strlen_dynamic): Handle null and
non-constant minlen, maxlen and maxbound.

gcc/testsuite/Changelog:
* gcc.dg/pr91570.c: New test.

From-SVN: r276105

PR c++/91868 - improve -Wshadow location.

* name-lookup.c (check_local_shadow): Use DECL_SOURCE_LOCATION
instead of input_location.

* g++.dg/warn/Wshadow-16.C: New test.

From-SVN: r276103

PR c++/91845 - ICE with invalid pointer-to-member.

* expr.c (mark_use): Use error_operand_p.
* typeck2.c (build_m_component_ref): Check error_operand_p after
calling mark_[lr]value_use.

* g++.dg/cpp1y/pr91845.C: New test.

From-SVN: r276102

Remove check for impossible condition in std::variant::index()

The __index_type is only ever unsigned char or unsigned short, so not
the same type as size_t.

* include/std/variant (variant::index()): Remove impossible case.

From-SVN: r276100

tree-vectorizer.h (_stmt_vec_info::const_cond_reduc_code): Rename to...

2019-09-24  Richard Biener  <rguenther@suse.de>

* tree-vectorizer.h (_stmt_vec_info::const_cond_reduc_code):
Rename to...
(_stmt_vec_info::cond_reduc_code): ... this.
(_stmt_vec_info::induc_cond_initial_val): Add.
(STMT_VINFO_VEC_CONST_COND_REDUC_CODE): Rename to...
(STMT_VINFO_VEC_COND_REDUC_CODE): ... this.
(STMT_VINFO_VEC_INDUC_COND_INITIAL_VAL): Add.
* tree-vectorizer.c (vec_info::new_stmt_vec_info): Adjust.
* tree-vect-loop.c (get_initial_def_for_reduction): Pass in
the reduction code.
(vect_create_epilog_for_reduction): Drop special
induction condition reduction params, pass in reduction code
and simplify.
(vectorizable_reduction): Perform condition reduction kind
selection only at analysis time.  Adjust passing on state.

From-SVN: r276099

[AArch64] Don't split 64-bit constant stores to volatile location

The optimisation to optimise:
   typedef unsigned long long u64;

   void bar(u64 *x)
   {
     *x = 0xabcdef10abcdef10;
   }

from:
        mov     x1, 61200
        movk    x1, 0xabcd, lsl 16
        movk    x1, 0xef10, lsl 32
        movk    x1, 0xabcd, lsl 48
        str     x1, [x0]

into:
        mov     w1, 61200
        movk    w1, 0xabcd, lsl 16
        stp     w1, w1, [x0]

ends up producing two distinct stores if the destination is volatile:
  void bar(u64 *x)
  {
    *(volatile u64 *)x = 0xabcdef10abcdef10;
  }
        mov     w1, 61200
        movk    w1, 0xabcd, lsl 16
        str     w1, [x0]
        str     w1, [x0, 4]

because we end up not merging the strs into an stp. It's questionable whether the use of STP is valid for volatile in the first place.
To avoid unnecessary pain in a context where it's unlikely to be performance critical [1] (use of volatile), this patch avoids this
transformation for volatile destinations, so we produce the original single STR-X.

Bootstrapped and tested on aarch64-none-linux-gnu.

[1] https://lore.kernel.org/lkml/20190821103200.kpufwtviqhpbuv2n@willie-the-truck/

* config/aarch64/aarch64.md (mov<mode>): Don't call
aarch64_split_dimode_const_store on volatile MEM.

* gcc.target/aarch64/nosplit-di-const-volatile_1.c: New test.

From-SVN: r276098

[GCC][PATCH][AArch64] Update hwcap string for fp16fml in aarch64-option-extensions.def

This is a minor patch that fixes the entry for the fp16fml feature in
GCC's aarch64-option-extensions.def.

As can be seen in the Linux sources here
https://github.com/torvalds/linux/blob/master/arch/arm64/kernel/cpuinfo.c#L69
the correct string is "asimdfhm", not "asimdfml".

Cross-compiled and tested on aarch64-none-linux-gnu.

2019-09-24  Stamatis Markianos-Wright  <stam.markianos-wright@arm.com>

* config/aarch64/aarch64-option-extensions.def (fp16fml):
Update hwcap string for fp16fml.

From-SVN: r276097

re PR middle-end/91866 (Sign extend of an int is not recognized)

PR middle-end/91866
* match.pd (((T)(A)) + CST -> (T)(A + CST)): Formatting fix.
(((T)(A + CST1)) + CST2 -> (T)(A) + (T)CST1 + CST2): New optimization.

* gcc.dg/tree-ssa/pr91866.c: New test.

From-SVN: r276096

Use more switch statements.

2019-09-24  Martin Liska  <mliska@suse.cz>

* cfgexpand.c (gimple_assign_rhs_to_tree): Use switch statement
instead of if-elseif-elseif-...
* gimple-expr.c (extract_ops_from_tree): Likewise.
* gimple.c (get_gimple_rhs_num_ops): Likewise.
* tree-ssa-forwprop.c (rhs_to_tree): Likewise.

From-SVN: r276095

[PR 91831] Copy PARM_DECLs of artificial thunks

Hi,

I am quite surprised I did not catch this before but the new
ipa-param-manipulation does not copy PARM_DECLs when creating
artificial thinks (I think it originally did but then I somehow
removed during one cleanups).  Fixed by adding the capability at the
natural place.  It is triggered whenever context of the PARM_DECL that
is just taken from the original function does not match the target
fndecl rather than by some constructor parameter because in such
situation it is always the correct thing to do.

Bootstrapped and tested on x86_64-linux.  OK for trunk?

Thanks,

Martin

2019-09-24  Martin Jambor  <mjambor@suse.cz>

PR ipa/91831
* ipa-param-manipulation.c (carry_over_param): Make a method of
ipa_param_body_adjustments, remove now unnecessary argument.  Also copy
in case of a context mismatch.
(ipa_param_body_adjustments::common_initialization): Adjust call to
carry_over_param.
* ipa-param-manipulation.h (class ipa_param_body_adjustments): Add
private method carry_over_param.

testsuite/
* g++.dg/ipa/pr91831.C: New test.

From-SVN: r276094

[PR 91832] Do not ICE on negative offsets in ipa-sra

Hi,

IPA-SRA asserts that an offset obtained from get_ref_base_and_extent
is non-negative (after it verifies it is based on a parameter).  That
assumption is invalid as the testcase shows.  One could probably also write a
testcase with defined behavior, but unless I see a reasonable one
where the transformation is really desirable, I'd like to just punt on
those cases.

Bootstrapped and tested on x86_64-linux.  OK for trunk?

Thanks,

Martin

2019-09-24  Martin Jambor  <mjambor@suse.cz>

PR ipa/91832
* ipa-sra.c (scan_expr_access): Check that offset is non-negative.

testsuite/
* gcc.dg/ipa/pr91832.c: New test.

From-SVN: r276093

tree-ssa-sccvn.c (vn_reference_lookup_3): Valueize MEM_REF base.

2019-09-24  Richard Biener  <rguenther@suse.de>

* tree-ssa-sccvn.c (vn_reference_lookup_3): Valueize MEM_REF
base.

* gcc.dg/torture/20190924-1.c: New testcase.

From-SVN: r276092

PR libstdc++/91871 fix Clang warnings in testsuite

PR libstdc++/91871
* testsuite/util/testsuite_hooks.h
(conversion::iterator_to_const_iterator()): Do not return an invalid
iterator. Test direct-initialization and direct-list-initialization
as well as implicit conversion.

From-SVN: r276091

Daily bump.

From-SVN: r276089

GNAT/testsuite: Pass the `ada' option to target compilation

Pass the `ada' option to DejaGNU's `target_compile' procedure, which by
default calls `default_target_compile', so that it arranges for an Ada
compilation rather the default of C.  We set the compiler to `gnatmake'
manually here, so that part of the logic in `default_target_compile' is
not used, but it affects other settings, such as the use of `adaflags'.

gcc/testsuite/
* lib/gnat.exp (gnat_target_compile): Pass the `ada' option to
`target_compile'.

From-SVN: r276085

RS6000, add xxswapd support

gcc/ChangeLog:

2019-09-23  Carl Love  <cel@us.ibm.com>

* config/rs6000/vsx.md (xxswapd_v4si, xxswapd_v8hi, xxswapd_v16qi):
New define_insn.
(vsx_xxpermdi4_le_<mode> for VSX_W, vsx_xxpermdi8_le_V8HI,
vsx_xxpermdi16_le_V16QI): Removed define_insn.

From-SVN: r276065

pt.c (check_explicit_specialization): Use cp_expr_loc_or_input_loc.

/cp
2019-09-23  Paolo Carlini  <paolo.carlini@oracle.com>

* pt.c (check_explicit_specialization): Use cp_expr_loc_or_input_loc.
(process_partial_specialization): Likewise.
(convert_nontype_argument_function): Likewise.
(invalid_tparm_referent_p): Likewise.
(convert_template_argument): Likewise.
(check_valid_ptrmem_cst_expr): Tidy.

/testsuite
2019-09-23  Paolo Carlini  <paolo.carlini@oracle.com>

* g++.dg/cpp0x/pr68724.C: Check location(s) too.
* g++.dg/cpp0x/variadic38.C: Likewise.
* g++.dg/cpp1z/nontype2.C: Likewise.
* g++.dg/parse/explicit1.C: Likewise.
* g++.dg/template/crash11.C: Likewise.
* g++.dg/template/non-dependent8.C: Likewise.
* g++.dg/template/nontype-array1.C: Likewise.
* g++.dg/template/nontype3.C: Likewise.
* g++.dg/template/nontype8.C: Likewise.
* g++.dg/template/partial5.C: Likewise.
* g++.dg/template/spec33.C: Likewise.
* g++.old-deja/g++.pt/memtemp64.C: Likewise.
* g++.old-deja/g++.pt/spec20.C: Likewise.
* g++.old-deja/g++.pt/spec21.C: Likewise.
* g++.old-deja/g++.robertl/eb103.C: Likewise.

From-SVN: r276064

2019-09-23  Sandra Loosemore  <sandra@codesourcery.com>

gcc/testsuite/
* lib/target-supports.exp
(check_effective_target_arm_vfp_ok_nocache): New.
(check_effective_target_arm_vfp_ok): Rewrite.
(add_options_for_arm_vfp): New.
(add_options_for_sqrt_insn): Add options for arm.
* gcc.target/arm/attr-neon-builtin-fail2.c: Use dg-add-options.
* gcc.target/arm/short-vfp-1.c: Likewise.

From-SVN: r276063

PR c++/91809 - bit-field and ellipsis.

decay_conversion converts a bit-field access to its declared type, which
isn't what we want here; it even has a comment that the caller is expected
to have already used default_conversion to perform integral promotion.  This
function handles arithmetic promotion differently, but we still don't want
to call decay_conversion before that happens.

* call.c (convert_arg_to_ellipsis): Don't call decay_conversion for
arithmetic arguments.

From-SVN: r276059

PR c++/91844 - Implement CWG 2352, Similar types and reference binding.

* call.c (reference_related_p): Use similar_type_p instead of
same_type_p.
(reference_compatible_p): Update implementation to match CWG 2352.
* cp-tree.h (similar_type_p): Declare.
* typeck.c (similar_type_p): New.

* g++.dg/cpp0x/pr33930.C: Add dg-error.
* g++.dg/cpp0x/ref-bind1.C: New test.
* g++.dg/cpp0x/ref-bind2.C: New test.
* g++.dg/cpp0x/ref-bind3.C: New test.
* g++.old-deja/g++.pt/spec35.C: Remove dg-error.

From-SVN: r276058

[arm] Add missing Makefile dependency on arm_acle_builtins.def

arm-builtins.o is missing a Makefile dependency on arm_acle_builtins.def
which can cause inconsistent rebuilds
when adding builtins in there.

This patch adds the right Makefile-foo to fix that.

* config/arm/t-arm (arm-builtins.o): Add dependency on
arm_acle_builtins.def.

From-SVN: r276057

PR libstdc++/91788 improve codegen for std::variant<T...>::index()

If __index_type is a smaller type than size_t, then the result of
size_t(__index_type(-1)) is not equal to size_t(-1), but to an incorrect
value such as size_t(255) or size_t(65535). The old implementation of
variant<T...>::index() uses (size_t(__index_type(_M_index + 1)) - 1)
which is always correct, but generates suboptimal code for many common
cases.

When the __index_type is size_t or valueless variants are not possible
we can just return the value directly.

When the number of alternatives is sufficiently small the result of
converting the _M_index value to the corresponding signed type will be
either non-negative or -1. In those cases converting to the signed type
and then to size_t will either produce the correct positive value or
will sign extend -1 to (size_t)-1 as desired.

For the remaining case we keep the existing arithmetic operations to
ensure the correct result.

PR libstdc++/91788 (partial)
* include/std/variant (variant::index()): Improve codegen for cases
where conversion to size_t already works correctly.

From-SVN: r276056

Fix non-canonical CONST_INTs in altivec_copysign_v4sf3 (PR91823)

The pattern was generating zero-extended rather than sign-extended
CONST_INTs.

2019-09-23  Richard Sandiford  <richard.sandiford@arm.com>

gcc/
PR target/91823
* config/rs6000/altivec.md (altivec_copysign_v4sf3): Generate
canonical CONST_INTs.  Use gen_rtvec.

From-SVN: r276055

tree-vect-loop.c (get_initial_def_for_reduction): Simplify, avoid adjusting by + 0 or * 1.

2019-09-23  Richard Biener  <rguenther@suse.de>

* tree-vect-loop.c (get_initial_def_for_reduction): Simplify,
avoid adjusting by + 0 or * 1.
(vect_create_epilog_for_reduction): Get reduction code only
when necessary.  Deal with adjustment_def only when necessary.

From-SVN: r276054

Skip gcc.dg/ucnid-5-utf8.c unless ucn is supported

* gcc.dg/ucnid-5-utf8.c: Skip unless ucn is supported.

From-SVN: r276053

[AArch64] Fix memmodel index in aarch64_store_exclusive_pair

Found via an rtx checking failure.

2019-09-23  Richard Sandiford  <richard.sandiford@arm.com>

gcc/
* config/aarch64/atomics.md (aarch64_store_exclusive_pair): Fix
memmodel index.

From-SVN: r276052

re PR fortran/91729 (ICE in gfc_match_select_rank, at fortran/match.c:6586)

2019-09-23  Paul Thomas  <pault@gcc.gnu.org>

PR fortran/91729
* match.c (gfc_match_select_rank): Initialise 'as' to NULL.
Check for a symtree in the selector expression before trying to
assign a value to 'as'. Revert to gfc_error and go to cleanup
after setting a MATCH_ERROR.

2019-09-23  Paul Thomas  <pault@gcc.gnu.org>

PR fortran/91729
* gfortran.dg/select_rank_2.f90 : Add two more errors in foo2.
* gfortran.dg/select_rank_3.f90 : New test.

From-SVN: r276051

Use underscore in IPA-SRA LTO section name (PR ipa/91835)

PR ipa/91835
* lto-section-in.c (lto_section_name): Use "ipa_sra" instead of
"ipa-sra".

From-SVN: r276050

Provide Task_Info.Number_Of_Processors on Solaris

gcc/ada:
* libgnarl/s-osinte__solaris.ads (sysconf): Declare.
(SC_NPROCESSORS_ONLN): Define.
* libgnarl/s-tasinf__solaris.ads (Number_Of_Processors): Declare.
* libgnarl/s-tasinf__solaris.adb (N_CPU): New variable.
(Number_Of_Processors): New function.

gcc/testsuite:
* gnat.dg/system_info1.adb: Sort dg-do target list.
Add *-*-solaris2.*.

From-SVN: r276049

* config/abi/post/riscv64-linux-gnu/baseline_symbols.txt: Update.

From-SVN: r276048

trans.c (Regular_Loop_to_gnu): Do not rotate the loop if -Og is enabled.

* gcc-interface/trans.c (Regular_Loop_to_gnu): Do not rotate the loop
if -Og is enabled.
(build_return_expr): Do not perform NRV if -Og is enabled.
(Subprogram_Body_to_gnu): Likewise.
(gnat_to_gnu) <N_Simple_Return_Statement>: Likewise.
(Handled_Sequence_Of_Statements_to_gnu): Do not inline finalizers if
-Og is enabled.
* gcc-interface/utils.c (convert_to_index_type): Return early if -Og
is enabled.

From-SVN: r276047

Fix typo

From-SVN: r276046

trans.c (gnat_compile_time_expr_list): New variable.

* gcc-interface/trans.c (gnat_compile_time_expr_list): New variable.
(Pragma_to_gnu): Rename local variable.  Save the (first) expression
of pragma Compile_Time_{Error|Warning} for later processing.
(Compilation_Unit_to_gnu): Process the expressions saved above.

From-SVN: r276045

trans.c (Attribute_to_gnu): Test Can_Use_Internal_Rep on the underlying type of the node.

* gcc-interface/trans.c (Attribute_to_gnu): Test Can_Use_Internal_Rep
on the underlying type of the node.
(Call_to_gnu): Likewise with the type of the prefix.

From-SVN: r276041

decl.c (components_to_record): Do not reorder fields in packed record types if...

* gcc-interface/decl.c (components_to_record): Do not reorder fields
in packed record types if they contain fixed-size fields that cannot
be laid out in a packed manner.

From-SVN: r276036

Daily bump.

From-SVN: r276035

[Darwin, PPC] Clean up symbol stubs code.

Remove dead code for the the TARGET_LINK_STACK which is not
applicable to Darwin. Use MACHOPIC_PURE instead of a hard-wired
PIC level to determine the stub kind.

Merge common code blocks.

gcc/ChangeLog:

2019-09-22  Iain Sandoe  <iain@sandoe.co.uk>

* config/rs6000/rs6000.c (machopic_output_stub): Remove dead
code.  Merge code blocks with common conditionals. Use declared
macro instead of a magic number for PIC level.

From-SVN: r276030

PR c++/91819 - ICE with operator++ and enum.

* call.c (build_new_op_1): Set arg2_type.

* g++.dg/other/operator4.C: New test.

From-SVN: r276027

Daily bump.

From-SVN: r276026

PR middle-end/91830 - Bogus -Warray-bounds on strcpy into a member

PR middle-end/91830 - Bogus -Warray-bounds on strcpy into a member
of a subobject compiling binutils

gcc/ChangeLog:
* gcc/gimple-ssa-warn-restrict.c (builtin_memref::set_base_and_offset):
Simplify computation of the offset of the referenced subobject.

gcc/testsuite/ChangeLog:
* gcc/testsuite/gcc.dg/Warray-bounds-47.c: New test.

From-SVN: r276022

re PR c++/30277 (bit-field: wrong overload resolution)

PR c++/30277
* g++.dg/expr/bitfield14.C (struct S): Use signed long long instead
of signed long.
(foo): Use long long instead of long.

From-SVN: r276021

[Darwin] Update machopic_legitimize_pic_address.

Some changes were missed here in the transition to LRA.  The Darwin
archs are all using LRA now.

gcc/ChangeLog:

2019-09-21  Iain Sandoe  <iain@sandoe.co.uk>

* config/darwin.c (machopic_legitimize_pic_address): Check
for lra not reload.

From-SVN: r276020

DR 2345 - Jumping across initializers in init-statements and conditions.

* g++.dg/cpp1z/init-statement10.C: New test.

From-SVN: r276019

Avoid adding impossible copies in ira-conflicts.c:process_reg_shuffles

If an insn requires two operands to be tied, and the input operand dies
in the insn, IRA acts as though there were a copy from the input to the
output with the same execution frequency as the insn.  Allocating the
same register to the input and the output then saves the cost of a move.

If there is no such tie, but an input operand nevertheless dies
in the insn, IRA creates a similar move, but with an eighth of the
frequency.  This helps to ensure that chains of instructions reuse
registers in a natural way, rather than using arbitrarily different
registers for no reason.

This heuristic seems to work well in the vast majority of cases.
However, for SVE, the handling of untied operands ends up creating
copies between dying predicate registers and vector outputs, even though
vector and predicate registers are distinct classes and can never be
tied.  This is a particular problem because the dying predicate tends
to be the loop control predicate, which is used by most instructions
in a vector loop and so (rightly) has a very high allocation priority.
Any copies involving the loop predicate therefore tend to get processed
before copies involving only vector registers.  The end result is that
we tend to allocate the output of the last vector instruction in a loop
ahead of its natural place in the allocation order and don't benefit
from chains created between vector registers.

This patch tries to avoid the problem by not adding register shuffle
copies if there appears to be no chance that the two operands could be
allocated to the same register.

2019-09-21  Richard Sandiford  <richard.sandiford@arm.com>

gcc/
* ira-conflicts.c (can_use_same_reg_p): New function.
(process_reg_shuffles): Take an insn parameter.  Ignore cases
in which input operand op_num could seemingly never be allocated
to the same register as the destination.
(add_insn_allocno_copies): Update call to process_reg_shuffles.

gcc/testsuite/
* gcc.target/aarch64/sve/cond_convert_1.c: Remove XFAILs.
* gcc.target/aarch64/sve/cond_convert_4.c: Likewise.
* gcc.target/aarch64/sve/cond_unary_2.c: Likewise.

From-SVN: r276018

Extend neg_const_int simplifications to other const rtxes

This patch generalises some neg_const_int-based rtx simplifications
so that they handle all CONST_SCALAR_INTs and also CONST_POLY_INT.
This actually simplifies things a bit, since we no longer have
to treat HOST_WIDE_INT_MIN specially.

This is tested by later SVE patches.

2019-09-21  Richard Sandiford  <richard.sandiford@arm.com>

gcc/
* simplify-rtx.c (neg_const_int): Replace with...
(neg_poly_int_rtx): ...this new function.
(simplify_binary_operation_1): Extend (minus x C) -> (plus X -C)
to all CONST_SCALAR_INTs and to CONST_POLY_INT.
(simplify_plus_minus): Likewise for constant terms here.

From-SVN: r276017

Daily bump.

From-SVN: r276015

microblaze.h (ASM_OUTPUT_SKIP): Use HOST_WIDE_PRINT_UNSIGNED.

* config/microblaze/microblaze.h (ASM_OUTPUT_SKIP): Use
HOST_WIDE_PRINT_UNSIGNED.

From-SVN: r276011

pa.c (pa_trampoline_init): Remove spurious extended character.

* config/pa/pa.c (pa_trampoline_init): Remove spurious extended
character.

From-SVN: r276007

re PR target/86811 (Vax port needs updating for CVE-2017-5753)

PR target/86811
* config/vax/vax.c (TARGET_HAVE_SPECULATION_SAFE_VALUE):
Define to speculation_safe_value_not_needed.

From-SVN: r276006

[Darwin, X86, testsuite] Fix naked-1.c fail.

This fails at m32 because the scan-asm is looking for an absence
of "ret". Darwin is generating the correct code for the function
but the picbase thunk has a 'ret' insn.  Fixed by making the test
use -mdynamic-no-pic for m32.

gcc/testsuite/ChangeLog:

2019-09-20  Iain Sandoe  <iain@sandoe.co.uk>

* gcc.target/i386/naked-1.c: Alter options to use non-
PIC codegen for m32 Darwin.

From-SVN: r276004

re PR fortran/78260 (ICE in gimplify_expr, at gimplify.c:11939)

2019-09-20  Tobias Burnus  <tobias@codesourcery.com>

        PR fortran/78260
        * openmp.c (gfc_resolve_oacc_declare): Reject all
        non variables but accept function result variables.
        * trans-openmp.c (gfc_trans_omp_clauses): Handle
        function-result variables for remaing cases.

2019-09-20  Tobias Burnus  <tobias@codesourcery.com>

        PR fortran/78260
        * gfortran.dg/goacc/parameter.f95: Change
        dg-error as it is now detected earlier.
        * gfortran.dg/goacc/pr85701.f90: Modify to
        use a separate result variable.
        * gfortran.dg/goacc/pr78260.f90: New.
        * gfortran.dg/goacc/pr78260-2.f90: New.
        * gfortran.dg/gomp/pr78260.f90: New.
        * gfortran.dg/gomp/pr78260-2.f90: New.
        * gfortran.dg/gomp/pr78260-3.f90: New.

From-SVN: r276002

Revert [ARM/FDPIC v6 13/24] [ARM] FDPIC: Force LSB bit for PC in Cortex-M architecture

This is causing regressions when mixing with user code compiled in ARM mode.

2019-09-20  Christophe Lyon  <christophe.lyon@st.com>

Revert:
2019-09-10  Christophe Lyon  <christophe.lyon@st.com>
Mickaël Guêné <mickael.guene@st.com>

* config/arm/unwind-arm.c (_Unwind_VRS_Set): Handle thumb-only
architecture.

From-SVN: r276001

Restrict gnat.dg/system_info1.adb to Linux and Windows hosts

Where it is know to work, still covering the original test intent.

From-SVN: r275999

re PR target/91814 (ICE in elimination_costs_in_insn, at reload1.c:3549 since r274926)

2019-09-20  Richard Biener  <rguenther@suse.de>
Uros Bizjak  <ubizjak@gmail.com>

PR target/91814
* config/i386/i386-features.c (gen_gpr_to_xmm_move_src): Revert
previous change.
(general_scalar_chain::convert_op): Force not suitable memory
operands to a register.

Co-Authored-By: Uros Bizjak <ubizjak@gmail.com>
From-SVN: r275998

re PR testsuite/91821 (r275928 breaks gcc.target/powerpc/sad-vectorize-2.c)

2019-09-20  Richard Biener  <rguenther@suse.de>

PR tree-optimization/91821
* tree-vect-loop.c (check_reduction_path): Check we can compute
reduc_idx.
(vect_is_simple_reduction): Set STMT_VINFO_REDUC_IDX.
* tree-vect-patterns.c (vect_reassociating_reduction_p): Return
operands in canonical order.
* tree-vectorizer.c (vec_info::new_stmt_vec_info): Initialize
STMT_VINFO_REDUC_IDX.
* tree-vectorizer.h (_stmt_vec_info::reduc_idx): New.
(STMT_VINFO_REDUC_IDX): Likewise.

From-SVN: r275996

re PR target/91269 (unaligned floating-point register with -mcpu=niagara4 -fcall-used-g6)

PR target/91269
* config/sparc/sparc.h (HARD_REGNO_CALLER_SAVE_MODE): Define.

From-SVN: r275994

re PR c/91815 (questionable error on type definition at file scope)

PR c/91815
* c-decl.c (pushdecl): In C detect duplicate declarations across scopes
of identifiers in the external scope only for variables and functions.

From-SVN: r275992

re PR tree-optimization/91822 (FAIL: gcc.dg/pr88031.c (internal compiler error))

2019-09-20  Richard Biener  <rguenther@suse.de>

PR tree-optimization/91822
* tree-vectorizer.h (vectorizable_condition): Restore for_reduction
parameter.
* tree-vect-loop.c (vectorizable_reduction): Adjust asserts
for reduc_index in nested cycles, adjust vectorizable_condition
calls.
* tree-vect-stmts.c (vectorizable_condition): Restore for_reduction
parameter.
(vect_analyze_stmt): Adjust.
(vect_transform_stmt): Likewise.

From-SVN: r275990

re PR target/91767 (After r274953, clang-compiled xgcc segfaults during RTL pass: stv)

2019-09-20  Richard Biener  <rguenther@suse.de>

PR target/91767
* config/i386/i386-features.c (general_scalar_chain::convert_registers):
Ensure there's a sequence point between allocating the new register
and passing a reference to a reg via regno_reg_rtx.

From-SVN: r275989

Daily bump.

From-SVN: r275986

New IPA-SRA

2019-09-20  Martin Jambor  <mjambor@suse.cz>

        * coretypes.h (cgraph_edge): Declare.
        * ipa-param-manipulation.c: Rewrite.
        * ipa-param-manipulation.h: Likewise.
        * Makefile.in (GTFILES): Added ipa-param-manipulation.h and ipa-sra.c.
        (OBJS): Added ipa-sra.o.
        * cgraph.h (ipa_replace_map): Removed fields old_tree, replace_p
        and ref_p, added fields param_adjustments and performed_splits.
        (struct cgraph_clone_info): Remove ags_to_skip and
        combined_args_to_skip, new field param_adjustments.
        (cgraph_node::create_clone): Changed parameters to use
        ipa_param_adjustments.
        (cgraph_node::create_virtual_clone): Likewise.
        (cgraph_node::create_virtual_clone_with_body): Likewise.
        (tree_function_versioning): Likewise.
        (cgraph_build_function_type_skip_args): Removed.
        * cgraph.c (cgraph_edge::redirect_call_stmt_to_callee): Convert to
        using ipa_param_adjustments.
        (clone_of_p): Likewise.
        * cgraphclones.c (cgraph_build_function_type_skip_args): Removed.
        (build_function_decl_skip_args): Likewise.
        (duplicate_thunk_for_node): Adjust parameters using
        ipa_param_body_adjustments, copy param_adjustments instead of
        args_to_skip.
        (cgraph_node::create_clone): Convert to using ipa_param_adjustments.
        (cgraph_node::create_virtual_clone): Likewise.
        (cgraph_node::create_version_clone_with_body): Likewise.
        (cgraph_materialize_clone): Likewise.
        (symbol_table::materialize_all_clones): Likewise.
        * ipa-fnsummary.c (ipa_fn_summary_t::duplicate): Simplify
        ipa_replace_map check.
        * ipa-cp.c (get_replacement_map): Do not initialize removed fields.
        (initialize_node_lattices): Make aware that some parameters might have
        already been removed.
        (want_remove_some_param_p): New function.
        (create_specialized_node): Convert to using ipa_param_adjustments and
        deal with possibly pre-existing adjustments.
        * lto-cgraph.c (output_cgraph_opt_summary_p): Likewise.
        (output_node_opt_summary): Do not stream removed fields.  Stream
        parameter adjustments instead of argumetns to skip.
        (input_node_opt_summary): Likewise.
        (input_node_opt_summary): Likewise.
        * lto-section-in.c (lto_section_name): Added ipa-sra section.
        * lto-streamer.h (lto_section_type): Likewise.
        * tree-inline.h (copy_body_data): New fields killed_new_ssa_names and
param_body_adjs.
        (copy_decl_to_var): Declare.
        * tree-inline.c (update_clone_info): Do not remap old_tree.
        (remap_gimple_stmt): Use ipa_param_body_adjustments to modify gimple
        statements, walk all extra generated statements and remap their
        operands.
        (redirect_all_calls): Add killed SSA names to a hash set.
        (remap_ssa_name): Do not remap killed SSA names.
        (copy_arguments_for_versioning): Renames to copy_arguments_nochange,
        half of functionality moved to ipa_param_body_adjustments.
        (copy_decl_to_var): Make exported.
        (copy_body): Destroy killed_new_ssa_names hash set.
        (expand_call_inline): Remap performed splits.
        (update_clone_info): Likewise.
        (tree_function_versioning): Simplify tree_map processing.  Updated to
        accept ipa_param_adjustments and use ipa_param_body_adjustments.
        * omp-simd-clone.c (simd_clone_vector_of_formal_parm_types): Adjust
        for the new interface.
        (simd_clone_clauses_extract): Likewise, make args an auto_vec.
        (simd_clone_compute_base_data_type): Likewise.
        (simd_clone_init_simd_arrays): Adjust for the new interface.
        (simd_clone_adjust_argument_types): Likewise.
        (struct modify_stmt_info): Likewise.
        (ipa_simd_modify_stmt_ops): Likewise.
        (ipa_simd_modify_function_body): Likewise.
        (simd_clone_adjust): Likewise.
        * tree-sra.c: Removed IPA-SRA.  Include tree-sra.h.
        (type_internals_preclude_sra_p): Make public.
        * tree-sra.h: New file.
        * ipa-inline-transform.c (save_inline_function_body): Update to
        refelct new tree_function_versioning signature.
        * ipa-prop.c (adjust_agg_replacement_values): Use a helper from
        ipa_param_adjustments to get current parameter indices.
        (ipcp_modif_dom_walker::before_dom_children): Likewise.
        (ipcp_update_bits): Likewise.
        (ipcp_update_vr): Likewise.
        * ipa-split.c (split_function): Convert to using ipa_param_adjustments.
        * ipa-sra.c: New file.
        * multiple_target.c (create_target_clone): Update to reflet new type
        of create_version_clone_with_body.
        * trans-mem.c (ipa_tm_create_version): Update to reflect new type of
        tree_function_versioning.
(modify_function): Update to reflect new type of
tree_function_versioning.
        * params.def (PARAM_IPA_SRA_MAX_REPLACEMENTS): New.
        * passes.def: Remove old IPA-SRA and add new one.
        * tree-pass.h (make_pass_early_ipa_sra): Remove declaration.
        (make_pass_ipa_sra): Declare.
* dbgcnt.def: Remove eipa_sra.  Added ipa_sra_params and
ipa_sra_retvalues.
* doc/invoke.texi (ipa-sra-max-replacements): New.

        testsuite/
        * g++.dg/ipa/pr81248.C: Adjust dg-options and dump-scan.
        * gcc.dg/ipa/ipa-sra-1.c: Likewise.
        * gcc.dg/ipa/ipa-sra-10.c: Likewise.
        * gcc.dg/ipa/ipa-sra-11.c: Likewise.
        * gcc.dg/ipa/ipa-sra-3.c: Likewise.
        * gcc.dg/ipa/ipa-sra-4.c: Likewise.
        * gcc.dg/ipa/ipa-sra-5.c: Likewise.
        * gcc.dg/ipa/ipacost-2.c: Disable ipa-sra.
        * gcc.dg/ipa/ipcp-agg-9.c: Likewise.
        * gcc.dg/ipa/pr78121.c: Adjust scan pattern.
        * gcc.dg/ipa/vrp1.c: Likewise.
        * gcc.dg/ipa/vrp2.c: Likewise.
        * gcc.dg/ipa/vrp3.c: Likewise.
        * gcc.dg/ipa/vrp7.c: Likewise.
        * gcc.dg/ipa/vrp8.c: Likewise.
        * gcc.dg/noreorder.c: use noipa attribute instead of noinline.
        * gcc.dg/ipa/20040703-wpa.c: New test.
* gcc.dg/ipa/ipa-sra-12.c: New test.
* gcc.dg/ipa/ipa-sra-13.c: Likewise.
* gcc.dg/ipa/ipa-sra-14.c: Likewise.
* gcc.dg/ipa/ipa-sra-15.c: Likewise.
* gcc.dg/ipa/ipa-sra-16.c: Likewise.
* gcc.dg/ipa/ipa-sra-17.c: Likewise.
* gcc.dg/ipa/ipa-sra-18.c: Likewise.
* gcc.dg/ipa/ipa-sra-19.c: Likewise.
* gcc.dg/ipa/ipa-sra-20.c: Likewise.
* gcc.dg/ipa/ipa-sra-21.c: Likewise.
* gcc.dg/ipa/ipa-sra-22.c: Likewise.
* gcc.dg/sso/ipa-sra-1.c: Likewise.
* g++.dg/ipa/ipa-sra-2.C: Likewise.
* g++.dg/ipa/ipa-sra-3.C: Likewise.
* gcc.dg/tree-ssa/ipa-cp-1.c: Make return value used.
* g++.dg/ipa/devirt-19.C: Add missing return, add -fipa-cp-clone
option.
* g++.dg/lto/devirt-19_0.C: Add -fipa-cp-clone option.
* gcc.dg/ipa/ipa-sra-2.c: Removed.
* gcc.dg/ipa/ipa-sra-6.c: Likewise.

From-SVN: r275982

PR middle-end/91631 - buffer overflow into an array member of a declared object not detected

gcc/ChangeLog:

PR middle-end/91631
* builtins.c (component_size): Correct trailing array computation,
rename to component_ref_size and move...
(compute_objsize): Adjust.
* gimple-ssa-warn-restrict.c (builtin_memref::refsize): New member.
(builtin_access::strict): Do not consider mememmove.
(builtin_access::write_off): New function.
(builtin_memref::builtin_memref): Initialize refsize.
(builtin_memref::set_base_and_offset): Adjust refoff and compute
refsize.
(builtin_memref::offset_out_of_bounds): Use ooboff input values.
Handle refsize.
(builtin_access::builtin_access): Intialize dstoff to destination
refeence offset here instead of in maybe_diag_overlap.  Adjust
referencess even to unrelated objects. Adjust sizrange of bounded
string functions to reflect bound.  For strcat, adjust destination
sizrange by that of source.
(builtin_access::strcat_overlap):  Adjust offsets and sizes
to reflect the increase in destination sizrange above.
(builtin_access::overlap): Do not set dstoff here but instead
in builtin_access::builtin_access.
(check_bounds_or_overlap): Use builtin_access::write_off.
(maybe_diag_access_bounds): Add argument.  Add informational notes.
(dump_builtin_memref, dump_builtin_access): New functions.
* tree.c (component_ref_size): ...to here.
* tree.h (component_ref_size): Declare.
* tree-ssa-strlen (handle_builtin_strcat): Include the terminating
nul in the size of the source string.

gcc/testsuite/ChangeLog:

PR middle-end/91631
* /c-c++-common/Warray-bounds-3.c: Correct expected offsets.
* /c-c++-common/Warray-bounds-4.c: Same.
* gcc.dg/Warray-bounds-39.c: Remove xfails.
* gcc.dg/Warray-bounds-45.c: New test.
* gcc.dg/Warray-bounds-46.c: New test.

From-SVN: r275981

Support extended characters in C/C++ identifiers (PR c/67224)

libcpp/ChangeLog
2019-09-19  Lewis Hyatt  <lhyatt@gmail.com>

PR c/67224
* charset.c (_cpp_valid_utf8): New function to help lex UTF-8 tokens.
* internal.h (_cpp_valid_utf8): Declare.
* lex.c (forms_identifier_p): Use it to recognize UTF-8 identifiers.
(_cpp_lex_direct): Handle UTF-8 in identifiers and CPP_OTHER tokens.
Do all work in "default" case to avoid slowing down typical code paths.
Also handle $ and UCN in the default case for consistency.

gcc/Changelog
2019-09-19  Lewis Hyatt  <lhyatt@gmail.com>

PR c/67224
* doc/cpp.texi: Document support for extended characters in
identifiers.
* doc/cppopts.texi: Likewise.

gcc/testsuite/ChangeLog
2019-09-19  Lewis Hyatt  <lhyatt@gmail.com>

PR c/67224
* c-c++-common/cpp/ucnid-2011-1-utf8.c: New test.
* g++.dg/cpp/ucnid-1-utf8.C: New test.
* g++.dg/cpp/ucnid-2-utf8.C: New test.
* g++.dg/cpp/ucnid-3-utf8.C: New test.
* g++.dg/cpp/ucnid-4-utf8.C: New test.
* g++.dg/other/ucnid-1-utf8.C: New test.
* gcc.dg/cpp/ucnid-1-utf8.c: New test.
* gcc.dg/cpp/ucnid-10-utf8.c: New test.
* gcc.dg/cpp/ucnid-11-utf8.c: New test.
* gcc.dg/cpp/ucnid-12-utf8.c: New test.
* gcc.dg/cpp/ucnid-13-utf8.c: New test.
* gcc.dg/cpp/ucnid-14-utf8.c: New test.
* gcc.dg/cpp/ucnid-15-utf8.c: New test.
* gcc.dg/cpp/ucnid-2-utf8.c: New test.
* gcc.dg/cpp/ucnid-3-utf8.c: New test.
* gcc.dg/cpp/ucnid-4-utf8.c: New test.
* gcc.dg/cpp/ucnid-6-utf8.c: New test.
* gcc.dg/cpp/ucnid-7-utf8.c: New test.
* gcc.dg/cpp/ucnid-9-utf8.c: New test.
* gcc.dg/ucnid-1-utf8.c: New test.
* gcc.dg/ucnid-10-utf8.c: New test.
* gcc.dg/ucnid-11-utf8.c: New test.
* gcc.dg/ucnid-12-utf8.c: New test.
* gcc.dg/ucnid-13-utf8.c: New test.
* gcc.dg/ucnid-14-utf8.c: New test.
* gcc.dg/ucnid-15-utf8.c: New test.
* gcc.dg/ucnid-16-utf8.c: New test.
* gcc.dg/ucnid-2-utf8.c: New test.
* gcc.dg/ucnid-3-utf8.c: New test.
* gcc.dg/ucnid-4-utf8.c: New test.
* gcc.dg/ucnid-5-utf8.c: New test.
* gcc.dg/ucnid-6-utf8.c: New test.
* gcc.dg/ucnid-7-utf8.c: New test.
* gcc.dg/ucnid-8-utf8.c: New test.
* gcc.dg/ucnid-9-utf8.c: New test.

From-SVN: r275979

Handle [[likely]] on compound-statement.

I overlooked this case when adding [[likely]] handling to
cp_parser_statement.

* parser.c (cp_parser_statement): Handle [[likely]] on
compound-statement.

From-SVN: r275978

[Darwin, PPC, testsuite] Fix pr89313.c fail.

Darwin defines '__POWERPC__' rather than '__powerpc__' so check for
the upper case version too in order to select the correct register
name.

gcc/testsuite:

2019-09-19  Iain Sandoe  <iain@sandoe.co.uk>

* gcc.dg/pr89313.c: Test for __POWERPC__ in addition to
__powerpc__ in register name selection.

From-SVN: r275977

Revert "Fix conversions for built-in operator overloading candidates."

This reverts commit 948d5b831affef14a49f56804b01e3f1ba00cdb3.

From-SVN: r275976

tree-vect-loop.c (vect_is_slp_reduction): Remove.

2019-09-19  Richard Biener  <rguenther@suse.de>

* tree-vect-loop.c (vect_is_slp_reduction): Remove.
(check_reduction_path): New overload having the path as result.
(vect_is_simple_reduction): From the detected reduction
path build a SLP reduction chain if possible.

From-SVN: r275972

re PR target/91814 (ICE in elimination_costs_in_insn, at reload1.c:3549 since r274926)

2019-09-19  Richard Biener  <rguenther@suse.de>

PR target/91814
* config/i386/i386-features.c (gen_gpr_to_xmm_move_src):
Force operand to a register if it isn't nonimmediate_operand.

From-SVN: r275971

[ARM] Simplify logical DImode iterators

Further simplify the logical DImode expander using code iterator and
obtab attributes.  This avoids adding unnecessary code_attr entries.

    gcc/
* config/arm/arm.md (<logical_op>di3): Use <optab> and <CODE>.
* config/arm/iterators.md (optab): Add and, ior, xor entries.
(logical_op): Remove code attribute.
(logical_OP): Likewise.

From-SVN: r275970

Fix cast in sort_congruence_class_groups_by_decl_uid.

2019-09-19  Martin Liska  <mliska@suse.cz>

* ipa-icf.c (sort_congruence_class_groups_by_decl_uid):
Use proper casting.

From-SVN: r275969

aarch64: Implement -moutline-atomics

* config/aarch64/aarch64.opt (-moutline-atomics): New.
* config/aarch64/aarch64.c (aarch64_atomic_ool_func): New.
(aarch64_ool_cas_names, aarch64_ool_swp_names): New.
(aarch64_ool_ldadd_names, aarch64_ool_ldset_names): New.
(aarch64_ool_ldclr_names, aarch64_ool_ldeor_names): New.
(aarch64_expand_compare_and_swap): Honor TARGET_OUTLINE_ATOMICS.
* config/aarch64/atomics.md (atomic_exchange<ALLI>): Likewise.
(atomic_<atomic_op><ALLI>): Likewise.
(atomic_fetch_<atomic_op><ALLI>): Likewise.
(atomic_<atomic_op>_fetch<ALLI>): Likewise.
* doc/invoke.texi: Document -moutline-atomics.
testsuite/
* gcc.target/aarch64/atomic-op-acq_rel.c: Use -mno-outline-atomics.
* gcc.target/aarch64/atomic-comp-swap-release-acquire.c: Likewise.
* gcc.target/aarch64/atomic-op-acquire.c: Likewise.
* gcc.target/aarch64/atomic-op-char.c: Likewise.
* gcc.target/aarch64/atomic-op-consume.c: Likewise.
* gcc.target/aarch64/atomic-op-imm.c: Likewise.
* gcc.target/aarch64/atomic-op-int.c: Likewise.
* gcc.target/aarch64/atomic-op-long.c: Likewise.
* gcc.target/aarch64/atomic-op-relaxed.c: Likewise.
* gcc.target/aarch64/atomic-op-release.c: Likewise.
* gcc.target/aarch64/atomic-op-seq_cst.c: Likewise.
* gcc.target/aarch64/atomic-op-short.c: Likewise.
* gcc.target/aarch64/atomic_cmp_exchange_zero_reg_1.c: Likewise.
* gcc.target/aarch64/atomic_cmp_exchange_zero_strong_1.c: Likewise.
* gcc.target/aarch64/sync-comp-swap.c: Likewise.
* gcc.target/aarch64/sync-op-acquire.c: Likewise.
* gcc.target/aarch64/sync-op-full.c: Likewise.

From-SVN: r275968

aarch64: Add out-of-line functions for LSE atomics

This is the libgcc part of the interface -- providing the functions.
Rationale is provided at the top of libgcc/config/aarch64/lse.S.

* config/aarch64/lse-init.c: New file.
* config/aarch64/lse.S: New file.
* config/aarch64/t-lse: New file.
* config.host: Add t-lse to all aarch64 tuples.

From-SVN: r275967