Luke Kenneth Casson Leighton [Fri, 16 Jul 2021 16:14:06 +0000 (17:14 +0100)]
add fft makefile
Luke Kenneth Casson Leighton [Fri, 16 Jul 2021 15:59:41 +0000 (16:59 +0100)]
add nayuki project reference code
https://www.nayuki.io/page/free-small-fft-in-multiple-languages
Luke Kenneth Casson Leighton [Thu, 15 Jul 2021 18:07:38 +0000 (19:07 +0100)]
use coincidence of svremap "persistence" to remove one more instruction
from FFT example
Luke Kenneth Casson Leighton [Thu, 15 Jul 2021 17:58:34 +0000 (18:58 +0100)]
enable use of svremap "persist" mode, remove 4 instructions from FFT example
Luke Kenneth Casson Leighton [Thu, 15 Jul 2021 17:49:45 +0000 (18:49 +0100)]
stop using MSR vfirst bit, move to SVSTATE bit 63 instead
Luke Kenneth Casson Leighton [Thu, 15 Jul 2021 17:44:13 +0000 (18:44 +0100)]
add extra "persistence" bit to svremap instruction
Luke Kenneth Casson Leighton [Thu, 15 Jul 2021 12:51:08 +0000 (13:51 +0100)]
big intrusive update: merge SVREMAP with SVSTATE, remove SVREMAP
this also involved creating an SVP64State class similar to the REMAPP
class (now removed).
unit tests had to be altered to the new API
Luke Kenneth Casson Leighton [Wed, 14 Jul 2021 20:37:38 +0000 (21:37 +0100)]
use fmadds and fmsubs in complex fft example
reduces inner loop instruction count by 2
Luke Kenneth Casson Leighton [Wed, 14 Jul 2021 19:01:24 +0000 (20:01 +0100)]
update SVSTATE to 64 bit length
Luke Kenneth Casson Leighton [Wed, 14 Jul 2021 18:29:49 +0000 (19:29 +0100)]
subtract one from SVi field for setvl assembler
update all uses to match
Luke Kenneth Casson Leighton [Tue, 13 Jul 2021 16:24:30 +0000 (17:24 +0100)]
change order of log printout for "writing gpr NN"
Luke Kenneth Casson Leighton [Mon, 12 Jul 2021 20:02:55 +0000 (21:02 +0100)]
successful complex FFT butterfly, in-place, using Vertical-First SVP64
Luke Kenneth Casson Leighton [Mon, 12 Jul 2021 14:20:02 +0000 (15:20 +0100)]
add a Discrete FFT butterfly unit test as an intermediary (incremental)
step towards full complex butterfly.
this test uses fp24 as an intermediary for storing the result of the
multiply, source from butterfly-scheduled operands.
that scalar reg is then used as a source in a butterfly-scheduled
twin +/- in-place ADD-SUB
Luke Kenneth Casson Leighton [Sun, 11 Jul 2021 23:02:00 +0000 (00:02 +0100)]
minor reordering of setvl and svshape: svshape is now capable of setting VL
Luke Kenneth Casson Leighton [Sun, 11 Jul 2021 19:17:51 +0000 (20:17 +0100)]
add svremap instruction into ISACaller
alter FFT and Matrix-Multiply SVP64 tests to use new svremap
generic redirect of any register to a SVSHAPE(0-3) rather than hard-coded
Luke Kenneth Casson Leighton [Sun, 11 Jul 2021 17:49:42 +0000 (18:49 +0100)]
update svremap instruction to correctly store immediate args in SPR
Luke Kenneth Casson Leighton [Sun, 11 Jul 2021 16:11:27 +0000 (17:11 +0100)]
whoops
0b00002 is not binary
Luke Kenneth Casson Leighton [Sun, 11 Jul 2021 16:09:44 +0000 (17:09 +0100)]
add SVREMAP new Form / Fields and CSV entry
Luke Kenneth Casson Leighton [Sun, 11 Jul 2021 15:08:00 +0000 (16:08 +0100)]
add SVREMAP SPR to ISACaller and parser
Luke Kenneth Casson Leighton [Sun, 11 Jul 2021 15:02:15 +0000 (16:02 +0100)]
add SVREMAP SPR
Luke Kenneth Casson Leighton [Sun, 11 Jul 2021 11:35:08 +0000 (12:35 +0100)]
add SVP64REMAP Record
Luke Kenneth Casson Leighton [Sun, 11 Jul 2021 11:34:50 +0000 (12:34 +0100)]
rename SVP64REMAP to SVP64SHAPE
Luke Kenneth Casson Leighton [Sun, 11 Jul 2021 11:22:03 +0000 (12:22 +0100)]
rename svremap to svshape
Luke Kenneth Casson Leighton [Sun, 11 Jul 2021 11:17:50 +0000 (12:17 +0100)]
rename svremap to svshape
Luke Kenneth Casson Leighton [Sat, 10 Jul 2021 16:25:25 +0000 (17:25 +0100)]
add scalar ffadds unit test
Luke Kenneth Casson Leighton [Sat, 10 Jul 2021 16:24:10 +0000 (17:24 +0100)]
whoops forgot elif in SVP64Asm translation, detection of ffmadds overwritten
Luke Kenneth Casson Leighton [Sat, 10 Jul 2021 16:08:24 +0000 (17:08 +0100)]
in scalar case do not increment RB for FFT mode
Luke Kenneth Casson Leighton [Sat, 10 Jul 2021 11:37:20 +0000 (12:37 +0100)]
add sv.ffadds unit test, inversion of subtract needed in svfparith pseudocode
Luke Kenneth Casson Leighton [Sat, 10 Jul 2021 11:36:43 +0000 (12:36 +0100)]
more generic allow fft mode 2nd output detection. REALLY need a CSV Out2 column
Luke Kenneth Casson Leighton [Sat, 10 Jul 2021 11:11:19 +0000 (12:11 +0100)]
add ffadds decoding:
- SVP64 trans manual creation of opcode with XO=
0b01101
- add to power enums ISA list
- add to minor 59 and SVP64 CSV
Luke Kenneth Casson Leighton [Sat, 10 Jul 2021 11:10:08 +0000 (12:10 +0100)]
add more generic detection of FFT mode, really needs to be a new column in CSV file for Out2
Luke Kenneth Casson Leighton [Sat, 10 Jul 2021 11:09:10 +0000 (12:09 +0100)]
add (disabled) FFT complex unit test under development
Luke Kenneth Casson Leighton [Sat, 10 Jul 2021 10:46:49 +0000 (11:46 +0100)]
corrections to remaining fft madd/msub
Luke Kenneth Casson Leighton [Fri, 9 Jul 2021 18:42:16 +0000 (19:42 +0100)]
update comments
Luke Kenneth Casson Leighton [Fri, 9 Jul 2021 16:12:37 +0000 (17:12 +0100)]
for scalar destination or scalar source on ffmadd, only offset by one
Luke Kenneth Casson Leighton [Fri, 9 Jul 2021 16:03:31 +0000 (17:03 +0100)]
add svstep variant of fpmadds fft test
Luke Kenneth Casson Leighton [Fri, 9 Jul 2021 15:52:37 +0000 (16:52 +0100)]
add "odd" SVP64 unit tests which alter SVSTATE
Luke Kenneth Casson Leighton [Fri, 9 Jul 2021 11:48:57 +0000 (12:48 +0100)]
comments in unit test
Luke Kenneth Casson Leighton [Fri, 9 Jul 2021 11:44:22 +0000 (12:44 +0100)]
add Vertical-First explicit branch-loop using svstep, with an sv.add. works!
Luke Kenneth Casson Leighton [Thu, 8 Jul 2021 22:09:49 +0000 (23:09 +0100)]
end SVP64 "Vertical First" mode on rollover when end of svstep reached
Luke Kenneth Casson Leighton [Thu, 8 Jul 2021 22:04:51 +0000 (23:04 +0100)]
add CR0 setting and unit test on svstep
Luke Kenneth Casson Leighton [Thu, 8 Jul 2021 21:34:29 +0000 (22:34 +0100)]
whoops asmcode length (number of instructions) went over 256, caused
asmcode in simulator to "wrap" and get the wrong instruction name,
and then execute totally the wrong simulated instruction
Luke Kenneth Casson Leighton [Thu, 8 Jul 2021 21:26:30 +0000 (22:26 +0100)]
test MSR.SVF bit set after setvl Vertical-First mode set
Luke Kenneth Casson Leighton [Thu, 8 Jul 2021 21:10:03 +0000 (22:10 +0100)]
whoops must not reset last_op_svstate except when out of SVP64 mode
Luke Kenneth Casson Leighton [Thu, 8 Jul 2021 21:03:55 +0000 (22:03 +0100)]
testing new setvl "svstep" mode
Luke Kenneth Casson Leighton [Thu, 8 Jul 2021 20:46:56 +0000 (21:46 +0100)]
whoops sv.lfs registers must be even numbers (match SVP6 EXTRA2 encoding)
Luke Kenneth Casson Leighton [Thu, 8 Jul 2021 18:02:37 +0000 (19:02 +0100)]
add ability to explicitly increment SVSTATE srcstep/dststep
Luke Kenneth Casson Leighton [Thu, 8 Jul 2021 15:21:49 +0000 (16:21 +0100)]
add (new) extra argument to setvl (Vertical-First mode, set to zero here)
Luke Kenneth Casson Leighton [Thu, 8 Jul 2021 15:12:14 +0000 (16:12 +0100)]
add in extra "vertical" mode into SVP64 setvl
Luke Kenneth Casson Leighton [Wed, 7 Jul 2021 15:43:40 +0000 (16:43 +0100)]
clean up imports and unit test name
Luke Kenneth Casson Leighton [Wed, 7 Jul 2021 15:31:08 +0000 (16:31 +0100)]
ffmuls test, had to add to b not a in expected results
Luke Kenneth Casson Leighton [Wed, 7 Jul 2021 15:27:46 +0000 (16:27 +0100)]
get butterfly RADIX2 SVP64 example working, breaks the fpmadds one though
Luke Kenneth Casson Leighton [Wed, 7 Jul 2021 13:07:27 +0000 (14:07 +0100)]
add in DFT test from Project Nayuki to verify results of butterfly schedule
Luke Kenneth Casson Leighton [Tue, 6 Jul 2021 20:15:02 +0000 (21:15 +0100)]
change coefficients in FFT REMAP example so as not to get alternating zeros
Luke Kenneth Casson Leighton [Tue, 6 Jul 2021 20:14:33 +0000 (21:14 +0100)]
when REMAP shape is zero, skip it in ISACaller.
also use srcstep only for FFT butterfly mode (for now)
bit of a hack
Luke Kenneth Casson Leighton [Tue, 6 Jul 2021 20:13:50 +0000 (21:13 +0100)]
on FRS for FFT with REMAP use scheduled offset
Luke Kenneth Casson Leighton [Tue, 6 Jul 2021 19:34:40 +0000 (20:34 +0100)]
add FFT REMAP butterfly unit test
Luke Kenneth Casson Leighton [Tue, 6 Jul 2021 18:55:41 +0000 (19:55 +0100)]
add FFT SHAPE pseudocode in svremap, and a schedule in ISACaller
Luke Kenneth Casson Leighton [Tue, 6 Jul 2021 16:03:53 +0000 (17:03 +0100)]
add FFT butterfly iteration to SVSHAPE REMAP class for ISACaller
Luke Kenneth Casson Leighton [Tue, 6 Jul 2021 16:03:16 +0000 (17:03 +0100)]
when FFT madd detected, only enable VL offset in non-REMAP mode
Luke Kenneth Casson Leighton [Mon, 5 Jul 2021 22:16:11 +0000 (23:16 +0100)]
add 2nd matrix multiply unit test with SV REMAP
Luke Kenneth Casson Leighton [Mon, 5 Jul 2021 21:29:51 +0000 (22:29 +0100)]
fix ISACaller FFT-enable detection, fixes sv.fmadds, matrix multiply works
Luke Kenneth Casson Leighton [Mon, 5 Jul 2021 21:03:15 +0000 (22:03 +0100)]
fix svremap field offsets
Luke Kenneth Casson Leighton [Mon, 5 Jul 2021 19:07:49 +0000 (20:07 +0100)]
whoops, REMAP inverted
Luke Kenneth Casson Leighton [Mon, 5 Jul 2021 19:01:18 +0000 (20:01 +0100)]
debug of SVP64 REMAP
Luke Kenneth Casson Leighton [Mon, 5 Jul 2021 18:36:01 +0000 (19:36 +0100)]
debugging SVSHAPE for REMAP
Luke Kenneth Casson Leighton [Mon, 5 Jul 2021 18:02:18 +0000 (19:02 +0100)]
add in use of SVSHAPE in ISACaller. untested (no damage done)
Luke Kenneth Casson Leighton [Mon, 5 Jul 2021 17:45:46 +0000 (18:45 +0100)]
add redirection "steps" for REMAP purposes, to be set up manually
in ISACaller for now
Luke Kenneth Casson Leighton [Mon, 5 Jul 2021 17:33:17 +0000 (18:33 +0100)]
add last_op_svshape flag to ISACaller
Luke Kenneth Casson Leighton [Mon, 5 Jul 2021 16:28:31 +0000 (17:28 +0100)]
add svremap manual instruction (Primary Opcode 22, sandbox)
Luke Kenneth Casson Leighton [Mon, 5 Jul 2021 14:53:18 +0000 (15:53 +0100)]
add SVSHAPE class, starting to add to ISACaller
Luke Kenneth Casson Leighton [Mon, 5 Jul 2021 13:30:50 +0000 (14:30 +0100)]
add function to turn permute into an order list
Luke Kenneth Casson Leighton [Mon, 5 Jul 2021 13:18:54 +0000 (14:18 +0100)]
update SVREMAP to match spec
Luke Kenneth Casson Leighton [Fri, 2 Jul 2021 12:45:31 +0000 (13:45 +0100)]
add basic README for media tests
Luke Kenneth Casson Leighton [Thu, 1 Jul 2021 17:12:13 +0000 (18:12 +0100)]
add temporary SV pseudocode
Luke Kenneth Casson Leighton [Thu, 1 Jul 2021 14:17:35 +0000 (15:17 +0100)]
add TEMPORARY svremap form and instruction
Luke Kenneth Casson Leighton [Tue, 29 Jun 2021 15:22:17 +0000 (16:22 +0100)]
re-enable accidentally-disabled sv ld/st tests
Luke Kenneth Casson Leighton [Tue, 29 Jun 2021 15:18:51 +0000 (16:18 +0100)]
corrections to comments and map-reduce adds, wrong way round
(not a prefix-sum)
Luke Kenneth Casson Leighton [Tue, 29 Jun 2021 15:16:32 +0000 (16:16 +0100)]
tab replacement
Luke Kenneth Casson Leighton [Mon, 28 Jun 2021 18:35:17 +0000 (19:35 +0100)]
add some notes into imdct_standalone.c
Luke Kenneth Casson Leighton [Mon, 28 Jun 2021 18:12:03 +0000 (19:12 +0100)]
morph imdct36 standalone c to look like it uses predication
loop can now be 5-long
Luke Kenneth Casson Leighton [Mon, 28 Jun 2021 18:03:26 +0000 (19:03 +0100)]
add copy of imdct36 standalone c test
Luke Kenneth Casson Leighton [Mon, 28 Jun 2021 14:15:03 +0000 (15:15 +0100)]
add extra offset for FRB, for FFT Cooley-Tukey twin mul/add-sub
Luke Kenneth Casson Leighton [Sun, 27 Jun 2021 17:39:11 +0000 (18:39 +0100)]
add new SVP64 FFT twin multiply-and-accumulate unit test
Luke Kenneth Casson Leighton [Sun, 27 Jun 2021 17:38:45 +0000 (18:38 +0100)]
add new (experimental) ffmadds and ffmsubs, for FFT twin mul-accumulate
Luke Kenneth Casson Leighton [Sun, 27 Jun 2021 13:26:09 +0000 (14:26 +0100)]
override logic for getting FRS in SVP64 FFT mode
Luke Kenneth Casson Leighton [Sun, 27 Jun 2021 12:52:25 +0000 (13:52 +0100)]
add FRS decode (2nd output) for SVP64 FFT FP mul-add in PowerDecoder2
Luke Kenneth Casson Leighton [Sun, 27 Jun 2021 12:46:51 +0000 (13:46 +0100)]
change name to OP_FP_MADD to identify fmadd (etc)
Luke Kenneth Casson Leighton [Sun, 27 Jun 2021 12:46:19 +0000 (13:46 +0100)]
comments on SVP64 LD/ST Mode detection
Luke Kenneth Casson Leighton [Sun, 27 Jun 2021 12:22:04 +0000 (13:22 +0100)]
add SVP64 FFT mode to PowerDecoder, add CSV entries
Luke Kenneth Casson Leighton [Sat, 26 Jun 2021 17:42:56 +0000 (18:42 +0100)]
add LD bit-reversed unit test
add LD/ST bit-reverse logic in ISACaller
Luke Kenneth Casson Leighton [Sat, 26 Jun 2021 14:14:44 +0000 (15:14 +0100)]
comment out l*br pseudo-ops from power_enums.py
Luke Kenneth Casson Leighton [Sat, 26 Jun 2021 12:37:25 +0000 (13:37 +0100)]
use If Elif in power_decoder conditions, a lot easier than switch/case
Luke Kenneth Casson Leighton [Sat, 26 Jun 2021 12:36:56 +0000 (13:36 +0100)]
rename bit-reversed LDs to match v3.0B (strip "br")
Luke Kenneth Casson Leighton [Sat, 26 Jun 2021 09:39:32 +0000 (10:39 +0100)]
move D const update to after picking up main input registers
Luke Kenneth Casson Leighton [Fri, 25 Jun 2021 18:18:35 +0000 (19:18 +0100)]
identify SVP64 LD bit-reverse pattern as pseudo-assembler
rewrite it before it gets too far into SVP64Asm
morph any "sv.ldxxxxbr" into "sv.ld/br" and rewrite the fields
Luke Kenneth Casson Leighton [Fri, 25 Jun 2021 18:12:13 +0000 (19:12 +0100)]
only set conditions in PowerDecoder2 for svp64 mode
Luke Kenneth Casson Leighton [Fri, 25 Jun 2021 13:42:55 +0000 (14:42 +0100)]
update sv_analysis.py to match new CONDITIONs field in CSV files
Luke Kenneth Casson Leighton [Fri, 25 Jun 2021 13:42:23 +0000 (14:42 +0100)]
rename svp64 bit-reversed LD instructions to not conflict with v3.0B
Luke Kenneth Casson Leighton [Thu, 24 Jun 2021 21:17:02 +0000 (22:17 +0100)]
whoops SVP64 bit-rev LDs need to use SVD and SVDS immediate not D and DS