Andreas Hansson [Wed, 10 Feb 2016 09:08:24 +0000 (04:08 -0500)]
mem: Align how snoops are handled when hitting writebacks
This patch unifies the snoop handling in case of hitting writebacks
with how we handle snoops hitting in the tags. As a result, we end up
using the same optimisation as the normal snoops, where we inform the
downstream cache if we encounter a line in Modified (writable and
dirty) state, which enables us to avoid sending out express snoops to
invalidate any Shared copies of the line. A few regressions
consequently change, as some transactions are sunk higher up in the
cache hierarchy.
Andreas Hansson [Wed, 10 Feb 2016 09:08:24 +0000 (04:08 -0500)]
mem: Deduce if cache should forward snoops
This patch changes how the cache determines if snoops should be
forwarded from the memory side to the CPU side. Instead of having a
parameter, the cache now looks at the port connected on the CPU side,
and if it is a snooping port, then snoops are forwarded. Less error
prone, and less parameters to worry about.
The patch also tidies up the CPU classes to ensure that their I-side
port is not snooping by removing overrides to the snoop request
handler, such that snoop requests will panic via the default
MasterPort implement
Curtis Dunham [Mon, 8 Feb 2016 19:39:45 +0000 (13:39 -0600)]
scons: always generate sim/tags.cc
Due to insufficient build deps, the checkpoint tags might not get
updated; this commit solves this. Due to the uncommon nature of the
build target, regenerating tags.cc is a fairly clean solution. Since
SCons hashes file contents, it won't recompile anything unless a new
checkpoint upgrader is actually added.
--HG--
extra : amend_source :
ed3879da7668554693f697076deaf5029cc9b954
Alexandru Dutu [Sun, 7 Feb 2016 01:21:20 +0000 (17:21 -0800)]
x86: revamp cmpxchg8b/cmpxchg16b implementation
The previous implementation did a pair of nested RMW operations,
which isn't compatible with the way that locked RMW operations are
implemented in the cache models. It was convenient though in that
it didn't require any new micro-ops, and supported cmpxchg16b using
64-bit memory ops. It also worked in AtomicSimpleCPU where
atomicity was guaranteed by the core and not by the memory system.
It did not work with timing CPU models though.
This new implementation defines new 'split' load and store micro-ops
which allow a single memory operation to use a pair of registers as
the source or destination, then uses a single ldsplit/stsplit RMW
pair to implement cmpxchg. This patch requires support for 128-bit
memory accesses in the ISA (added via a separate patch) to support
cmpxchg16b.
Steve Reinhardt [Sun, 7 Feb 2016 01:21:20 +0000 (17:21 -0800)]
arch, x86: add support for arrays as memory operands
Although the cache models support wider accesses, the ISA descriptions
assume that (for the most part) memory operands are integer types,
which makes it difficult to define instructions that do memory accesses
larger than 64 bits.
This patch adds some generic support for memory operands that are arrays
of uint64_t, and specifically a 'u2qw' operand type for x86 that is an
array of 2 uint64_ts (128 bits). This support is unused at this point,
but will be needed shortly for cmpxchg16b. Ideally the 128-bit SSE
memory accesses will also be rewritten to use this support.
Support for 128-bit accesses could also have been added using the gcc
__int128_t extension, which would have been less disruptive. However,
although clang also supports __int128_t, it's still non-standard.
Also, more importantly, this approach creates a path to defining
256- and 512-byte operands as well, which will be useful for eventual
AVX support.
Steve Reinhardt [Sun, 7 Feb 2016 01:21:20 +0000 (17:21 -0800)]
arch: get rid of dummy var init
MemOperand variables were being initialized to 0
"to avoid 'uninitialized variable' errors" but these
no longer seem to be a problem (with the exception of
one use case in POWER that is arguably broken and
easily fixed here).
Getting rid of the initialization is necessary to
set up a subsequent patch which extends memory
operands to possibly not be scalars, making the
'= 0' initialization no longer feasible.
Steve Reinhardt [Sun, 7 Feb 2016 01:21:20 +0000 (17:21 -0800)]
syscall_emul: fix bug in aux vector initialization
Writing 16 bytes from an 8-byte source value is a bad idea.
This doesn't appear to have broken anything, but showed up
as spurious differences when tracediffing runs.
Steve Reinhardt [Sun, 7 Feb 2016 01:21:20 +0000 (17:21 -0800)]
style: eliminate explicit boolean comparisons
Result of running 'hg m5style --skip-all --fix-control -a' to get
rid of '== true' comparisons, plus trivial manual edits to get
rid of '== false'/'== False' comparisons.
Left a couple of explicit comparisons in where they didn't seem
unreasonable:
invalid boolean comparison in src/arch/mips/interrupts.cc:155
>> DPRINTF(Interrupt, "Interrupts OnCpuTimerINterrupt(tc) == true\n");<<
invalid boolean comparison in src/unittest/unittest.hh:110
>> "EXPECT_FALSE(" #expr ")", (expr) == false)<<
Steve Reinhardt [Sun, 7 Feb 2016 01:21:20 +0000 (17:21 -0800)]
x86: create function to check miscreg validity
In the process of trying to get rid of an '== false' comparison,
it became apparent that a slightly more involved solution was
needed. Split this out into its own changeset since it's not
a totally trivial local change like the others.
Steve Reinhardt [Sun, 7 Feb 2016 01:21:20 +0000 (17:21 -0800)]
util: fix apparent statetrace bug
In the process of trying to eliminate boolean comparisons,
I ran across this statement that appears to be a bug
(should have been an assignment).
Steve Reinhardt [Sun, 7 Feb 2016 01:21:20 +0000 (17:21 -0800)]
util: added line length and boolean comparison style checkers
Added checkers for line length and boolean comparisons
(== true/== false) to the style script.
Steve Reinhardt [Sun, 7 Feb 2016 01:21:19 +0000 (17:21 -0800)]
style: fix missing spaces in control statements
Result of running 'hg m5style --skip-all --fix-control -a'.
Steve Reinhardt [Sun, 7 Feb 2016 01:21:18 +0000 (17:21 -0800)]
style: remove trailing whitespace
Result of running 'hg m5style --skip-all --fix-white -a'.
Steve Reinhardt [Sun, 7 Feb 2016 01:21:18 +0000 (17:21 -0800)]
util: clean up and extend style checker
Added a new Verifier object to check for and fix spacing
between if/while/for and following paren.
Restructured Verifier class to make it easier to add
new subclasses, particularly by using a global list of
verifiers to auto-generate command line options and
simplify the invocation loop.
Steve Reinhardt [Sun, 7 Feb 2016 01:21:18 +0000 (17:21 -0800)]
util: delete old unused style-checking scripts
The functions in these scripts were apparently folded into style.py but the
old scripts were orphaned without being deleted. Get rid of them so their
existence is no longer confusing.
Mohammad Alian [Sat, 6 Feb 2016 18:33:34 +0000 (13:33 -0500)]
dist, dev: add an ethernet switch model
Steve Reinhardt [Sat, 6 Feb 2016 06:35:03 +0000 (01:35 -0500)]
stats: update EIO stats for recent changes
Curtis Dunham [Thu, 4 Feb 2016 22:57:59 +0000 (16:57 -0600)]
ext: fix SST connector
Should work with SST 5.1 and trunk as of right now.
Curtis Dunham [Fri, 29 Jan 2016 23:47:15 +0000 (17:47 -0600)]
ext: remove redundant parameter in example SST+gem5 test
The SST connector automatically adds --initialize-only to the gem5
"command line" (as it should); the config script doesn't need it.
Andreas Sandberg [Fri, 29 Jan 2016 12:14:21 +0000 (12:14 +0000)]
ext: Update NoMali to external rev
f08e0a5
Update NoMali from external revision
9adf9d6 to
f08e0a5 and bring in
the following changes:
f08e0a5 Add support for tracking address space state
f11099e Fix job slot register handling when running new jobs
b28c98e api: Add a reset callback
29ac4c3 tests: Update gitignore to cover all future test cases
1c6b893 Propagate reset calls to all job slots
8f8ec15 Remove redundant reg vector in MMU
85d90d2 tests: Fix incorrect extern declaration
Tony Gutierrez [Fri, 22 Jan 2016 15:42:13 +0000 (10:42 -0500)]
stats: update stats to after GPU checkin
Brad Beckmann [Fri, 22 Jan 2016 15:42:12 +0000 (10:42 -0500)]
ruby: removed Write_Only AccessPermission
Brad Beckmann [Fri, 22 Jan 2016 15:42:12 +0000 (10:42 -0500)]
ruby: changed all references to numCPs to num-cp
David Hashe [Mon, 20 Jul 2015 14:15:18 +0000 (09:15 -0500)]
ruby: split CPU and GPU latency stats
Tony Gutierrez [Tue, 19 Jan 2016 19:28:22 +0000 (14:28 -0500)]
gpu-compute: AMD's baseline GPU model
Tony Gutierrez [Tue, 19 Jan 2016 19:05:03 +0000 (14:05 -0500)]
mem: write combining for ruby protocols
This patch adds support for write-combining in ruby.
Tony Gutierrez [Tue, 19 Jan 2016 18:57:50 +0000 (13:57 -0500)]
* * *
mem: support for gpu-style RMWs in ruby
This patch adds support for GPU-style read-modify-write (RMW) operations in
ruby. Such atomic operations are traditionally executed at the memory controller
(instead of through an L1 cache using cache-line locking).
Currently, this patch works by propogating operation functors through the memory
system.
Blake Hechtman [Mon, 20 Jul 2015 14:15:18 +0000 (09:15 -0500)]
mem: misc flags for AMD gpu model
This patch add support to mark memory requests/packets with attributes defined
in HSA, such as memory order and scope.
Steve Reinhardt [Mon, 18 Jan 2016 03:18:49 +0000 (19:18 -0800)]
sim: fix redundant --debug-start help string
Just changes the metavar for --debug-start from TIME
to TICK in cset
72046b9b3323 and didn't notice that the
comment "must be in ticks" is now redundant.
Steve Reinhardt [Mon, 18 Jan 2016 02:27:46 +0000 (18:27 -0800)]
cpu. arch: add initiateMemRead() to ExecContext interface
For historical reasons, the ExecContext interface had a single
function, readMem(), that did two different things depending on
whether the ExecContext supported atomic memory mode (i.e.,
AtomicSimpleCPU) or timing memory mode (all the other models).
In the former case, it actually performed a memory read; in the
latter case, it merely initiated a read access, and the read
completion did not happen until later when a response packet
arrived from the memory system.
This led to some confusing things, including timing accesses
being required to provide a pointer for the return data even
though that pointer was only used in atomic mode.
This patch splits this interface, adding a new initiateMemRead()
function to the ExecContext interface to replace the timing-mode
use of readMem().
For consistency and clarity, the readMemTiming() helper function
in the ISA definitions is renamed to initiateMemRead() as well.
For x86, where the access size is passed in explicitly, we can
also get rid of the data parameter at this level. For other ISAs,
where the access size is determined from the type of the data
parameter, we have to keep the parameter for that purpose.
Steve Reinhardt [Mon, 18 Jan 2016 02:27:46 +0000 (18:27 -0800)]
cpu: remove unnecessary data ptr from O3 internal read() funcs
The read() function merely initiates a memory read operation; the
data doesn't arrive until the access completes and a response packet
is received from the memory system. Thus there's no need to provide
a data pointer; its existence is historical.
Getting this pointer out of this internal o3 interface sets the
stage for similar cleanup in the ExecContext interface. Also
found that we were pointlessly setting the contents at this pointer
on a store forward (the useful memcpy happens just a few lines
below the deleted one).
Steve Reinhardt [Mon, 18 Jan 2016 02:27:46 +0000 (18:27 -0800)]
arch: don't call *Timing functions from *Atomic versions
The readMemAtomic/writeMemAtomic helper functions were calling
readMemTiming/writeMemTiming respectively. This is functionally
correct, since the *Timing functions are doing the same access
initiation operation as the *Atomic functions (just that the
*Atomic versions also complete the access in line). It also
provides for some (very minimal) code reuse. Unfortunately,
it's potentially pretty confusing, since it makes it look like
the atomic accesses are somehow being converted to timing
accesses. It also gets in the way of specializing the timing
interface (as will be done in a future patch).
Steve Reinhardt [Mon, 18 Jan 2016 02:27:46 +0000 (18:27 -0800)]
arch: get rid of unused LargestRead typedef
Steve Reinhardt [Mon, 18 Jan 2016 02:27:46 +0000 (18:27 -0800)]
sim: don't ignore SIG_TRAP
By ignoring SIG_TRAP, using --debug-break <N> when not connected to
a debugger becomes a no-op. Apparently this was intended to be a
feature, though the rationale is not clear.
If we don't ignore SIG_TRAP, then using --debug-break <N> when not
connected to a debugger causes the simulation process to terminate
at tick N. This is occasionally useful, e.g., if you just want to
collect a trace for a specific window of execution then you can combine
this with --debug-start to do exactly that.
In addition to not ignoring the signal, this patch also updates
the --debug-break help message and deletes a handful of unprotected
calls to Debug::breakpoint() that relied on the prior behavior.
Steve Reinhardt [Mon, 18 Jan 2016 02:13:29 +0000 (21:13 -0500)]
stats: update SPARC FS stats
The fs/80.solaris-boot/sparc/solaris/t1000-simple-atomic test was
broken for so long that, now that it's working again, the stats
output is out of date. This changeset updates the outputs, on
the assumption that the stats changes are all valid differences
due to other changes made while it was broken.
Andreas Sandberg [Fri, 15 Jan 2016 11:30:13 +0000 (11:30 +0000)]
dev, arm: Add a platform with support for both aarch32 and aarch64
Add a platform with support for both aarch32 and aarch64. This
platform implements a subset of the devices in a real Versatile
Express and extends it with some gem5-specific functionality. It is in
many ways similar to the old VExpress_EMM64 platform, but supports the
following new features:
* Automatic PCI interrupt assignment
* PCI interrupts allocated in a contiguous range.
* Automatic boot loader selection (32-bit / 64-bit)
* Cleaner memory map where gem5-specific devices live in CS5 which
isn't used by current Versatile Express platforms.
* No fake devices. Devices that were previously faked will be
removed from the device tree instead.
* Support for 510 GiB contiguous memory
Andreas Sandberg [Fri, 15 Jan 2016 11:30:06 +0000 (11:30 +0000)]
dev, arm: Add support for automatic PCI interrupt routing
Add support for automatic PCI interrupt routing using a device's ID on
the PCI bus. Our current DTBs typically tell the kernel that we do
this or something similar when declaring the PCI controller. This
changeset adds an option to make the simulator behave in the same way.
Interrupt routing can be selected by setting the int_policy parameter
in the GenericArmPciHost. The following values are supported:
* ARM_PCI_INT_STATIC: Use the old static routing policy using the
interrupt line from a device's configurtion space.
* ARM_PCI_INT_DEV: Use device number on the PCI bus to map to an
interrupt in the GIC. The interrupt is computed as:
gic_int = int_base + (pci_dev % int_count)
* ARM_PCI_INT_PIN: Use device interrupt pin on the PCI bus to map to
an interrupt in the GIC. The PCI specification reserves pin ID 0
for devices without interrupts, the interrupt therefore computed
as:
gic_int = int_base + ((pin - 1) % int_count)
Steve Reinhardt [Mon, 11 Jan 2016 21:20:38 +0000 (16:20 -0500)]
mem: fix bug in packet access endianness changes
The new Packet::setRaw() method incorrectly still contained
an htog() conversion. As a result, calls to the old set()
method (now defined as setRaw(htog(v))) underwent two htog
conversions, which breaks things when htog() is not a no-op.
Interestingly the only test that caught this was a SPARC
boot test, where an IsaFake device with a non-zero return
value was getting swapped twice resulting in a register
getting loaded with 0x100000000000000 instead of 1.
(Good reason for keeping SPARC around, perhaps?)
Andreas Hansson [Mon, 11 Jan 2016 10:52:20 +0000 (05:52 -0500)]
scons: Enable -Wextra by default
Make best use of the compiler, and enable -Wextra as well as
-Wall. There are a few issues that had to be resolved, but they are
all trivial.
Andreas Hansson [Mon, 11 Jan 2016 10:52:18 +0000 (05:52 -0500)]
ext: Replace gzstream with iostream3 from zlib to avoid LGPL
This patch replaces the gzstream zlib wrapper with the iostream3
wrapper provided as part of zlib contributions. The main reason for
the switch is to avoid including LGPL in the default gem5
build. iostream3 is provided under a more permissive license:
The code is provided "as is", with the permission to use, copy,
modify, distribute and sell it for any purpose without fee.
Andreas Hansson [Mon, 11 Jan 2016 10:52:17 +0000 (05:52 -0500)]
configs: Fix inheritance of HMCSystem and cleanup spacing
Minor fix to ensure the HMCSystem can actually be instantiated
(SimObject cannot be created). Also address some spacing issues.
Gabor Dozsa [Thu, 7 Jan 2016 22:33:47 +0000 (16:33 -0600)]
config: Updates for distributed gem5 simulations
Gabor Dozsa [Thu, 7 Jan 2016 22:33:47 +0000 (16:33 -0600)]
dev: Distributed Ethernet link for distributed gem5 simulations
Distributed gem5 (abbreviated dist-gem5) is the result of the
convergence effort between multi-gem5 and pd-gem5 (from Univ. of
Wisconsin). It relies on the base multi-gem5 infrastructure for packet
forwarding, synchronisation and checkpointing but combines those with
the elaborated network switch model from pd-gem5.
--HG--
rename : src/dev/net/multi_etherlink.cc => src/dev/net/dist_etherlink.cc
rename : src/dev/net/multi_etherlink.hh => src/dev/net/dist_etherlink.hh
rename : src/dev/net/multi_iface.cc => src/dev/net/dist_iface.cc
rename : src/dev/net/multi_iface.hh => src/dev/net/dist_iface.hh
rename : src/dev/net/multi_packet.hh => src/dev/net/dist_packet.hh
Gabor Dozsa [Thu, 7 Jan 2016 22:33:47 +0000 (16:33 -0600)]
pseudo inst,util: Add optional key to initparam pseudo instruction
The key parameter can be used to read out various config parameters from
within the simulated software.
Steve Reinhardt [Thu, 31 Dec 2015 17:32:09 +0000 (09:32 -0800)]
mem: add CacheVerbose debug flag, filter noisy DPRINTFs
Some of the DPRINTFs added to the classic cache in cset
45df88079f04,
while useful to those unfamiliar with the cache code, end up being
noise when you're familiar with the code but are trying to debug tricky
protocol issues. (Particularly getting two messages from each cache
as it receives a snoop request then declares that there was no match.)
This patch introduces a CacheVerbose debug flag, and moves a subset of
the added DPRINTFs into that category, so that Cache by itself returns
to being a more succinct summary of cache activity.
Also added a CacheAll compound flag to turn on all the cache-related
debug flags (other than CacheTags, which you *really* have to want badly
to turn it on, IMO).
Andreas Hansson [Thu, 31 Dec 2015 14:34:18 +0000 (09:34 -0500)]
mem: Do not rely on the NeedsWritable flag for responses
This patch removes the NeedsWritable flag for all responses, as it is
really only the request that needs a writable response. The response,
on the other hand, should in these cases always provide the line in a
writable state, as indicated by the hasSharers flag not being set.
When we send requests that has NeedsWritable set, the response will
always have the hasSharers flag not set. Additionally, there are cases
where the request did not have NeedsWritable set, and we still get a
writable response with the hasSharers flag not set. This never happens
on snoops, but is used by downstream caches to pass ownership
upstream.
As part of this patch, the affected response types are updated, and
the snoop filter is similarly modified to check only the hasSharers
flag (as it should). A sanity check is also added to the packet class,
asserting that we never look at the NeedsWritable flag for responses.
No regressions are affected.
Andreas Hansson [Thu, 31 Dec 2015 14:33:39 +0000 (09:33 -0500)]
mem: Do not allocate space for packet data if not needed
This patch looks at the request and response command to determine if
either actually has any data payload, and if not, we do not allocate
any space for packet data.
The only tricky case is where the command type is changed as part of
the MSHR functionality. In these cases where the original packet had
no data, but the new packet does, we need to explicitly call
allocate().
Andreas Hansson [Thu, 31 Dec 2015 14:33:25 +0000 (09:33 -0500)]
mem: Do not alter cache block state on uncacheable snoops
This patch ensures we do not respond with a Modified (dirty and
writable) line if the request is uncacheable, and that the cache
responding retains the line without modifying the state (even if
responding).
Andreas Hansson [Thu, 31 Dec 2015 14:32:58 +0000 (09:32 -0500)]
mem: Make cache terminology easier to understand
This patch changes the name of a bunch of packet flags and MSHR member
functions and variables to make the coherency protocol easier to
understand. In addition the patch adds and updates lots of
descriptions, explicitly spelling out assumptions.
The following name changes are made:
* the packet memInhibit flag is renamed to cacheResponding
* the packet sharedAsserted flag is renamed to hasSharers
* the packet NeedsExclusive attribute is renamed to NeedsWritable
* the packet isSupplyExclusive is renamed responderHadWritable
* the MSHR pendingDirty is renamed to pendingModified
The cache states, Modified, Owned, Exclusive, Shared are also called
out in the cache and MSHR code to make it easier to understand.
Tony Gutierrez [Mon, 20 Jul 2015 14:15:18 +0000 (09:15 -0500)]
ruby: slicc: have a static MachineType
This patch is imported from reviewboard patch 2551 by Nilay.
This patch moves from a dynamically defined MachineType to a statically
defined one. The need for this patch was felt since a dynamically defined
type prevents us from having types for which no machine definition may
exist.
The following changes have been made:
i. each machine definition now uses a type from the MachineType enumeration
instead of any random identifier. This required changing the grammar and the
*.sm files.
ii. MachineType enumeration defined statically in RubySlicc_Exports.sm.
* * *
normal protocol fixes for nilay's parser machine type fix
Tony Gutierrez [Mon, 20 Jul 2015 14:15:18 +0000 (09:15 -0500)]
ruby: slicc: remove support for single machine, multiple types
This patch is imported from reviewboard patch 2550 by Nilay.
It was possible to specify multiple machine types with a single state machine.
This seems unnecessary and is being removed.
Steve Reinhardt [Wed, 30 Dec 2015 16:18:44 +0000 (11:18 -0500)]
stats: more updates due to PCI changes
A couple of the long regressions have been showing as CHANGED
since 11244:
a2af58a06c4e despite the updates in 11245:
1c5102c0a7a9.
The x86 regression looks like it was just missed, but it's not clear
why the ARM one is giving different results (perhaps a non-determinism
between zizzer and wherever the updated results were run?).
Steve Reinhardt [Mon, 28 Dec 2015 20:43:06 +0000 (15:43 -0500)]
tests: update EIO reference outputs
Andreas Hansson [Mon, 28 Dec 2015 16:14:18 +0000 (11:14 -0500)]
mem: Explicitly check MSHR snoops for cases not dealt with
Add a sanity check to make it explicit that we currently do not allow
an I/O coherent agent to directly issue writes into the coherent part
of the memory system (it has to go via a cache, and get transformed
into a read ex, upgrade or invalidation).
Andreas Hansson [Mon, 28 Dec 2015 16:14:16 +0000 (11:14 -0500)]
mem: Remove unused cache squash functionality
This patch removes the unused squash function from the MSHR queue, and
the associated (and also unused) threadNum member from the MSHR.
Andreas Hansson [Mon, 28 Dec 2015 16:14:15 +0000 (11:14 -0500)]
mem: Avoid unecessary checks when creating HardPFReq in cache
The checks made before sending out a HardPFReq were unecessarily
complex, and checked for cases that never occur. This patch
tidies it up.
Andreas Hansson [Mon, 28 Dec 2015 16:14:14 +0000 (11:14 -0500)]
mem: Do not use sender state to track forwarded snoops in cache
This patch changes how the cache tracks which snoops are forwarded,
and which ones are created locally. Previously the identification was
based on an empty sender state of a specific class, but this method
fails to distinguish which cache actually attached the sender
state. Instead we use the same mechanism as the crossbar, and keep
track of the requests that have outstanding snoops.
Andreas Hansson [Mon, 28 Dec 2015 16:14:10 +0000 (11:14 -0500)]
mem: Fix cache sender state handling and add clarification
This patch addresses a bug in how the cache attached the MSHR as a
sender state. Rather than overwriting any existing sender state it now
pushes a new one. The handling of upward snoops is also clarified.
Boris Shingarov [Fri, 18 Dec 2015 21:12:07 +0000 (15:12 -0600)]
arm: remote GDB: rationalize structure of register offsets
Currently, the wire format of register values in g- and G-packets is
modelled using a union of uint8/16/32/64 arrays. The offset positions
of each register are expressed as a "register count" scaled according
to the width of the register in question. This results in counter-
intuitive and error-prone "register count arithmetic", and some
formats would even be altogether unrepresentable in such model, e.g.
a 64-bit register following a 32-bit one would have a fractional index
in the regs64 array.
Another difficulty is that the array is allocated before the actual
architecture of the workload is known (and therefore before the correct
size for the array can be calculated).
With this patch I propose a simpler mechanism for expressing the
register set structure. In the new code, GdbRegCache is an abstract
class; its subclasses contain straightforward structs reflecting the
register representation. The determination whether to use e.g. the
AArch32 vs. AArch64 register set (or SPARCv8 vs SPARCv9, etc.) is made
by polymorphically dispatching getregs() to the concrete subclass.
The subclass is not instantiated until it is needed for actual
g-/G-packet processing, when the mode is already known.
This patch is not meant to be merged in on its own, because it changes
the contract between src/base/remote_gdb.* and src/arch/*/remote_gdb.*,
so as it stands right now, it would break the other architectures.
In this patch only the base and the ARM code are provided for review;
once we agree on the structure, I will provide src/arch/*/remote_gdb.*
for the other architectures; those patches could then be merged in
together.
Review Request: http://reviews.gem5.org/r/3207/
Pushed by Joel Hestness <jthestness@gmail.com>
Andreas Sandberg [Fri, 18 Dec 2015 10:14:17 +0000 (10:14 +0000)]
sim: Use the old work item behavior by default
When adding an option to forward work items to the Python environment,
the new behavior was accidentally enabled by default. Set the value of
exit_on_work_items to False by default to revert to the old behavior
unless the simulation scripts explicitly requests work item
forwarding.
Andreas Hansson [Thu, 17 Dec 2015 22:07:22 +0000 (17:07 -0500)]
configs: Make the default memtest behaviour more complex
Add functional and uncacheable accesses by default.
Andreas Hansson [Thu, 17 Dec 2015 22:07:11 +0000 (17:07 -0500)]
mem: Fix memory allocation bug in deferred snoop handling
This patch fixes a corner case in the deferred snoop handling, where
requests ended up being used by multiple packets with different
lifetimes, and inadvertently got deleted while they were still in use.
Andreas Sandberg [Mon, 14 Dec 2015 17:10:36 +0000 (17:10 +0000)]
sim: Add an option to forward work items to Python
There are cases where we want the Python world to handle work items
instead of the C++ world. However, that's currently not possible. This
changeset adds the forward_work_items option to the System class. Then
it is set to True, work items will generate workbegin/workend
simulation exists with the work item ID as the exit code and the old
C++ handling is completely bypassed.
--HG--
extra : rebase_source :
8de637a744fc4b6ff2bc763f00cdf8ddf2bff885
David Hashe [Mon, 20 Jul 2015 14:15:18 +0000 (09:15 -0500)]
mem: add request types for acquire and release
Add support for acquire and release requests. These synchronization operations
are commonly supported by several modern instruction sets.
Anthony Gutierrez [Sat, 12 Dec 2015 22:27:38 +0000 (17:27 -0500)]
stats: bump stats to reflect ruby tester changes
Brad Beckmann [Fri, 11 Dec 2015 21:07:01 +0000 (16:07 -0500)]
regress: updates required for the compute-gpu patches
Brad Beckmann [Mon, 20 Jul 2015 14:15:18 +0000 (09:15 -0500)]
ruby: more flexible ruby tester support
This patch allows the ruby random tester to use ruby ports that may only
support instr or data requests. This patch is similar to a previous changeset
(8932:
1b2c17565ac8) that was unfortunately broken by subsequent changesets.
This current patch implements the support in a more straight-forward way.
Since retries are now tested when running the ruby random tester, this patch
splits up the retry and drain check behavior so that RubyPort children, such
as the GPUCoalescer, can perform those operations correctly without having to
duplicate code. Finally, the patch also includes better DPRINTFs for
debugging the tester.
Andreas Sandberg [Thu, 10 Dec 2015 18:46:02 +0000 (18:46 +0000)]
dev: Add missing SConscript in src/dev/i2c
Andreas Sandberg [Thu, 10 Dec 2015 10:35:23 +0000 (10:35 +0000)]
dev: Move storage devices to src/dev/storage/
Move the IDE controller and the disk implementations to
src/dev/storage.
--HG--
rename : src/dev/DiskImage.py => src/dev/storage/DiskImage.py
rename : src/dev/Ide.py => src/dev/storage/Ide.py
rename : src/dev/SimpleDisk.py => src/dev/storage/SimpleDisk.py
rename : src/dev/disk_image.cc => src/dev/storage/disk_image.cc
rename : src/dev/disk_image.hh => src/dev/storage/disk_image.hh
rename : src/dev/ide_atareg.h => src/dev/storage/ide_atareg.h
rename : src/dev/ide_ctrl.cc => src/dev/storage/ide_ctrl.cc
rename : src/dev/ide_ctrl.hh => src/dev/storage/ide_ctrl.hh
rename : src/dev/ide_disk.cc => src/dev/storage/ide_disk.cc
rename : src/dev/ide_disk.hh => src/dev/storage/ide_disk.hh
rename : src/dev/ide_wdcreg.h => src/dev/storage/ide_wdcreg.h
rename : src/dev/simple_disk.cc => src/dev/storage/simple_disk.cc
rename : src/dev/simple_disk.hh => src/dev/storage/simple_disk.hh
Andreas Sandberg [Thu, 10 Dec 2015 10:35:18 +0000 (10:35 +0000)]
dev: Move network devices to src/dev/net/
--HG--
rename : src/dev/Ethernet.py => src/dev/net/Ethernet.py
rename : src/dev/etherbus.cc => src/dev/net/etherbus.cc
rename : src/dev/etherbus.hh => src/dev/net/etherbus.hh
rename : src/dev/etherdevice.cc => src/dev/net/etherdevice.cc
rename : src/dev/etherdevice.hh => src/dev/net/etherdevice.hh
rename : src/dev/etherdump.cc => src/dev/net/etherdump.cc
rename : src/dev/etherdump.hh => src/dev/net/etherdump.hh
rename : src/dev/etherint.cc => src/dev/net/etherint.cc
rename : src/dev/etherint.hh => src/dev/net/etherint.hh
rename : src/dev/etherlink.cc => src/dev/net/etherlink.cc
rename : src/dev/etherlink.hh => src/dev/net/etherlink.hh
rename : src/dev/etherobject.hh => src/dev/net/etherobject.hh
rename : src/dev/etherpkt.cc => src/dev/net/etherpkt.cc
rename : src/dev/etherpkt.hh => src/dev/net/etherpkt.hh
rename : src/dev/ethertap.cc => src/dev/net/ethertap.cc
rename : src/dev/ethertap.hh => src/dev/net/ethertap.hh
rename : src/dev/i8254xGBe.cc => src/dev/net/i8254xGBe.cc
rename : src/dev/i8254xGBe.hh => src/dev/net/i8254xGBe.hh
rename : src/dev/i8254xGBe_defs.hh => src/dev/net/i8254xGBe_defs.hh
rename : src/dev/multi_etherlink.cc => src/dev/net/multi_etherlink.cc
rename : src/dev/multi_etherlink.hh => src/dev/net/multi_etherlink.hh
rename : src/dev/multi_iface.cc => src/dev/net/multi_iface.cc
rename : src/dev/multi_iface.hh => src/dev/net/multi_iface.hh
rename : src/dev/multi_packet.cc => src/dev/net/multi_packet.cc
rename : src/dev/multi_packet.hh => src/dev/net/multi_packet.hh
rename : src/dev/ns_gige.cc => src/dev/net/ns_gige.cc
rename : src/dev/ns_gige.hh => src/dev/net/ns_gige.hh
rename : src/dev/ns_gige_reg.h => src/dev/net/ns_gige_reg.h
rename : src/dev/pktfifo.cc => src/dev/net/pktfifo.cc
rename : src/dev/pktfifo.hh => src/dev/net/pktfifo.hh
rename : src/dev/sinic.cc => src/dev/net/sinic.cc
rename : src/dev/sinic.hh => src/dev/net/sinic.hh
rename : src/dev/sinicreg.hh => src/dev/net/sinicreg.hh
rename : src/dev/tcp_iface.cc => src/dev/net/tcp_iface.cc
rename : src/dev/tcp_iface.hh => src/dev/net/tcp_iface.hh
Andreas Sandberg [Thu, 10 Dec 2015 10:35:18 +0000 (10:35 +0000)]
dev: Move i2c functionality to src/dev/i2c/
--HG--
rename : src/dev/I2C.py => src/dev/i2c/I2C.py
rename : src/dev/i2cbus.cc => src/dev/i2c/bus.cc
rename : src/dev/i2cbus.hh => src/dev/i2c/bus.hh
rename : src/dev/i2cdev.hh => src/dev/i2c/device.hh
Andreas Sandberg [Thu, 10 Dec 2015 10:35:16 +0000 (10:35 +0000)]
dev: Move the CopyEngine class to src/dev/pci
--HG--
rename : src/dev/CopyEngine.py => src/dev/pci/CopyEngine.py
rename : src/dev/copy_engine.cc => src/dev/pci/copy_engine.cc
rename : src/dev/copy_engine.hh => src/dev/pci/copy_engine.hh
rename : src/dev/copy_engine_defs.hh => src/dev/pci/copy_engine_defs.hh
Andreas Sandberg [Thu, 10 Dec 2015 10:35:15 +0000 (10:35 +0000)]
dev: Move existing PCI device functionality to src/dev/pci
Move pcidev.(hh|cc) to src/dev/pci/device.(hh|cc) and update existing
devices to use the new header location. This also renames the PCIDEV
debug flag to have a capitalization that is consistent with the PCI
host and other devices.
--HG--
rename : src/dev/Pci.py => src/dev/pci/PciDevice.py
rename : src/dev/pcidev.cc => src/dev/pci/device.cc
rename : src/dev/pcidev.hh => src/dev/pci/device.hh
rename : src/dev/pcireg.h => src/dev/pci/pcireg.h
Sascha Bischoff [Thu, 5 Nov 2015 18:26:23 +0000 (18:26 +0000)]
sim: Disable gzip compression for writefile pseudo instruction
The writefile pseudo instruction uses OutputDirectory::create and
OutputDirectory::openFile to create the output files. However, by
default these will check the file extention for .gz, and create a gzip
compressed stream if the file ending matches. When writing out files,
we want to write them out exactly as they are in the guest simulation,
and never want to compress them with gzio. Additionally, this causes
m5 writefile to fail when checking the error flags for the output
steam.
With this patch we add an additional no_gz argument to
OutputDirectory::create and OutputDirectory::openFile which allows us
to override the gzip compression. Therefore, for m5 writefile we
disable the filename check, and always create a standard ostream.
Karthik Sangaiah [Wed, 15 Jul 2015 13:43:35 +0000 (14:43 +0100)]
arm: Bootloader fix for v8 over 16 cores
Previous code used a smaller 4 bit mask to test the MPIDR-EL1 register.
The bitmask was extended to support greater than 16 cores.
Karthik Sangaiah [Fri, 18 Sep 2015 15:49:28 +0000 (16:49 +0100)]
dev, arm: Add gem5 extensions to support more than 8 cores
Previous ARM-based simulations were limited to 8 cores due to
limitations in GICv2 and earlier. This changeset adds a set of
gem5-specific extensions that enable support for up to 256 cores.
When the gem5 extensions are enabled, the GIC uses CPU IDs instead of
a CPU bitmask in the GIC's register interface. To OS can enable the
extensions by setting bit 0x200 in ICDICTR.
This changeset is based on previous work by Matt Evans.
Tony Gutierrez [Thu, 10 Dec 2015 03:56:31 +0000 (22:56 -0500)]
mem: remove acq/rel cmds from packet and add mem fence req
Steve Reinhardt [Wed, 9 Dec 2015 19:47:43 +0000 (14:47 -0500)]
syscall_emul: don't check host fd when allocating target fd
There's a well-meaning check in Process::allocFD() to return an invalid
target fd (-1) if the incoming host fd is -1. However, this means that
emulated drivers, which want to allocate a target fd that doesn't
correspond to a host fd, can't use -1 to indicate an intentionally
invalid host fd.
It turns out the allocFD() check is redundant, as callers always test
the host fd for validity before calling. Also, callers never test the
return value of allocFD() for validity, so even if the test failed,
it would likely have the undesirable result of returning -1 to the
target app as a file descriptor without setting errno.
Thus the check is pointless and is now getting in the way, so it seems
we should just get rid of it.
Curtis Dunham [Tue, 8 Dec 2015 20:30:31 +0000 (14:30 -0600)]
ext: fix SST connector
Writeback no longer a MemCmd.
Radhika Jagtap [Mon, 7 Dec 2015 22:42:16 +0000 (16:42 -0600)]
cpu: Support virtual addr in elastic traces
This patch adds support to optionally capture the virtual address and asid
for load/store instructions in the elastic traces. If they are present in
the traces, Trace CPU will set those fields of the request during replay.
Radhika Jagtap [Mon, 7 Dec 2015 22:42:16 +0000 (16:42 -0600)]
cpu: Create record type enum for elastic traces
This patch replaces the booleans that specified the elastic trace record
type with an enum type. The source of change is the proto message for
elastic trace where the enum is introduced. The struct definitions in the
elastic trace probe listener as well as the Trace CPU replace the boleans
with the proto message enum.
The patch does not impact functionality, but traces are not compatible with
previous version. This is preparation for adding new types of records in
subsequent patches.
Radhika Jagtap [Mon, 7 Dec 2015 22:42:16 +0000 (16:42 -0600)]
config: Enable elastic trace capture and replay in se/fs
This patch adds changes to the configuration scripts to support elastic
tracing and replay.
The patch adds a command line option to enable elastic tracing in SE mode
and FS mode. When enabled the Elastic Trace cpu probe is attached to O3CPU
and a few O3 CPU parameters are tuned. The Elastic Trace probe writes out
both instruction fetch and data dependency traces. The patch also enables
configuring the TraceCPU to replay traces using the SE and FS script.
The replay run is designed to resume from checkpoint using atomic cpu to
restore state keeping it consistent with FS run flow. It then switches to
TraceCPU to replay the input traces.
Radhika Jagtap [Mon, 7 Dec 2015 22:42:15 +0000 (16:42 -0600)]
util: Add decode and encode scripts for elastic traces
This patch adds python scripts to parse a protobuf encoded O3CPU
elastic trace and convert it to a text file output and vice versa.
Radhika Jagtap [Mon, 7 Dec 2015 22:42:15 +0000 (16:42 -0600)]
cpu: Add TraceCPU to playback elastic traces
This patch defines a TraceCPU that replays trace generated using the elastic
trace probe attached to the O3 CPU model. The elastic trace is an execution
trace with data dependencies and ordering dependencies annoted to it. It also
replays fixed timestamp instruction fetch trace that is also generated by the
elastic trace probe.
The TraceCPU inherits from BaseCPU as a result of which some methods need
to be defined. It has two port subclasses inherited from MasterPort for
instruction and data ports. It issues the memory requests deducing the
timing from the trace and without performing real execution of micro-ops.
As soon as the last dependency for an instruction is complete,
its computational delay, also provided in the input trace is added. The
dependency-free nodes are maintained in a list, called 'ReadyList',
ordered by ready time. Instructions which depend on load stall until the
responses for read requests are received thus achieving elastic replay. If
the dependency is not found when adding a new node, it is assumed complete.
Thus, if this node is found to be completely dependency-free its issue time is
calculated and it is added to the ready list immediately. This is encapsulated
in the subclass ElasticDataGen.
If ready nodes are issued in an unconstrained way there can be more nodes
outstanding which results in divergence in timing compared to the O3CPU.
Therefore, the Trace CPU also models hardware resources. A sub-class to model
hardware resources is added which contains the maximum sizes of load buffer,
store buffer and ROB. If resources are not available, the node is not issued.
The 'depFreeQueue' structure holds nodes that are pending issue.
Modeling the ROB size in the Trace CPU as a resource limitation is arguably the
most important parameter of all resources. The ROB occupancy is estimated using
the newly added field 'robNum'. We need to use ROB number as sequence number is
at times much higher due to squashing and trace replay is focused on correct
path modeling.
A map called 'inFlightNodes' is added to track nodes that are not only in
the readyList but also load nodes that are executed (and thus removed from
readyList) but are not complete. ReadyList handles what and when to execute
next node while the inFlightNodes is used for resource modelling. The oldest
ROB number is updated when any node occupies the ROB or when an entry in the
ROB is released. The ROB occupancy is equal to the difference in the ROB number
of the newly dependency-free node and the oldest ROB number in flight.
If no node dependends on a non load/store node then there is no reason to track
it in the dependency graph. We filter out such nodes but count them and add a
weight field to the subsequent node that we do include in the trace. The weight
field is used to model ROB occupancy during replay.
The depFreeQueue is chosen to be FIFO so that child nodes which are in
program order get pushed into it in that order and thus issued in the in
program order, like in the O3CPU. This is also why the dependents is made a
sequential container, std::set to std::vector. We only check head of the
depFreeQueue as nodes are issued in order and blocking on head models that
better than looping the entire queue. An alternative choice would be to inspect
top N pending nodes where N is the issue-width. This is left for future as the
timing correlation looks good as it is.
At the start of an execution event, first we attempt to issue such pending
nodes by checking if appropriate resources have become available. If yes, we
compute the execute tick with respect to the time then. Then we proceed to
complete nodes from the readyList.
When a read response is received, sometimes a dependency on it that was
supposed to be released when it was issued is still not released. This occurs
because the dependent gets added to the graph after the read was sent. So the
check is made less strict and the dependency is marked complete on read
response instead of insisting that it should have been removed on read sent.
There is a check for requests spanning two cache lines as this condition
triggers an assert fail in the L1 cache. If it does then truncate the size
to access only until the end of that line and ignore the remainder.
Strictly-ordered requests are skipped and the dependencies on such requests
are handled by simply marking them complete immediately.
The simulated seconds can be calculated as the difference between the
final_tick stat and the tickOffset stat. A CountedExitEvent that contains
a static int belonging to the Trace CPU class as a down counter is used to
implement multi Trace CPU simulation exit.
Radhika Jagtap [Mon, 7 Dec 2015 22:42:15 +0000 (16:42 -0600)]
mem: Add instruction sequence number to request
This patch adds the instruction sequence number to the request and provides a
request constructor that accepts a sequence number for initialization.
Radhika Jagtap [Mon, 7 Dec 2015 22:42:15 +0000 (16:42 -0600)]
proto, probe: Add elastic trace probe to o3 cpu
The elastic trace is a type of probe listener and listens to probe points
in multiple stages of the O3CPU. The notify method is called on a probe
point typically when an instruction successfully progresses through that
stage.
As different listener methods mapped to the different probe points execute,
relevant information about the instruction, e.g. timestamps and register
accesses, are captured and stored in temporary InstExecInfo class objects.
When the instruction progresses through the commit stage, the timing and the
dependency information about the instruction is finalised and encapsulated in
a struct called TraceInfo. TraceInfo objects are collected in a list instead
of writing them out to the trace file one a time. This is required as the
trace is processed in chunks to evaluate order dependencies and computational
delay in case an instruction does not have any register dependencies. By this
we achieve a simpler algorithm during replay because every record in the
trace can be hooked onto a record in its past. The instruction dependency
trace is written out as a protobuf format file. A second trace containing
fetch requests at absolute timestamps is written to a separate protobuf
format file.
If the instruction is not executed then it is not added to the trace.
The code checks if the instruction had a fault, if it predicated
false and thus previous register values were restored or if it was a
load/store that did not have a request (e.g. when the size of the
request is zero). In all these cases the instruction is set as
executed by the Execute stage and is picked up by the commit probe
listener. But a request is not issued and registers are not written.
So practically, skipping these should not hurt the dependency modelling.
If squashing results in squashing younger instructions, it may happen that
the squash probe discards the inst and removes it from the temporary
store but execute stage deals with the instruction in the next cycle which
results in the execute probe seeing this inst as 'new' inst. A sequence
number of the last processed trace record is used to trap these cases and
not add to the temporary store.
The elastic instruction trace and fetch request trace can be read in and
played back by the TraceCPU.
Radhika Jagtap [Mon, 7 Dec 2015 22:42:15 +0000 (16:42 -0600)]
probe: Add probe in Fetch, IEW, Rename and Commit
This patch adds probe points in Fetch, IEW, Rename and Commit stages as follows.
A probe point is added in the Fetch stage for probing when a fetch request is
sent. Notify is fired on the probe point when a request is sent succesfully in
the first attempt as well as on a retry attempt.
Probe points are added in the IEW stage when an instruction begins to execute
and when execution is complete. This points can be used for monitoring the
execution time of an instruction.
Probe points are added in the Rename stage to probe renaming of source and
destination registers and when there is squashing. These probe points can be
used to track register dependencies and remove when there is squashing.
A probe point for squashing is added in Commit to probe squashed instructions.
Andreas Sandberg [Sat, 5 Dec 2015 00:11:25 +0000 (00:11 +0000)]
stats: Update to reflect changes to PCI handling
Andreas Sandberg [Sat, 5 Dec 2015 00:11:24 +0000 (00:11 +0000)]
dev: Rewrite PCI host functionality
The gem5's current PCI host functionality is very ad hoc. The current
implementations require PCI devices to be hooked up to the
configuration space via a separate configuration port. Devices query
the platform to get their config-space address range. Un-mapped parts
of the config space are intercepted using the XBar's default port
mechanism and a magic catch-all device (PciConfigAll).
This changeset redesigns the PCI host functionality to improve code
reuse and make config-space and interrupt mapping more
transparent. Existing platform code has been updated to use the new
PCI host and configured to stay backwards compatible (i.e., no
guest-side visible changes). The current implementation does not
expose any new functionality, but it can easily be extended with
features such as automatic interrupt mapping.
PCI devices now register themselves with a PCI host controller. The
host controller interface is defined in the abstract base class
PciHost. Registration is done by PciHost::registerDevice() which takes
the device, its bus position (bus/dev/func tuple), and its interrupt
pin (INTA-INTC) as a parameter. The registration interface returns a
PciHost::DeviceInterface that the PCI device can use to query memory
mappings and signal interrupts.
The host device manages the entire PCI configuration space. Accesses
to devices decoded into the devices bus position and then forwarded to
the correct device.
Basic PCI host functionality is implemented in the GenericPciHost base
class. Most platforms can use this class as a basic PCI controller. It
provides the following functionality:
* Configurable configuration space decoding. The number of bits
dedicated to a device is a prameter, making it possible to support
both CAM, ECAM, and legacy mappings.
* Basic interrupt mapping using the interruptLine value from a
device's configuration space. This behavior is the same as in the
old implementation. More advanced controllers can override the
interrupt mapping method to dynamically assign host interrupts to
PCI devices.
* Simple (base + addr) remapping from the PCI bus's address space to
physical addresses for PIO, memory, and DMA.
Pau Cabre [Fri, 4 Dec 2015 23:54:03 +0000 (17:54 -0600)]
cpu: fix unitialized variable which may cause assertion failure
The assert in lsq_unit_impl.hh line 963 needs pktPending to be initialized to
NULL (I got the assertion failure several times without the fix).
Committed by: Nilay Vaish <nilay@cs.wisc.edu>
Bjoern A. Zeeb [Fri, 4 Dec 2015 23:25:45 +0000 (17:25 -0600)]
util: term: drop CC from Makefile
With clang there are systems without gcc being installed anymore and we should
not rely on that. This patch drops CC so that system's default compiler is
invoked.
Committed by: Nilay Vaish <nilay@cs.wisc.edu>
Abdul Mutaal Ahmad [Fri, 4 Dec 2015 23:20:07 +0000 (17:20 -0600)]
util: DrainManager/Checkpoint changes in SystemC coupling
Due to changes in Drain Manager, the lastest systemc coupling doesn't work. The
code for handling Checkpoint has been modified and it is now compatiable with
new drain manager.
Testing is being done on systemC coupling. It needs more testing to verify
checkpointing feature.
Committed by: Nilay Vaish <nilay@cs.wisc.edu>
Andreas Sandberg [Fri, 4 Dec 2015 09:48:48 +0000 (09:48 +0000)]
sim: Get rid of the non-const serialize() method
The last SimObject using the legacy serialize API with non-const
methods has now been transitioned to the new API. This changeset
removes the serializeOld() methods from the serialization base class
as they are no longer used.
Andreas Sandberg [Fri, 4 Dec 2015 00:19:05 +0000 (00:19 +0000)]
stats: Update to reflect changes to RealView platform code
Andreas Sandberg [Fri, 4 Dec 2015 00:19:05 +0000 (00:19 +0000)]
arm, config: Automatically discover available platforms
Add support for automatically discover available platforms. The
Python-side uses functionality similar to what we use when
auto-detecting available CPU models. The machine IDs have been updated
to match the platform configurations. If there isn't a matching
machine ID, the configuration scripts default to -1 which Linux uses
for device tree only platforms.
Andreas Sandberg [Fri, 4 Dec 2015 00:19:05 +0000 (00:19 +0000)]
dev, arm: Disable R/B swap in HDLCD by default
The HDLCD model implements a workaround that swaps the red and blue
channels. This works around an issue in certain old kernels. The new
driver doesn't seem to have this behavior, so disable the workaround
by default and enable it in the affected platforms.
Andreas Sandberg [Fri, 4 Dec 2015 00:19:05 +0000 (00:19 +0000)]
dev, arm: Split MCC and DCC subsystems
Devices behind the Versatile Express configuration controllers are
currently all lumped into one SimObject. This will make DTB generation
challenging since the DTB assumes them to be in different parts of the
hierarchy. It also makes it hard to model other CoreTiles without also
replicating devices from the motherboard.
This changeset splits the VExpressCoreTileCtrl into two subsystems:
VExpressMCC for all motherboard-related devices and CoreTile2A15DCC
for Core Tile specific devices.
Andreas Sandberg [Fri, 4 Dec 2015 00:12:58 +0000 (00:12 +0000)]
sim: Add support for generating back traces on errors
Add functionality to generate a back trace if gem5 crashes (SIGABRT or
SIGSEGV). The current implementation uses glibc's stack traversal
support if available and stubs out the call to print_backtrace()
otherwise.
Andreas Sandberg [Thu, 3 Dec 2015 23:53:37 +0000 (23:53 +0000)]
arm: Add support for automatic boot loader selection
Add support for automatically selecting a boot loader that matches the
guest system's kernel. Instead of accepting a single boot loader, the
ArmSystem class now accepts a vector of boot loaders. When
initializing a system, the we now look for the first boot loader with
an architecture that matches the kernel.
This changeset makes it possible to use the same system for both
64-bit and 32-bit kernels.
Andreas Sandberg [Thu, 3 Dec 2015 23:09:34 +0000 (23:09 +0000)]
dev, mips: Remove the unused MaltaPChip class
The MaltaPChip class is currently unused and identical (except for the
class name) to the TsunamiPChip. If someone decides to implement PCI
for Malta, they should make sure to share code with the Tsunami
implementation if they are similar.