Bobby R. Bruce [Thu, 17 Sep 2020 00:16:17 +0000 (17:16 -0700)]
misc: Merge branch 'release-staging-v20.1.0.0' into develop
Change-Id: I8c3277af7903f0b055b26e497139455a03678524
Jason Lowe-Power [Wed, 16 Sep 2020 17:12:37 +0000 (10:12 -0700)]
misc: Add Matt Poremba as GPU maintainer
Change-Id: I90494955b6db628695ef8a42111977decba27618
Signed-off-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/34655
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Matthew Poremba <matthew.poremba@amd.com>
Reviewed-by: Matt Sinclair <mattdsinclair@gmail.com>
Reviewed-by: Matthew Poremba <matthew.poremba@amd.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Jason Lowe-Power [Wed, 16 Sep 2020 00:59:51 +0000 (17:59 -0700)]
configs: Add special case in MemConfig
SimpleMemory doesn't implement a full MemCtrl interface. Thus, like the
NVM and HMC memories, we need to add a special case to MemConfig.py. The
--mem-type command line option now works for SimpleMemory and all of the
DRAM interfaces (it does not work for the NVM interfaces, though).
Issue-on: https://gem5.atlassian.net/browse/GEM5-777
Change-Id: I6d60649215be324bdd2a104b1976752f936c960e
Signed-off-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/34595
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Gabe Black [Sun, 30 Aug 2020 09:40:21 +0000 (02:40 -0700)]
arch,cpu: Get rid of the IsMemRef StaticInst flag.
A comment at the top of StaticInstFlags.py says that if IsMemRef is set,
exactly one of IsStore or IsLoad will be set. That's not strictly true
since IsAtomic may be set as well, in which case neither IsStore or
IsLoad will be set (in one example I found).
The isMemRef accessor still exists, and now just ors the IsStore,
IsLoad, and IsAtomic flags.
Change-Id: Ic5ff104da68978273977a6eff2abab5dd0ae7fda
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/33744
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Gabe Black [Wed, 26 Aug 2020 04:48:04 +0000 (21:48 -0700)]
base: Create a SConscript for the loader subdirectory.
These files had been handled in base/SConscript, but there are enough of
them that they deserve their own.
Change-Id: I0c4166d8ff3c761c25940d2af5d7f0a9a6c874fa
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/33898
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Gabe Black [Sun, 30 Aug 2020 09:28:33 +0000 (02:28 -0700)]
arch,cpu: Rearrange StaticInst flags for memory barriers.
There were three different StaticInst flags for memory barriers,
IsMemBarrier, IsReadBarrier, and IsWriteBarrier. IsReadBarrier was never
used, and IsMemBarrier was for both loads and stores, so a composite of
IsReadBarrier and IsWriteBarrier.
This change gets rid of IsMemBarrier and replaces by setting
IsReadBarrier and IsWriteBarrier at the same time. An isMemBarrier
accessor is left, but is now implemented by checking if both of the
other flags are set, and renamed to isFullMemBarrier to make it clear
that it's checking both for both types of barrier, not one or the other.
Change-Id: I702633a047f4777be4b180b42d62438ca69f52ea
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/33743
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Earl Ou [Fri, 11 Sep 2020 01:21:52 +0000 (09:21 +0800)]
base: use setjmp to speed up fiber
ucontext is an order of magnitude slower compared to most of the fiber
implementation, mainly due to the additional signal mask operation.
This change applies the trick provided in
http://www.1024cores.net/home/lock-free-algorithms/tricks/fibers,
which uses _setjmp/_longjmp to switch between contexts created by
ucontext.
Combine with NodeList improvement, we see 81% speed improvement with the
example provided by Matthias Jung:
https://gist.github.com/myzinsky/
557200aa04556de44a317e0a10f51840
Compared with Accellera's SystemC, gem5 SystemC was originally 10x
slower, and with this change it's about 1.8x.
Change-Id: I0ffb6978e83dc8be049b750dc1baebb3d251601c
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/34356
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Gabe Black [Tue, 15 Sep 2020 02:46:47 +0000 (19:46 -0700)]
mem-ruby: Remove conditional includes based on THE_ISA in ruby.
These were including instruction class definitions from x86 for some
reason. There was no code in those .cc files which actually used
anything from them, as evidenced by the fact that the GCN3_X86 build
still works. No other code in the file was conditionally compiled as of
today.
Change-Id: I3cef8348fb601dd7af67665cf64bbf514c91c3db
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/34577
Reviewed-by: Matthew Poremba <matthew.poremba@amd.com>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>
Gabe Black [Tue, 15 Sep 2020 02:45:13 +0000 (19:45 -0700)]
gpu: Fix a syntax error in X86GPUTLB.py.
The recent changes which removed master/slave terminology also
accidentally deleted an "=", making the syntax in that file illegal.
Change-Id: I50aa945f0f66765db36775380b98a88caff23c13
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/34576
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>
Gabe Black [Tue, 15 Sep 2020 02:40:42 +0000 (19:40 -0700)]
arm: Use zero initialization for the BigRegVect types.
These were being initialized with BigRegVect brv = {0}, which made the
compiler complain because there is internal structure. The first element
of the union is actually an array, and this was telling it to initialize
that array to scalar 0. It was warning about this which was breaking the
build.
Instead, use zero initlization like BigRegVect brv = {}. This
initializes the first element of the union to all zeroes, with all
padding bits initialized to zero as well.
This satisfies the compiler and avoids a build error.
Change-Id: I31e7a8730c538637ff2e0c7fb00a4e12ed05e074
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/34575
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>
Gabe Black [Sun, 30 Aug 2020 08:24:50 +0000 (01:24 -0700)]
mips,cpu: Eliminate the unused IsIndexed StaticInst flag.
It's set by some MIPS instructions, but does not have an accessor in
StaticInst and is not used by anything.
Change-Id: I3466f7d2723fb1b0ac195064867e3840e3a8f21b
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/33735
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Gabe Black [Tue, 15 Sep 2020 03:15:37 +0000 (20:15 -0700)]
mem: Remove #if THE_ISA in the AbstractMemory class.
This used to guard the extraction of the endianness when tracing memory
accesses. Since that's now always possible even in NULL_ISA, we don't
need conditional compilation.
Change-Id: Ie5ec76f5b0f27dd4123bc0f0a4c02438bed629ad
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/34499
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Gabe Black <gabeblack@google.com>
Gabe Black [Sun, 30 Aug 2020 09:51:21 +0000 (02:51 -0700)]
cpu: Get rid of the unused IsMicroBranch StaticInst flag.
This flag was never set, nor read.
Change-Id: I74506c220d96b53dcd44740639286b1dbbe84d2e
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/33742
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>
Gabe Black [Sun, 30 Aug 2020 09:48:37 +0000 (02:48 -0700)]
x86,cpu: Get rid of the unused IsCC StaticInst flag.
This flag was set when some registers were used in x86, but never
actually checked by anything.
Change-Id: Id0f9847aeca5017455929ab4bbf28210288a3553
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/33741
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Maintainer: Gabe Black <gabeblack@google.com>
Gabe Black [Sun, 30 Aug 2020 08:46:31 +0000 (01:46 -0700)]
mips,cpu: Get rid of the IsDpsOp StaticInst flag.
This flag was set by MIPS for a few instructions, but didn't have an
accessor in StaticInst and was never used for anything.
Change-Id: I153cedde0d16cb1d78b2705bd7340ebfd10e4fb6
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/33740
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Bobby R. Bruce [Tue, 15 Sep 2020 16:03:55 +0000 (09:03 -0700)]
misc: Merge branch 'release-staging-v20.1.0.0' into develop
Change-Id: I1eacbc5719aa85c5a7650ec33fd99f673fdf443d
Bobby R. Bruce [Tue, 15 Sep 2020 03:29:24 +0000 (20:29 -0700)]
cpu,misc: Revert problematic terminology renames in BaseCPU
Due to gem5's use of duck-typing, we must termorarly revert the
terminology in BaseCPU back to master/slave to avoid issues.
This fixes https://gem5.atlassian.net/browse/GEM5-775.
Change-Id: Idf1cb99aa9568ee70943ebec96f27394d8167f8c
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/34495
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>
Earl Ou [Fri, 11 Sep 2020 01:03:04 +0000 (09:03 +0800)]
systemc: avoid dynamic_cast in the critical path
NodeList is in the critical path of the systemc scheduler in gem5. A
unnecessary dynamic_cast in the NodeList slow down the event process by
about 15%. Fix the issue by avoiding dynamic_cast.
We see about 15% speed improvement on the example provided by Matthias Jung:
https://gist.github.com/myzinsky/
557200aa04556de44a317e0a10f51840
Compare with Accellera implementation, gem5 version is originally 10x
slower and now it's about 8.5x slower.
Change-Id: I3b4ddca31e58e1d4e96144a4021b0a5bb956fda4
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/34355
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Gabe Black [Sun, 30 Aug 2020 08:38:47 +0000 (01:38 -0700)]
mips,cpu: Get rid of the IsIprAccess StaticInst flag.
This was set by MIPS in two places, I think largely just because it was
available. This flag refers to IPRs which are an Alpha concept. In the
O3 CPU, IsIprAccess was used as a possible indicator to determine if an
instruction IsSerializeBefore, but we've already got a flag for that. In
the minor CPU, which hasn't been made to work with MIPS as far as I
know, it was used in a condition but not mentioned in the comment
alongside the condition. I think there it was added for the sake of
Alpha.
This change eliminates that flag and removes it from the O3 and minor
CPUs. In the MIPS ISA description, the instructions that were marked as
IsIprAccess have now been marked as IsSerializeBefore since, if there
was a real reason for them to be marked as IsIprAccess, it would have
been to get it them to work in O3, and there IsSerializeBefore gets
equivalent behavior.
Change-Id: Ia874cde12fa70b998d3e638458f13d69798d40b7
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/33739
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Gabe Black [Sun, 30 Aug 2020 08:32:43 +0000 (01:32 -0700)]
mips,cpu: Get rid of the IsERET StaticInst flag.
This is set by MIPS but doesn't have an accessor in StaticInst, and
isn't used by anything.
Change-Id: Ie28d2df134dcf264bca17c9c66dd32515a240492
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/33738
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Gabe Black [Sun, 30 Aug 2020 08:31:20 +0000 (01:31 -0700)]
cpu: Get rid of the IsThreadSync StaticInst flag.
This flag was never set and only checked in one place. If it was set, it
would have triggered a panic there.
Change-Id: I934a0346837c66bae8ce06f50027003bfd47083d
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/33737
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Gabe Black [Sun, 30 Aug 2020 08:29:18 +0000 (01:29 -0700)]
mips,cpu: Get rid of the IsCondDelaySlot StaticInst flag.
This is set by MIPS in a few places, but not actually used by anything.
Change-Id: Iaf3b29b2c14bb1de3ffd6a0035f12f238591cb60
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/33736
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Gabe Black [Mon, 7 Sep 2020 02:03:12 +0000 (19:03 -0700)]
sparc,sim: Remove special handling of SPARC in the clone system call.
We can set the extra syscall return values in the ISA specific archClone
function. We don't need a special #ifdef to handle them.
Change-Id: I82904b3d4bdf211c89d271d7277a60151191cdfc
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/34167
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Ciro Santilli <ciro.santilli@arm.com>
Jason Lowe-Power [Fri, 11 Sep 2020 20:26:29 +0000 (13:26 -0700)]
mem-ruby: Update port names in Ruby
After the terminology update commit there were still many confusing
names in the Ruby ports. This changeset is a proposal for updating these
names.
For an example use case, see the following resources changeset.
https://gem5-review.googlesource.com/c/public/gem5-resources/+/34416
Change-Id: I01d4f24a70b300e39438ee147dfab7a8d674d5c7
Signed-off-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/34417
Reviewed-by: Ayaz Akram <yazakram@ucdavis.edu>
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>
Jason Lowe-Power [Fri, 11 Sep 2020 18:32:05 +0000 (11:32 -0700)]
tests: Remove MIPS from Learning gem5 tests
Change-Id: Iffd9f5da188cac26ac75a8109886c36789956959
Signed-off-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/34415
Reviewed-by: mike upton <michaelupton@gmail.com>
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>
Jason Lowe-Power [Fri, 11 Sep 2020 20:32:06 +0000 (13:32 -0700)]
dev: Fix port name in x86 device
Change-Id: I7704109287b9a1a09e51da3c62c29720631ce87e
Signed-off-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/34435
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>
Andreas Sandberg [Fri, 11 Sep 2020 18:01:44 +0000 (19:01 +0100)]
stats: Move global CPU stats to BaseCPU
We currently register global CPU statistics such as sim_insts and
sim_ops from stat_control.cc. This adds an undesriable dependency on
BaseCPU from stats_contro.cc. Move the CPU-specific stats to a global
stat group in BaseCPU. This group is merged with the Root object's
stats which means that they appear as global stats in a typical stat
dump.
Care has been taken to keep the old stat names. However, the order of
the stats.txt will be slightly different due to the way legacy stats
and new-style stats are serialised.
Change-Id: I5410bc432f1a8cf3de58b08ca54a1aa2711d9c76
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/34395
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Andreas Sandberg [Mon, 7 Sep 2020 11:34:02 +0000 (12:34 +0100)]
base, sim, mem, arch: Remove the dummy CPU in NULL
The NULL ISA target has a dummy BaseCPU class that doesn't seem to be
needed anymore. Remove this class and the some unnecessary includes.
Change-Id: I031c999b3c0bb8dec036ad087a3edb2c1c723501
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/34236
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Gabe Black <gabeblack@google.com>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Tested-by: kokoro <noreply+kokoro@google.com>
Giacomo Travaglini [Fri, 11 Sep 2020 20:40:54 +0000 (21:40 +0100)]
arch-arm: Fix ArmISA namespace requirement for Arm KVM
This is needed after:
https://gem5-review.googlesource.com/c/public/gem5/+/34155
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Change-Id: I614b908a48145d8c2f5e8b8177448e3269f8dac9
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/34418
Reviewed-by: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Muhammad Sarmad Saeed [Fri, 24 Jul 2020 22:08:27 +0000 (22:08 +0000)]
misc: Update documentation of SimObject related APIs
Updated documentation of Drain, Serialize, Evnet queue and Simobject
APIs. Made some corrections to where the documentation was available
in the code but did not appear in the documentation.
Change-Id: I5254e87eb5663232e824bcd5592da0a04eba673b
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/31814
Reviewed-by: Ayaz Akram <yazakram@ucdavis.edu>
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Srikant Bharadwaj [Thu, 10 Sep 2020 07:39:45 +0000 (03:39 -0400)]
mem-garnet: Upgrade garnet version to 3.0
This version of garnet includes HeteroGarnet which
supports heterogenous interconnect systems, flexible
router and link configurations, and better debugging
resources.
This patch changes the garnet directory structure
to not include the version number. The user will be
informed about the garnet version being used.
Change-Id: Id4763421528305193ae0cd10c159b385a9513553
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/34259
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Jason Lowe-Power [Thu, 10 Sep 2020 21:58:15 +0000 (14:58 -0700)]
arch-arm: Initialize some cases of destReg
Some compilers complained that this variable may be uninitialized. This
change initializes it to 0.
Change-Id: I201d75ba05ce49d13bbaf4d67e1c728ef704fdf0
Signed-off-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/34335
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Reviewed-by: mike upton <michaelupton@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Jason Lowe-Power [Thu, 10 Sep 2020 19:06:56 +0000 (12:06 -0700)]
tests: Update x86 system.py for MemCtrl interface
Change-Id: If4103b197720f74df70d0a24602e2b3715936826
Signed-off-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/34315
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Reviewed-by: mike upton <michaelupton@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Srikant Bharadwaj [Thu, 10 Sep 2020 06:33:51 +0000 (02:33 -0400)]
mem-garnet: Allow empty vnet list for garnet network links
An empty supporting_vnet list is the default and implies that
all vnets are supported. This removes the assert which requires
the list to have a minimum list size of 1.
Change-Id: I6710ba06041164bbd597d98e75374a26a1aa5655
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/34258
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Srikant Bharadwaj [Thu, 10 Sep 2020 06:31:43 +0000 (02:31 -0400)]
mem-garnet: Fix default value of network bridge
Initializing the network bridge with NULL causes it to have
an class error when instatiating a link. The bridge is only
needed whne either a CDC or SerDes is enabled. This is handled
later during construction of the GarnetLink.
Change-Id: If19a21a6d9bf49449b9c390467d08d3422ae991a
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/34257
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Shivani Parekh [Mon, 24 Aug 2020 18:47:44 +0000 (11:47 -0700)]
misc: Replaced master/slave terminology
Change-Id: I4df2557c71e38cc4e3a485b0e590e85eb45de8b6
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/33553
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>
Dimitrios Chasapis [Thu, 10 Sep 2020 11:53:35 +0000 (13:53 +0200)]
configs,python: Fixes an issue with python3 and the config scripts when restoring a checkpoint
Fixes a compatibility issue with the configuration scripts when trying to restore a checkpoint. Since python2.4 list.sort has an updated interface. The older one has been dropped in python3.
Jira Issue: https://gem5.atlassian.net/browse/GEM5-754
Change-Id: I09f819057d510e477d6ceae0356fafad40f4280d
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/34295
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Mahyar Samani [Sat, 2 May 2020 02:19:19 +0000 (02:19 +0000)]
tests: cross-compiling hello binaries for hello_se tests.
Some of the hello_se tests fail due to different syntax of the string
for different isas. This patch adds makefiles for cross-compiling the
hello.c file located at tests/test-progs/hello/src/.
Change-Id: I8ccfc0487020df9da722a97e57310db2d2e8882c
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/28528
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>
Bobby R. Bruce [Thu, 10 Sep 2020 05:26:29 +0000 (22:26 -0700)]
cpu: Fixed unused var error when with fast builds
As `is_htm_speculative` is only used in assert statements, it is
considered unused during the `.fast` compilation. This commit adds the
`M5_USED_VAR` macro.
This caused our compiler tests to fail:
https://www.mail-archive.com/gem5-dev@gem5.org/msg35913.html
Change-Id: I00d187d1a31d065c236ac29a657bd479ad4b03bc
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/34256
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Reviewed-by: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Iru Cai [Thu, 10 Sep 2020 06:18:19 +0000 (14:18 +0800)]
arch-arm: just return the fault in twoEqualRegInst{,Fp}
This prevents the code from using the uninitialized destReg when
running the ``if (imm >= eCount)`` branch, which will make GCC 10.2
report a -Werror=maybe-uninitialized error when building gem5.opt.
Change-Id: Ie6e7d3d47a1b65b840b2106263ecfc21eb6af26b
Signed-off-by: Iru Cai <mytbk920423@gmail.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/34275
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Iru Cai [Fri, 21 Aug 2020 07:11:39 +0000 (15:11 +0800)]
arch-arm: Fix build errors with gcc 10.2
The "-Werror=type-limits" flag in GCC 10.2 reports these errors,
because ``imm`` in neon.isa, and ``imm`` and ``count`` in sve.isa are
unsigned, and they're used to do ``imm < 0`` and ``imm * count >= 0``
comparison.
Change-Id: I33934357f578a9fc1040a6d9c08ea929fb36eb47
Signed-off-by: Iru Cai <mytbk920423@gmail.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/33154
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Richard Cooper <richard.cooper@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Andreas Sandberg [Mon, 24 Aug 2020 17:00:57 +0000 (18:00 +0100)]
dev: Use the new ByteOrder param type in VirtIO devices
VirtIO devices currently request their endianness from the System
object. Instead of explicitly querying the system for its endianness,
expose the device's endianness as a param. This param defaults to the
endianness of a parent object using the Parent proxy (in practice the
system).
Change-Id: If4f84ff61f4d064bdd015a881790f5af03de6535
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/33296
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Gabe Black <gabeblack@google.com>
Andreas Sandberg [Mon, 24 Aug 2020 16:55:45 +0000 (17:55 +0100)]
dev: Use the new ByteOrder param type in SimpleUart
Use the new ByteOrder param type in SimpleUart. The default value is
currently little endian. However, it is expected that most users of
this device will use single-byte accesses which aren't affected by
endianness.
Change-Id: I3f5d4ea566e5127474cff976332bd53c5b49b9e2
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/33295
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Gabe Black [Mon, 18 May 2020 13:10:15 +0000 (06:10 -0700)]
fastmodel: Add an ISA class which defers to IRIS.
This class is just to enable checkpointing of "ISA" state, aka the
MiscRegs.
Change-Id: I45315b8aaa09aaf6230f44665c13597400efd780
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/29822
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Gabe Black [Tue, 5 May 2020 05:44:02 +0000 (22:44 -0700)]
fastmodel: Create a fake "Interrupts" object for fast model CPUs.
This object doesn't actually manage interrupts since the fast model
CPUs do that on their own, it just checkpoints interrupt related state.
Change-Id: I9d3a6354b02e4ae7bfd032c50e51a3a841b81388
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/29821
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Bobby R. Bruce [Thu, 10 Sep 2020 00:24:05 +0000 (17:24 -0700)]
arch-mips: Replaced `BigEndianByteOrder` in MIPS
The following change removed the `BigEndianByteOrder` enum and replaced
it with `ByteOrder:big`:
https://gem5-review.googlesource.com/c/public/gem5/+/33174
This change was not propogated to `src/arch/mips/isa/decoder.isa` and
`src/arch/mips/isa/formats/mem.isa`, and therefore caused compilation
errors. This caused the Nightly Build to fail:
https://www.mail-archive.com/gem5-dev@gem5.org/msg35900.html
This commit fixes this error.
Change-Id: I3967eb9e9236a7a95318c17ca410b613b8473eed
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/34255
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Giacomo Travaglini [Wed, 9 Sep 2020 09:33:58 +0000 (10:33 +0100)]
arch-arm: Fix ArmISA namespace requirement for TME instructions
This is needed after:
https://gem5-review.googlesource.com/c/public/gem5/+/34155
Change-Id: I8ef0b5ce9cd5ae5224331e1c9347fdd9e884a536
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/34235
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Emily Brickey [Tue, 25 Aug 2020 21:11:47 +0000 (14:11 -0700)]
cpu-o3: convert rename to new style stats
Change-Id: Id34a85e40ad7e83d5805a034df6e0c5ad9b9af82
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/33397
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Emily Brickey [Tue, 25 Aug 2020 21:42:27 +0000 (14:42 -0700)]
cpu-o3: convert rob to new style stats
Change-Id: I84430d50c49742cd536dd75ce25184c2316dce51
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/33398
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Emily Brickey [Tue, 25 Aug 2020 16:39:48 +0000 (09:39 -0700)]
cpu-o3: convert lsq_unit to new style stats
Removes unused stats: invAddrLoads, invAddrSwpfs, lsqBlockedLoads
Change-Id: Icd7fc6d8a040f4a1f9b190409b7cdb0a57fd68cf
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/33394
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Emily Brickey [Mon, 24 Aug 2020 16:58:30 +0000 (09:58 -0700)]
cpu-o3: convert decode to new style stats
Change-Id: Ia67a51f3b2c2d40d8bf09f1636c721550f5e9a23
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/33316
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Emily Brickey [Wed, 19 Aug 2020 19:20:25 +0000 (12:20 -0700)]
cpu-o3: convert commit to new style stats
Change-Id: I859fe753d1a2ec2da8a4209d1db122f1014af5d6
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/33315
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Andreas Sandberg [Fri, 21 Aug 2020 10:55:00 +0000 (11:55 +0100)]
sim: Expose the system's byte order as a param
There are cases where a system's byte order isn't well-defined from an
ISA. For example, Arm implementations can be either big or little
endian, sometimes depending on a boot parameter. Decouple the CPU byte
order from the System's default byte order by exposing the System's
byte order as a parameter that defaults to big endian for SPARC and
POWER and little endian for everything else.
Change-Id: I24f87ea3a61b05042ede20dea6bb056af071d2c0
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/33175
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Gabe Black <gabeblack@google.com>
Gabe Black [Wed, 9 Sep 2020 00:49:46 +0000 (17:49 -0700)]
mem: Remove the unused nvm private member from NVMInterface::Rank.
This unused (and otherwise unusable) member caused a compiler warning
and broke the build for me. It can be reintroduced if used in the
future.
Change-Id: I48181f6bca60c059e74727290950adfb9a194680
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/34217
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Gabe Black [Wed, 9 Sep 2020 00:46:39 +0000 (17:46 -0700)]
cpu: Fix style and add overrides to bas_dyn_inst.hh.
Either return types, brackets and the function body should all be on
their own line, or the entire function should be on a single line.
Consistently place the * or & up against the variable name and not the
type name. There isn't an official rule for which to use, but the
majority of existing uses were this way.
Add overrides for overridden virtual methods.
These fixes get rid of compiler warnings which are breaking the build
for me.
Change-Id: Ifc6ace4794a66ffd031ee686f6b6ef888004d786
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/34216
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Gabe Black [Wed, 9 Sep 2020 00:45:16 +0000 (17:45 -0700)]
arch: Add a virtual destructor to BaseHTMCheckpoint.
Since it has virtual methods, it should also have a virtual destructor.
My compiler complains otherwise, which breaks my build.
Change-Id: I44bba97b76931bab6e3511fcdee79831080c12d4
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/34215
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
eavivi [Wed, 2 Sep 2020 17:35:27 +0000 (10:35 -0700)]
cpu-minor: convert fetch2 to new style stats
Change-Id: Idfe0f1f256c93209fe51140b9cab3b454153c597
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/33975
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Gabe Black [Sun, 6 Sep 2020 12:01:48 +0000 (05:01 -0700)]
arm: Remove "using namespace ArmISA" from arch/arm/isa_traits.hh.
This has been in this file since it was created in 2009. No global "using
namespace ${NAMESPACE}" should ever appear in a .hh file since then that
namespace is "used" in all files that include the .hh, even if they
aren't aware of it or even actively don't want to.
Change-Id: Idb7d7c5b959077eb4905fbb2044aa55959b8f37f
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/34155
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Timothy Hayes [Fri, 25 Oct 2019 14:33:18 +0000 (15:33 +0100)]
arch-arm: Transactional Memory Extension (TME)
This patch extends the generic hardware transactional memory support in
Ruby and the O3/TimingSimpleCPU cores with the Arm-specific hardware
transactional memory architectural extensions (TME).
JIRA: https://gem5.atlassian.net/browse/GEM5-588
Change-Id: I8c663da977ed3e8c94635fcb11834bd001e92054
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/30329
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Hoa Nguyen [Thu, 20 Aug 2020 18:48:02 +0000 (11:48 -0700)]
base,misc: Add group definitions for newly tagged API in src/base
Signed-off-by: Hoa Nguyen <hoanguyen@ucdavis.edu>
Change-Id: If2f5ce3bc4f5d0a8cc31def17702223a27e6970e
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/33034
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Michael Boyer [Tue, 28 Apr 2020 18:02:41 +0000 (14:02 -0400)]
mem-ruby: Check number of vnets when creating links
Added error checking to ensure that the system has sufficient virtual
networks when setting latency and weight values.
Change-Id: I1b28144bbe9fefab0c0a6227f1fdf4ea10403061
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/32603
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Gabe Black [Mon, 7 Sep 2020 06:21:48 +0000 (23:21 -0700)]
dev,arm: Use the ArmSystem::PageBytes constant in the generic timer.
This component very specific to ARM, and so there's no reason to use
generic interfaces to get the page size.
Change-Id: Id757b5742c807c5f616a6dc8df94a7709932d071
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/34171
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Gabe Black [Mon, 7 Sep 2020 06:20:17 +0000 (23:20 -0700)]
arm: Replicate the PageBytes constant in the ArmSystem class.
When isa_traits.hh hopefully goes away in the not too distant future,
this constant will need somewhere to live so ARM components can find it.
There are valid arguments that this should not be a constant in the
first place, but that's outside the scope of this change.
Change-Id: Ic5bd046dc1cc196b3cf6b6c36878fdbf5eb4c0bf
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/34170
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
eavivi [Tue, 1 Sep 2020 00:28:57 +0000 (17:28 -0700)]
cpu: convert trace cpu to new style stats
This required making minor changes to how the name was set for the
generators within the trace CPU to enable the stats to keep similar
names.
Change-Id: I9f97d4006a0edbd717fc34d0033b9548011d1631
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/33875
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Ayaz Akram <yazakram@ucdavis.edu>
Emily Brickey [Tue, 25 Aug 2020 23:05:41 +0000 (16:05 -0700)]
cpu-o3: convert elastic trace to new style stats
Change-Id: If767f17b905a77e12058022a9e8bc65b854978a4
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/33399
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Hoa Nguyen [Thu, 3 Sep 2020 08:36:35 +0000 (01:36 -0700)]
ext,tests: Copy test's output files from /tmp to testing-results
When a test is complete, the output files are in a random folder
in /tmp.
This commit adds a procedure copying those files to
testing-results/SuiteUID/TestUID/ folder, where SuiteUID and
TestUID are the corresponding uid's of the test.
This procedure is triggered after a test is complete and before
the folder in /tmp being removed.
Change-Id: Id960e7f2f1629769008ae99aff4c8bfafa9ca849
Signed-off-by: Hoa Nguyen <hoanguyen@ucdavis.edu>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/33998
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Hoa Nguyen [Thu, 3 Sep 2020 08:35:24 +0000 (01:35 -0700)]
ext: Add post_test_procedure to testlib runner
This procedure is trigger after a test has finished and before
the tearing down process kicks in.
Change-Id: I58ce10814fbc80d96f2f72565491b18de0ec290a
Signed-off-by: Hoa Nguyen <hoanguyen@ucdavis.edu>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/33997
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Hoa Nguyen [Sat, 29 Aug 2020 09:35:11 +0000 (02:35 -0700)]
ext: Force testlib to only create one Log object
Log object should remain being a singleton throughout the program.
The current code creates multiple Log objects, which at least
causes the issues of missing outputs in stdout.
E.g., "Logging call to command", which logs which command is
being called in a subprocess, is missing from stdout.
Change-Id: I96c5dd79c4f14e0a013c15d42d202397488d56b6
Signed-off-by: Hoa Nguyen <hoanguyen@ucdavis.edu>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/33715
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
eavivi [Fri, 4 Sep 2020 21:54:14 +0000 (14:54 -0700)]
cpu: convert memtest to new style stats
Change-Id: I91b17dd46fd0f70816159ea14c1c8f498048c696
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/34137
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Wendy Elsasser [Tue, 21 Jul 2020 04:09:21 +0000 (23:09 -0500)]
mem: Clean up Memory Controller
Make the actual controller more generic
- Rename DRAMCtrl to MemCtrl
- Rename DRAMacket to MemPacket
- Rename dram_ctrl.cc to mem_ctrl.cc
- Rename dram_ctrl.hh to mem_ctrl.hh
- Create MemCtrl debug flag
Move the memory interface classes/functions to separate files
- mem_interface.cc
- mem_interface.hh
Change-Id: I1acba44c855776343e205e7733a7d8bbba92a82c
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/31654
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Wendy Elsasser [Wed, 1 Apr 2020 17:39:42 +0000 (12:39 -0500)]
mem: Add NVM interface
Add NVM interface to memory controller.
This can be used with or instead of the existing
DRAM interface. Therefore, a single controller can interface
to either DRAM or NVM, or both.
Specifically, a memory channel can be configured as:
- Memory controller interfacing to DRAM only
- Memory controller interfacing to NVM only
- Memory controller interfacing to both DRAM and NVM
How data is placed or migrated between media types is outside
of the scope of this change.
The NVM interface incorporates new static delay parameters
for read and write completion. The interface defines a 2
stage read to manage non-deterministic read delays while
enabling deterministic data transfer, similar to NVDIMM-P.
The NVM interface also includes parameters to define
read and write buffers on the media side (on-DIMM). These are
utilized to quickly offload commands and write data, mitigating
the effects of lower latency and bandwidth media characteristics.
Change-Id: I6b22ddb495877f88d161f0bd74ade32cc8fdcbcc
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/29027
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Wendy Elsasser <wendy.elsasser@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Wendy Elsasser [Sat, 8 Feb 2020 00:00:57 +0000 (18:00 -0600)]
mem: Make MemCtrl a ClockedObject
Made DRAMCtrl a ClockedObject, with DRAMInterface
defined as an AbstractMemory. The address
ranges are now defined per interface. Currently
the model only includes a DRAMInterface but this
can be expanded for other media types.
The controller object includes a parameter to the
interface, which is setup when gem5 is configured.
Change-Id: I6a368b845d574a713c7196c5671188ca8c1dc5e8
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/28968
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Wendy Elsasser [Mon, 18 Nov 2019 22:56:13 +0000 (16:56 -0600)]
mem: Factor out DRAM interface
Separate out the DRAM specific functions into a new class:
- DRAMInterface
Move the Rank class to DRAMInterface since rank functions are
specific to the media.
Move DRAMPacket and Bank class definitions outside of DRAMCtrl.
This is patch 1 within a set of patches that separate the
memory controller and media interface. These changes enable
future incorporation of new media interfaces into the model.
Change-Id: Ief632d73ec27176a61f16b4f642c10d56630f376
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/28967
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Hoa Nguyen [Thu, 3 Sep 2020 08:45:27 +0000 (01:45 -0700)]
ext: Make the testing-results folder visible
Currently, testlib will write outputs to .testing-results, which
is a hidden folder. However, the outputs in the folder are useful
for debugging. This commit makes this folder visible on Linux
systems.
Change-Id: I158e1a4a62c7b494309a0a4bf6521fedd04cbe22
Signed-off-by: Hoa Nguyen <hoanguyen@ucdavis.edu>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/34015
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Hoa Nguyen [Thu, 20 Aug 2020 06:53:03 +0000 (23:53 -0700)]
base: Tag API methods in crc.hh
Change-Id: I4fc8977dad705a6774f649479184cdfb15aa2be5
Signed-off-by: Hoa Nguyen <hoanguyen@ucdavis.edu>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/32961
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Hoa Nguyen [Mon, 24 Aug 2020 05:46:41 +0000 (22:46 -0700)]
base: Tag API methods to debug.hh
Change-Id: Ic4395f3594cbc156a2b678710a3ed4717ce87a81
Signed-off-by: Hoa Nguyen <hoanguyen@ucdavis.edu>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/33257
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Hoa Nguyen [Mon, 24 Aug 2020 04:41:21 +0000 (21:41 -0700)]
base: Tag API methods in inet.hh
Change-Id: Id53ab873c7de9de7ccb99ff8434827aeec676c30
Signed-off-by: Hoa Nguyen <hoanguyen@ucdavis.edu>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/33254
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>
Hoa Nguyen [Thu, 20 Aug 2020 06:50:48 +0000 (23:50 -0700)]
base: Tag API variables in date.cc
Change-Id: I5a90f6496ef1e39b6135a14dfdf3f5febd22ece2
Signed-off-by: Hoa Nguyen <hoanguyen@ucdavis.edu>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/32974
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Hoa Nguyen [Thu, 20 Aug 2020 20:54:34 +0000 (13:54 -0700)]
base: Tag API methods in flags.hh
Change-Id: I12eb94b43e190ee46f82fba7d2a3ef6c29fdee80
Signed-off-by: Hoa Nguyen <hoanguyen@ucdavis.edu>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/33035
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Hoa Nguyen [Fri, 21 Aug 2020 01:21:29 +0000 (18:21 -0700)]
base: Tag API variables in version.cc
Change-Id: I49438963a1cdb82b00fa6bea153d55b8cdbfcf33
Signed-off-by: Hoa Nguyen <hoanguyen@ucdavis.edu>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/33079
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Hoa Nguyen [Thu, 20 Aug 2020 23:17:34 +0000 (16:17 -0700)]
base: Tag API methods in intmath.hh
Change-Id: Ia50830c7620380ff2aba081f56f74822aff982bf
Signed-off-by: Hoa Nguyen <hoanguyen@ucdavis.edu>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/33075
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Hoa Nguyen [Fri, 21 Aug 2020 00:46:04 +0000 (17:46 -0700)]
base: Tag API methods in sat_counter.hh
Change-Id: Id5da647f35cca30276bb34b745999f4571a47d89
Signed-off-by: Hoa Nguyen <hoanguyen@ucdavis.edu>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/33117
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Hoa Nguyen [Thu, 20 Aug 2020 22:03:53 +0000 (15:03 -0700)]
base: Tag API methods in condcodes.hh
Change-Id: Ife6b5ed6ee684b65790c374ab6e709ce8eb708ad
Signed-off-by: Hoa Nguyen <hoanguyen@ucdavis.edu>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/33074
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>
Hoa Nguyen [Mon, 24 Aug 2020 04:56:06 +0000 (21:56 -0700)]
base: Tag API methods to trace.hh
Change-Id: Ia2ad759b9bee4fd3413abd62cfa6b120616a14f9
Signed-off-by: Hoa Nguyen <hoanguyen@ucdavis.edu>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/33255
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>
Hoa Nguyen [Mon, 24 Aug 2020 05:23:45 +0000 (22:23 -0700)]
base: Tag API methods in remote_gdb.hh
Change-Id: I7d4d6ce8a2b18a365561ad88434fea7d6823d310
Signed-off-by: Hoa Nguyen <hoanguyen@ucdavis.edu>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/33256
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>
Hoa Nguyen [Fri, 21 Aug 2020 01:14:04 +0000 (18:14 -0700)]
base: Tag API methods in stl_helpers.hh
Change-Id: Ibc967febfd29444214094883121a66600d80cad8
Signed-off-by: Hoa Nguyen <hoanguyen@ucdavis.edu>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/33118
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>
Hoa Nguyen [Thu, 20 Aug 2020 23:40:59 +0000 (16:40 -0700)]
base: Tag API methods in pollevent.hh
Change-Id: Ic2eb596c873fc4917cf650c2e240310b1e025fa5
Signed-off-by: Hoa Nguyen <hoanguyen@ucdavis.edu>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/33114
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>
Hoa Nguyen [Thu, 20 Aug 2020 05:58:01 +0000 (22:58 -0700)]
base: Tag API methods and variables in addr_range.hh
Change-Id: I4bff99ecf1e0eeab4a76574e99163303f7dec83b
Signed-off-by: Hoa Nguyen <hoanguyen@ucdavis.edu>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/32955
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Hoa Nguyen [Thu, 20 Aug 2020 06:33:36 +0000 (23:33 -0700)]
base: Tag API methods and variables in callback.hh
Change-Id: I4ff6d9914e6edb4e8e7b033aec4b26482e950cc0
Signed-off-by: Hoa Nguyen <hoanguyen@ucdavis.edu>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/32959
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>
Hoa Nguyen [Thu, 20 Aug 2020 06:28:01 +0000 (23:28 -0700)]
base: Tag API methods and variables in bitunion.hh
Change-Id: I322645801e9832014f54d4ed633796b082b06c6b
Signed-off-by: Hoa Nguyen <hoanguyen@ucdavis.edu>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/32958
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Hoa Nguyen [Fri, 21 Aug 2020 01:25:10 +0000 (18:25 -0700)]
base: Tag API methods and variables in trie.hh
Change-Id: I4492dbb997a3ece5cb2675b45bf37d7512449ab6
Signed-off-by: Hoa Nguyen <hoanguyen@ucdavis.edu>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/33080
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>
Hoa Nguyen [Fri, 21 Aug 2020 01:09:52 +0000 (18:09 -0700)]
base: Tag API methods in socket.hh
Change-Id: Ifdbe1d9367df602e45fa3d39c91de9e0f8f1d87e
Signed-off-by: Hoa Nguyen <hoanguyen@ucdavis.edu>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/33078
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Hoa Nguyen [Thu, 20 Aug 2020 06:39:36 +0000 (23:39 -0700)]
base: Tag API methods and variables in channel_addr.hh
Change-Id: I91c806e88f035457f93dcfcee1833d6955a07807
Signed-off-by: Hoa Nguyen <hoanguyen@ucdavis.edu>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/32960
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>
Hoa Nguyen [Thu, 20 Aug 2020 06:05:01 +0000 (23:05 -0700)]
base: Tag API methods and variables in addr_range_map.hh
Change-Id: I9dc630e7c0d0826a20f032879346da6327b38a2d
Signed-off-by: Hoa Nguyen <hoanguyen@ucdavis.edu>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/32956
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>
Hoa Nguyen [Mon, 24 Aug 2020 05:06:50 +0000 (22:06 -0700)]
base: Tag API methods in amo.hh
Change-Id: I8014d729611721dd15ee27a974acbab2744c5e82
Signed-off-by: Hoa Nguyen <hoanguyen@ucdavis.edu>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/33274
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>
Hoa Nguyen [Thu, 20 Aug 2020 23:57:46 +0000 (16:57 -0700)]
base: Tag API methods and variables in random.hh
Change-Id: I75f8843ee696055f156aa0d9e035094d8206f4b9
Signed-off-by: Hoa Nguyen <hoanguyen@ucdavis.edu>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/33115
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>
Andreas Sandberg [Fri, 21 Aug 2020 10:53:18 +0000 (11:53 +0100)]
base, sim: Make ByteOrder into a ScopedEnum accessible to Python
There is currently no good way of passing a byte order as a Param
since the ByteOrder type is defined in C++. Make this into a generated
ScopedEnum that can be used in Params.
Change-Id: I990f402340c17c4e0799de57df19516ae61794d4
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/33174
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Gabe Black <gabeblack@google.com>
Hoa Nguyen [Thu, 20 Aug 2020 07:08:07 +0000 (00:08 -0700)]
base: Tag API methods and variables to circular_queue.hh
Change-Id: I0e6a89a3e3d14a6d269277e1ffeea1ed49d8e1e4
Signed-off-by: Hoa Nguyen <hoanguyen@ucdavis.edu>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/32962
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>
Hoa Nguyen [Thu, 20 Aug 2020 06:44:40 +0000 (23:44 -0700)]
base: Tag API methods and variables in chunk_generator.hh
Change-Id: I8dbcef360ec1c5539fc415781729fcb86112fdbc
Signed-off-by: Hoa Nguyen <hoanguyen@ucdavis.edu>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/32935
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>
Hoa Nguyen [Thu, 20 Aug 2020 23:24:05 +0000 (16:24 -0700)]
base: Tag API methods and macros in logger.hh
Change-Id: I36c4d39eb26fc3af1683ec648df91d6055be97ba
Signed-off-by: Hoa Nguyen <hoanguyen@ucdavis.edu>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/33076
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
projects / gem5.git / log