Steve Reinhardt [Thu, 23 Feb 2006 02:11:45 +0000 (21:11 -0500)]
Clean excess comments out of SConscripts.
SConscript:
arch/alpha/SConscript:
Clean out excess comments.
--HG--
extra : convert_revision :
7aae68d36f9fce5f236d117d803b5e3cd4a3769d
Gabe Black [Wed, 22 Feb 2006 01:10:40 +0000 (20:10 -0500)]
Changed Fault * to Fault, which is a typedef to FaultBase *, which is the old Fault class renamed.
--HG--
extra : convert_revision :
5b2f457401f8ff94fe39fe071288eb117814b7bb
Gabe Black [Tue, 21 Feb 2006 08:38:21 +0000 (03:38 -0500)]
Made Addr a global type
--HG--
extra : convert_revision :
869bd9fa5d8591115ac9b4a7401eb2490986b835
Gabe Black [Tue, 21 Feb 2006 04:55:25 +0000 (23:55 -0500)]
Merge zizzer.eecs.umich.edu:/z/m5/Bitkeeper/m5
into zizzer.eecs.umich.edu:/z/m5/Bitkeeper/multiarch
--HG--
extra : convert_revision :
da72b3593037c2a67a56c799e292853b8aece907
Gabe Black [Tue, 21 Feb 2006 04:54:38 +0000 (23:54 -0500)]
Merge gblack@m5.eecs.umich.edu:/bk/multiarch
into ewok.(none):/home/gblack/m5/multiarch
--HG--
extra : convert_revision :
9d386beecc6d13625ff19ca72cbc3628dcd59d3c
Gabe Black [Tue, 21 Feb 2006 04:53:14 +0000 (23:53 -0500)]
Finished the implementing the change of the ISA from a class to a namespace
dev/sinic.cc:
When DPRINTF disappears, reg32 becomes an unused variable. With -Werror, this causes the compile to fail.
--HG--
extra : convert_revision :
c003c714228491e060155070d192521c53d9e929
Nathan Binkert [Tue, 21 Feb 2006 04:41:50 +0000 (23:41 -0500)]
Get rid of the code that delays PIO write accesses
until the cache access occurs. The fundamental problem
is that a subsequent read that occurs functionally will
get a functionally incorrect result that can break
driver code.
dev/ns_gige.cc:
dev/ns_gige.hh:
dev/sinic.cc:
dev/sinic.hh:
get rid of pio_delay write and the associated code to move
the write to the cache access function
dev/sinicreg.hh:
no more write delays
python/m5/objects/Ethernet.py:
get rid of pio_delay write
--HG--
extra : convert_revision :
1dcb51b8f4514e717bc334a782dfdf06d29ae69d
Korey Sewell [Mon, 20 Feb 2006 19:48:10 +0000 (14:48 -0500)]
make MIPS specific
--HG--
extra : convert_revision :
c019fad60fbf1a316bc6201b8ce8acf5a9875989
Korey Sewell [Mon, 20 Feb 2006 19:30:23 +0000 (14:30 -0500)]
load/store instruction format ... now generates load/store code
and breaks it into a separate EA and MemAccess templated
from how the Alpha ARch. was coded to do the same thing.
arch/mips/isa/bitfields.isa:
comment change
arch/mips/isa/decoder.isa:
re-structuring of load/store instruction definitions
arch/mips/isa/formats/mem.isa:
Define LoadMemory & Store Memory formats
Use style of formatting & base class similar to what was used for ALPHA
arch/mips/isa/formats/util.isa:
Insert LoadStoreBase function here from alpha/arch/isa/mem.isa
arch/mips/isa/operands.isa:
change shw->sh and uhw->uh
--HG--
extra : convert_revision :
5d85f15f4a600dd4c473a3b4a170ba39cf07fc8a
Korey Sewell [Mon, 20 Feb 2006 06:49:16 +0000 (01:49 -0500)]
Support for All Jump Instructions ...
Redo format for Branches and Jumps ( Must update NNPC not NPC )
Now all branches and jumps look like they auto-generate correctly from isa_parser.py!!!
arch/mips/isa/decoder.isa:
Support for All Jump Instructions ..
arch/mips/isa/formats/branch.isa:
Redo format for Branches and Jumps ( Must update NNPC not NPC )
arch/mips/isa/formats/util.isa:
define clear_exe_inst_hazards for later use
--HG--
extra : convert_revision :
63618ed12ee6ed94c47d29619cc1cab2cbaf5cda
Gabe Black [Sun, 19 Feb 2006 09:00:05 +0000 (04:00 -0500)]
Reapplied changes which were undone by a pull
arch/alpha/faults.hh:
kern/linux/linux.hh:
Added typedef for Addr
kern/tru64/tru64.hh:
Fixed up namespaces
--HG--
extra : convert_revision :
bf968e615bc0acc96abeb0eec0872f5b02b5a065
Gabe Black [Sun, 19 Feb 2006 08:20:05 +0000 (03:20 -0500)]
Merge zizzer.eecs.umich.edu:/z/m5/Bitkeeper/m5
into zizzer.eecs.umich.edu:/z/m5/Bitkeeper/multiarch
arch/alpha/faults.hh:
ur
Using cleaned up fault class dei
\7ff
\7ffinitions
--HG--
extra : convert_revision :
a600950d539be2be73358f072aa5426456bf3d2d
Gabe Black [Sun, 19 Feb 2006 08:04:44 +0000 (03:04 -0500)]
Remade some changes which were undone
cpu/base.hh:
cpu/static_inst.hh:
Changed include of targetarch/isa_traits.hh back to arch/isa_traits.hh
cpu/exec_context.hh:
Changed Fault back to Fault *
--HG--
extra : convert_revision :
410f2e2472f8aa5bf92619a5defdf85f689a5597
Gabe Black [Sun, 19 Feb 2006 07:34:52 +0000 (02:34 -0500)]
Merge gblack@m5.eecs.umich.edu:/bk/multiarch
into ewok.(none):/home/gblack/m5/multiarch
--HG--
extra : convert_revision :
090b30a7f70294e1aeb13ba0bc15da4061bdf348
Gabe Black [Sun, 19 Feb 2006 07:34:37 +0000 (02:34 -0500)]
Changes to untemplate StaticInst and StaticInstPtr, change the isa to a namespace instead of a class, an improvement to the architecture specific header file selection system, and fixed up a few include paths.
arch/alpha/alpha_linux_process.cc:
Added using directive for AlphaISA namespace
arch/alpha/alpha_memory.hh:
arch/alpha/isa/branch.isa:
cpu/pc_event.hh:
Added typedefs for Addr
arch/alpha/alpha_tru64_process.cc:
arch/alpha/arguments.cc:
Added using directive for AlphaISA
arch/alpha/ev5.hh:
Added an include of arch/alpha/isa_traits.hh, and a using directive for the AlphaISA namespace.
arch/alpha/faults.hh:
Added a typedef for the Addr type, and changed the formatting of the faults slightly.
arch/alpha/isa/main.isa:
Untemplatized StaticInst, added a using for namespace AlphaISA to show up in decoder.cc and the exec.ccs, relocated makeNop to decoder.hh
arch/alpha/isa/mem.isa:
Untemplatized StaticInst and StaticInstPtr
arch/alpha/isa/pal.isa:
cpu/base_dyn_inst.cc:
Untemplatized StaticInstPtr
arch/alpha/isa_traits.hh:
Changed variables to be externs instead of static since they are part of a namespace and not a class.
arch/alpha/stacktrace.cc:
Untemplatized StaticInstPtr, and added a using directive for AlphaISA.
arch/alpha/stacktrace.hh:
Added some typedefs for Addr and MachInst, and untemplatized StaticInstPtr
arch/alpha/vtophys.cc:
Added a using directive for AlphaISA
arch/alpha/vtophys.hh:
Added the AlphaISA namespace specifier where needed
arch/isa_parser.py:
Changed the placement of the definition of the decodeInst function to be outside the namespaceInst namespace.
base/loader/object_file.hh:
cpu/o3/bpred_unit.hh:
Added a typedef for Addr
base/loader/symtab.hh:
Added a typedef for Addr, and added a TheISA to Addr in another typedef
base/remote_gdb.cc:
Added a using namespace TheISA, and untemplatized StaticInstPtr
base/remote_gdb.hh:
Added typedefs for Addr and MachInst
cpu/base.cc:
Added TheISA specifier to some variables exported from the isa.
cpu/base.hh:
Added a typedef for Addr, and TheISA to some variables from the ISA
cpu/base_dyn_inst.hh:
Untemplatized StaticInstPtr, and added TheISA specifier to some variables from the ISA.
cpu/exec_context.hh:
Added some typedefs for types from the isa, and added TheISA specifier to some variables from the isa
cpu/exetrace.hh:
Added typedefs for some types from the ISA, and untemplatized StaticInstPtr
cpu/memtest/memtest.cc:
cpu/o3/btb.cc:
dev/baddev.cc:
dev/ide_ctrl.cc:
dev/ide_disk.cc:
dev/isa_fake.cc:
dev/ns_gige.cc:
dev/pciconfigall.cc:
dev/platform.cc:
dev/sinic.cc:
dev/uart8250.cc:
kern/freebsd/freebsd_system.cc:
kern/linux/linux_system.cc:
kern/system_events.cc:
kern/tru64/dump_mbuf.cc:
kern/tru64/tru64_events.cc:
sim/process.cc:
sim/pseudo_inst.cc:
sim/system.cc:
Added using namespace TheISA
cpu/memtest/memtest.hh:
cpu/trace/opt_cpu.hh:
cpu/trace/reader/itx_reader.hh:
dev/ide_disk.hh:
dev/pcidev.hh:
dev/platform.hh:
dev/tsunami.hh:
sim/system.hh:
sim/vptr.hh:
Added typedef for Addr
cpu/o3/2bit_local_pred.hh:
Changed the include to use arch/isa_traits.hh instead of arch/alpha/isa_traits.hh. Added typedef for Addr
cpu/o3/alpha_cpu.hh:
Added typedefs for Addr and IntReg
cpu/o3/alpha_cpu_impl.hh:
Added this-> to setNextPC to fix a problem since it didn't depend on template parameters any more. Removed "typename" where it was no longer needed.
cpu/o3/alpha_dyn_inst.hh:
Cleaned up some typedefs, and untemplatized StaticInst
cpu/o3/alpha_dyn_inst_impl.hh:
untemplatized StaticInstPtr
cpu/o3/alpha_impl.hh:
Fixed up a typedef of MachInst
cpu/o3/bpred_unit_impl.hh:
Added a using TheISA::MachInst to a function
cpu/o3/btb.hh:
Changed an include from arch/alpha/isa_traits.hh to arch/isa_traits.hh, and added a typedef for Addr
cpu/o3/commit.hh:
Removed a typedef of Impl::ISA as ISA, since TheISA takes care of this now.
cpu/o3/cpu.cc:
Cleaned up namespace issues
cpu/o3/cpu.hh:
Cleaned up namespace usage
cpu/o3/decode.hh:
Removed typedef of ISA, and changed it to TheISA
cpu/o3/fetch.hh:
Fized up typedefs, and changed ISA to TheISA
cpu/o3/free_list.hh:
Changed include of arch/alpha/isa_traits.hh to arch/isa_traits.hh
cpu/o3/iew.hh:
Removed typedef of ISA
cpu/o3/iew_impl.hh:
Added TheISA namespace specifier to MachInst
cpu/o3/ras.hh:
Changed include from arch/alpha/isa_traits.hh to arch/isa_traits.hh, and added a typedef for Addr.
cpu/o3/regfile.hh:
Changed ISA to TheISA, and added some typedefs for Addr, IntReg, FloatReg, and MiscRegFile
cpu/o3/rename.hh:
Changed ISA to TheISA, and added a typedef for RegIndex
cpu/o3/rename_map.hh:
Added an include for arch/isa_traits.hh, and a typedef for RegIndex
cpu/o3/rob.hh:
Added a typedef for RegIndex
cpu/o3/store_set.hh:
cpu/o3/tournament_pred.hh:
Changed an include of arch/alpha/isa_traits.hh to arch/isa_traits.hh, and added a typedef of Addr
cpu/ozone/cpu.hh:
Changed ISA into TheISA, and untemplatized StaticInst
cpu/pc_event.cc:
Added namespace specifier TheISA to Addr types
cpu/profile.hh:
kern/kernel_stats.hh:
Added typedef for Addr, and untemplatized StaticInstPtr
cpu/simple/cpu.cc:
Changed using directive from LittleEndianGuest to AlphaISA, which will contain both namespaces. Added TheISA where needed, and untemplatized StaticInst
cpu/simple/cpu.hh:
Added a typedef for MachInst, and untemplatized StaticInst
cpu/static_inst.cc:
Untemplatized StaticInst
cpu/static_inst.hh:
Untemplatized StaticInst by using the TheISA namespace
dev/alpha_console.cc:
Added using namespace AlphaISA
dev/simple_disk.hh:
Added typedef for Addr and fixed up some formatting
dev/sinicreg.hh:
Added TheISA namespace specifier where needed
dev/tsunami.cc:
dev/tsunami_io.cc:
dev/tsunami_pchip.cc:
Added using namespace TheISA. It might be better for it to be AlphaISA
dev/tsunami_cchip.cc:
Added typedef for TheISA. It might be better for it to be AlphaISA
kern/linux/aligned.hh:
sim/pseudo_inst.hh:
Added TheISA namespace specifier to Addr
kern/linux/linux_threadinfo.hh:
Added typedef for Addr, and TheISA namespace specifier to StackPointerReg
kern/tru64/mbuf.hh:
Added TheISA to Addr type in structs
sim/process.hh:
Added typedefs of Addr, RegFile, and MachInst
sim/syscall_emul.cc:
Added using namespace TheISA, and a cast of VMPageSize to the int type
sim/syscall_emul.hh:
Added typecast for Addr, and TheISA namespace specifier for where needed
--HG--
extra : convert_revision :
91d4f6ca33a73b21c1f1771d74bfdea3b80eff45
Ali Saidi [Sun, 19 Feb 2006 05:47:45 +0000 (00:47 -0500)]
Merge zizzer:/bk/m5
into pb15.local:/Users/ali/work/m5.head
--HG--
extra : convert_revision :
774e4afbb0f9c3ae62843138b6d7195ea184ff92
Ali Saidi [Sun, 19 Feb 2006 05:28:53 +0000 (00:28 -0500)]
forgot a negative sign
--HG--
extra : convert_revision :
9cdb00198979fca831d3e6840f9c534671ccead3
Ali Saidi [Sun, 19 Feb 2006 04:44:22 +0000 (23:44 -0500)]
Move Linux/Tru64 architecture independent code into kern/*
leaving dependent code making way for solaris linux syscall emu.
SConscript:
Add two new files for syscall emulation
Add getDesc() function
arch/alpha/alpha_linux_process.cc:
arch/alpha/alpha_tru64_process.cc:
move architecture independent code into kern/linux/linux.(hh|cc)
arch/alpha/alpha_linux_process.hh:
arch/alpha/alpha_tru64_process.hh:
Add getDesc function
kern/linux/linux.hh:
move generi linux syscall emulation code into kern/linux
kern/tru64/tru64.hh:
move generi tru64 syscall emulation code into kern/tru64
sim/process.cc:
sim/process.hh:
Push the function determination and calling stuff down to LiveProcess
and out of the Linux/Tru64 classes respectively
sim/syscall_emul.cc:
sim/syscall_emul.hh:
fnctl implementation was identical in tru64 and linux so moved to generic
--HG--
extra : convert_revision :
103293dbe6fe2f7892de4929d17dc085def77026
Korey Sewell [Sun, 19 Feb 2006 04:17:45 +0000 (23:17 -0500)]
Support NNPC and branch instructions ... Outputs to decoder.cc correctly
Edits to the CPU model may still need to be made to handle branch likely insts...
arch/isa_parser.py:
add a NNPC operand ...
arch/mips/isa/base.isa:
change SPARC to MIPS
arch/mips/isa/decoder.isa:
typo < to >=
arch/mips/isa/formats/basic.isa:
spacing
arch/mips/isa/formats/branch.isa:
add code for branch instructions (still need adjustments for the branch likely)
arch/mips/isa/operands.isa:
support for NNPC and R31
arch/mips/isa_traits.hh:
NNPC Addr variable
--HG--
extra : convert_revision :
df03d2a71c36dbc00270c2e3d7882b4f09ed97ad
Gabe Black [Sun, 19 Feb 2006 01:58:26 +0000 (20:58 -0500)]
Merge gblack@m5.eecs.umich.edu:/bk/multiarch
into ewok.(none):/home/gblack/m5/multiarch
--HG--
extra : convert_revision :
8b2759d670a6a60142be748817ccef736d61dabf
Gabe Black [Sun, 19 Feb 2006 01:58:08 +0000 (20:58 -0500)]
Changed the isa from a class to a namespace, untemplated StaticInst and StaticInstPtr, converted things to using TheISA, cleaned up some header file paths, and improved the system which pulls header files from the appropriate architecture.
--HG--
extra : convert_revision :
5087333fbaf442efb4b55e70376244629fff507d
Lisa Hsu [Sun, 19 Feb 2006 01:10:42 +0000 (20:10 -0500)]
few changes for nate:
1) cosmetic - removing visibility of meta axes except for the tick labels.
2) unless subticklabels defined, don't do meta axes. (instead of assuming if you have 3D graph, do meta axes)
--HG--
extra : convert_revision :
396011ffaa51ea4066b34257f6fd5b3faac9d242
Lisa Hsu [Sat, 18 Feb 2006 23:39:19 +0000 (18:39 -0500)]
remove print statements
--HG--
extra : convert_revision :
abd635034424eeb9685aea777440a02887ce81a6
Lisa Hsu [Sat, 18 Feb 2006 22:29:43 +0000 (17:29 -0500)]
more changes for subtick labels.
util/stats/barchart.py:
oop forgot this for 1D graph cases.
util/stats/chart.py:
need to add default param to chart.
--HG--
extra : convert_revision :
f4e6c6c614d584e7928ed905e97608716455ab6c
Lisa Hsu [Sat, 18 Feb 2006 22:24:37 +0000 (17:24 -0500)]
Merge zizzer:/bk/m5
into zed.eecs.umich.edu:/z/hsul/work/m5/clean
--HG--
extra : convert_revision :
5f7c75eb3f82d9b04edc0efece3b054b5d0fe81f
Lisa Hsu [Sat, 18 Feb 2006 22:24:23 +0000 (17:24 -0500)]
Now you can have sublabels for every bar using the self.xsubticklabels parameter.
--HG--
extra : convert_revision :
a6bdf3a972e81c84947b7d6ae76f828494a125c8
Korey Sewell [Sat, 18 Feb 2006 19:38:23 +0000 (14:38 -0500)]
changes from mergedmem
arch/mips/isa/formats/branch.isa:
add branch_likely member functions
cpu/base.hh:
cpu/exec_context.hh:
cpu/static_inst.hh:
change from mergedmem
--HG--
extra : convert_revision :
d6ad6943e2ef09eac91a466fc5c9bd8e66bf319a
Korey Sewell [Sat, 18 Feb 2006 09:17:11 +0000 (04:17 -0500)]
use string name to figure out if we have a "AndLink" instruction
arch/mips/isa/operands.isa:
uq -> uw
--HG--
extra : convert_revision :
eeac6dba813de8174d080a5fa9b5a396b345113a
Korey Sewell [Sat, 18 Feb 2006 08:12:04 +0000 (03:12 -0500)]
MIPS generates ISA code through scons '.../decoder.cc'!!!
Now, must create g++ compilable code ...
arch/mips/isa/decoder.isa:
missing a '}' ... edited a few instruction decodings ...
arch/mips/isa/formats.isa:
rearranged #include
arch/mips/isa/formats/branch.isa:
add Branch Likely and Unconditional format
arch/mips/isa/formats/int.isa:
move OperateNopCheckDecode template to another file ...
arch/mips/isa/formats/noop.isa:
change Alpha to Mips in noop.isa
--HG--
extra : convert_revision :
4bf955fa6dffbbc99fb95fee7878f691e3df5424
Kevin Lim [Fri, 17 Feb 2006 20:07:48 +0000 (15:07 -0500)]
Get rid of deque (poor memory allocation), switch them over to lists.
Beware that using size() on a list is a O(n) operation.
dev/ns_gige.hh:
Remove typedefs that (I assume) were copied over from etherdev.hh. They were unused in the ns_gige code.
--HG--
extra : convert_revision :
577954ec26b899bd6329ce6a4aaa1d9b0ba4f34c
Kevin Lim [Thu, 16 Feb 2006 19:55:15 +0000 (14:55 -0500)]
Remove fake fault.
Switch fault pointers to const pointers to prevent them from accidentally being changed.
Fix some coding style.
arch/alpha/ev5.cc:
cpu/o3/commit_impl.hh:
kern/kernel_stats.hh:
Remove fake fault.
arch/alpha/faults.cc:
Remove fake fault, fix to have normal m5 line length limit, and change pointers to be const pointers so that the default faults aren't changed accidentally.
arch/alpha/faults.hh:
Fix to have normal m5 line length limit, change pointers to const pointers.
sim/faults.cc:
sim/faults.hh:
Remove fake fault, change pointers to const pointers.
--HG--
extra : convert_revision :
01d4600e0d4bdc1d177b32edebc78f86a1bbfe2e
Kevin Lim [Thu, 16 Feb 2006 17:03:44 +0000 (12:03 -0500)]
Merge ktlim@zizzer:/bk/m5
into zamp.eecs.umich.edu:/z/ktlim2/clean/m5-new
arch/alpha/isa/mem.isa:
Hand merge.
--HG--
extra : convert_revision :
c557aa4c867d84ab01139e509ee9f2ed05dd8ea0
Kevin Lim [Thu, 16 Feb 2006 16:55:28 +0000 (11:55 -0500)]
Fixes to handle generating the initiateAcc and completeAcc functions a little more cleanly.
arch/alpha/isa/mem.isa:
Avoid explicitly declaring the Mem variable. Instead break up the code blocks used to generate the initiate and complete functions. The templates reflect which operands need to be declared for each function (src, dest, or both).
Loads use both the EA code and mem acc code for the initiate, and memacc code and postacc code for the complete.
Stores use both the EA code and mem acc code for the initiate, and only post acc code for the complete.
arch/isa_parser.py:
Remove hack for mem ops.
--HG--
extra : convert_revision :
a367797a2cb698762bfc27be1da00bcbe9367150
Korey Sewell [Thu, 16 Feb 2006 07:51:04 +0000 (02:51 -0500)]
Get ISA parser to at least include all the ISA correctly ... crashes with "None" error
arch/mips/isa/decoder.isa:
CondBranch format split up into Branch & BranchLikely formats
arch/mips/isa/formats.isa:
include util.isa
arch/mips/isa/formats/branch.isa:
erroneous 'e' at top of code
arch/mips/isa/formats/util.isa:
util.isa
--HG--
extra : convert_revision :
4fc44a05e2838749e66cd70f210e8a718b34cbf3
Korey Sewell [Thu, 16 Feb 2006 07:40:04 +0000 (02:40 -0500)]
Merge zizzer:/bk/multiarch
into zazzer.eecs.umich.edu:/z/ksewell/research/m5-sim/m5-multiarch
--HG--
extra : convert_revision :
17b164847aee7e21d15d1a9d99aae43f46906c28
Korey Sewell [Thu, 16 Feb 2006 07:39:46 +0000 (02:39 -0500)]
file name changes ... minor ISA changes
arch/mips/isa/base.isa:
restoring base.isa file ...
arch/mips/isa/formats/basic.isa:
add c++ emacs header
arch/mips/isa/formats/branch.isa:
added branch likely format
arch/mips/isa/formats/int.isa:
small change to python code
--HG--
extra : convert_revision :
defd592abb1a724f5f88b19c197b858420e92d17
Gabe Black [Thu, 16 Feb 2006 07:08:13 +0000 (02:08 -0500)]
Some changes which weren't needed before doing a bk pull were needed afterwards, for some reason.
arch/alpha/ev5.cc:
Took out the unnecessary check for a null Fault pointer.
arch/alpha/isa/mem.isa:
Changed Fault to Fault *, and removed underscores from fault names.
--HG--
extra : convert_revision :
367a58a375f911185ddcc5fc826034af96427461
Gabe Black [Thu, 16 Feb 2006 06:25:48 +0000 (01:25 -0500)]
Merge gblack@m5.eecs.umich.edu:/bk/multiarch
into ewok.(none):/home/gblack/m5/multiarch
--HG--
extra : convert_revision :
d8626acb2686e123ad0bb6cf94e85c992657470d
Gabe Black [Thu, 16 Feb 2006 06:22:51 +0000 (01:22 -0500)]
Changed the fault enum into a class, and fixed everything up to work with it. Next, the faults need to be pulled out of all the other code so that they are only used to communicate between the CPU and the ISA.
SConscript:
The new faults.cc file in sim allocates the system wide faults. When these faults are generated through a function interface in the ISA, this file may go away.
arch/alpha/alpha_memory.cc:
Changed Fault to Fault * and took the underscores out of fault names.
arch/alpha/alpha_memory.hh:
Changed Fault to Fault *. Also, added an include for the alpha faults.
arch/alpha/ev5.cc:
Changed the fault_addr array into a fault_addr function. Once all of the faults can be expected to have the same type, fault_addr can go away completely and the info it provided will come from the fault itself. Also, Fault was changed to Fault *, and underscores were taken out of fault names.
arch/alpha/isa/decoder.isa:
Changed Fault to Fault * and took the underscores out fault names.
arch/alpha/isa/fp.isa:
Changed Fault to Fault *, and took the underscores out of fault names.
arch/alpha/isa/main.isa:
Changed Fault to Fault *, removed underscores from fault names, and made an include of the alpha faults show up in all the generated files.
arch/alpha/isa/mem.isa:
Changed Fault to Fault * and removed underscores from fault names.
arch/alpha/isa/unimp.isa:
arch/alpha/isa/unknown.isa:
cpu/exec_context.hh:
cpu/ozone/cpu.hh:
cpu/simple/cpu.cc:
dev/alpha_console.cc:
dev/ide_ctrl.cc:
dev/isa_fake.cc:
dev/pciconfigall.cc:
dev/pcidev.cc:
dev/pcidev.hh:
dev/tsunami_cchip.cc:
dev/tsunami_io.cc:
dev/tsunami_pchip.cc:
Changed Fault to Fault *, and removed underscores from fault names.
arch/alpha/isa_traits.hh:
Changed the include of arch/alpha/faults.hh to sim/faults.hh, since the alpha faults weren't needed.
cpu/base_dyn_inst.cc:
Changed Fault to Fault *, and removed underscores from fault names. This file probably shouldn't use the Unimplemented Opcode fault.
cpu/base_dyn_inst.hh:
Changed Fault to Fault * and took the underscores out of the fault names.
cpu/exec_context.cc:
cpu/o3/alpha_dyn_inst.hh:
cpu/o3/alpha_dyn_inst_impl.hh:
cpu/o3/fetch.hh:
dev/alpha_console.hh:
dev/baddev.hh:
dev/ide_ctrl.hh:
dev/isa_fake.hh:
dev/ns_gige.hh:
dev/pciconfigall.hh:
dev/sinic.hh:
dev/tsunami_cchip.hh:
dev/tsunami_io.hh:
dev/tsunami_pchip.hh:
dev/uart.hh:
dev/uart8250.hh:
Changed Fault to Fault *.
cpu/o3/alpha_cpu.hh:
Changed Fault to Fault *, removed underscores from fault names.
cpu/o3/alpha_cpu_impl.hh:
Changed Fault to Fault *, removed underscores from fault names, and changed the fault_addr array to the fault_addr function. Once all faults are from the ISA, this function will probably go away.
cpu/o3/commit_impl.hh:
cpu/o3/fetch_impl.hh:
dev/baddev.cc:
Changed Fault to Fault *, and removed underscores from the fault names.
cpu/o3/regfile.hh:
Added an include for the alpha specific faults which will hopefully go away once the ipr stuff is moved, changed Fault to Fault *, and removed the underscores from fault names.
cpu/simple/cpu.hh:
Changed Fault to Fault *
dev/ns_gige.cc:
Changed Fault to Fault *, and removdd underscores from fault names.
dev/sinic.cc:
Changed Fault to Fault *, and removed the underscores from fault names.
dev/uart8250.cc:
Chanted Fault to Fault *, and removed underscores from fault names.
kern/kernel_stats.cc:
Removed underscores from fault names, and from NumFaults.
kern/kernel_stats.hh:
Changed the predeclaration of Fault from an enum to a class, and changd the "fault" function to work with the classes instead of the enum. Once there are no system wide faults anymore, this code will simplify back to something like it was originally.
sim/faults.cc:
This allocates the system wide faults.
sim/faults.hh:
This declares the system wide faults.
sim/syscall_emul.cc:
sim/syscall_emul.hh:
Removed the underscores from fault names.
--HG--
rename : arch/alpha/faults.cc => sim/faults.cc
rename : arch/alpha/faults.hh => sim/faults.hh
extra : convert_revision :
253d39258237333ae8ec4d8047367cb3ea68569d
Gabe Black [Thu, 16 Feb 2006 04:24:35 +0000 (23:24 -0500)]
Merge zizzer.eecs.umich.edu:/z/m5/Bitkeeper/m5
into zizzer.eecs.umich.edu:/z/m5/Bitkeeper/multiarch
--HG--
extra : convert_revision :
b4bbf63ec3b1c6de0ea7220e6dda5366c0529c07
Korey Sewell [Wed, 15 Feb 2006 19:08:54 +0000 (14:08 -0500)]
...
arch/mips/isa/base.isa:
restore base.isa
--HG--
extra : convert_revision :
a551caae28f505b22bceae3297fc00b0fb6a0e23
Kevin Lim [Wed, 15 Feb 2006 18:05:21 +0000 (13:05 -0500)]
Gives separate methods for initiating and completing a memory access, which will be helpful for the merged memory model.
arch/alpha/isa/mem.isa:
Include methods that allow a memory operation to be split between the part that initiates the access, and the part that completes the access. In these functions the Mem variable is explicitly declared; in the default execute functions, the Mem variable is still handled through %(op_decl)s.
arch/isa_parser.py:
Include recording the type of the memory access variable so that it can be used if it needs to be explicitly declared in a template.
Have memory operands consider themselves neither a source nor a destination to avoid including themselves on the op_src_decl list or the op_dest_decl list.
Record op_src_decl and op_dest_decl lists to allow for declaring only source or destination operands. This is needed for the split memory access methods.
--HG--
extra : convert_revision :
f674f7a2f747ae40ba8c3a0933b0337c87ee0b6c
Ali Saidi [Wed, 15 Feb 2006 06:27:06 +0000 (01:27 -0500)]
Merge zizzer:/bk/m5
into pb15.local:/Users/ali/work/m5.head
sim/byteswap.hh:
SCCS merged
--HG--
extra : convert_revision :
65989fef265ddfafb59a6c96e3cdde76eb3e071d
Ali Saidi [Wed, 15 Feb 2006 06:23:13 +0000 (01:23 -0500)]
endian fixes and compiles on mac os x
arch/alpha/alpha_linux_process.cc:
add endian conversions for fstat functions
arch/alpha/alpha_tru64_process.cc:
add endian conversions for various functions
sim/byteswap.hh:
for some reason gcc on macos really wants long and unsigned long
Why int32_t and uint32_t isn't sufficient I don't know.
sim/process.cc:
sim/syscall_emul.hh:
endian fixes
--HG--
extra : convert_revision :
ce625d5660b70867c43c74fbed856149c0d8cd36
Korey Sewell [Wed, 15 Feb 2006 03:43:26 +0000 (22:43 -0500)]
Merge zizzer:/bk/multiarch
into zazzer.eecs.umich.edu:/z/ksewell/research/m5-sim/m5-multiarch
--HG--
extra : convert_revision :
5b0a3dd1a52ca9b29ea4a1c505a7435bfd6110fe
Korey Sewell [Wed, 15 Feb 2006 03:43:14 +0000 (22:43 -0500)]
another big step to a parsable ISA ... no errors after I used a symbolic link for
arch/alpha/main.isa to test my files ...
arch/mips/isa/operands.isa:
use sd and ud instead of sdw and udw
--HG--
extra : convert_revision :
d66f3fd2c4a4d70e6015f0f1643c400cdfe73055
Korey Sewell [Wed, 15 Feb 2006 02:26:01 +0000 (21:26 -0500)]
trying to get ISA to parse correctly ...
arch/mips/isa/formats/unimp.isa:
holds unimplemented formats
arch/mips/isa/formats/unknown.isa:
holds unknown formats
--HG--
extra : convert_revision :
0f3a8ea7e3a1592322cce54527d6989152e57975
Gabe Black [Wed, 15 Feb 2006 01:13:08 +0000 (20:13 -0500)]
New files to fix building the SPARC_SE and MIPS_SE isa_parser.py generated files.
--HG--
extra : convert_revision :
94a9543376f8b4709a4aef54c5ac0d6f582a9dad
Gabe Black [Tue, 14 Feb 2006 08:57:42 +0000 (03:57 -0500)]
Fixed a path in the alpha isa description.
--HG--
extra : convert_revision :
2a73ef7703ffe5c5232619698a16c8b4ee265a21
Korey Sewell [Tue, 14 Feb 2006 07:12:39 +0000 (02:12 -0500)]
Merge zizzer:/bk/multiarch
into zazzer.eecs.umich.edu:/z/ksewell/research/m5-sim/m5-multiarch
--HG--
extra : convert_revision :
62d9346c44d5b7d455414fbebf0da3a8ef8d0754
Korey Sewell [Tue, 14 Feb 2006 07:03:14 +0000 (02:03 -0500)]
make MIPS MT instructions decodable ...
arch/mips/isa/bitfields.isa:
extra bitfield for decoding
--HG--
extra : convert_revision :
27f0afc3ee6ce00a94f44b2b1ac160ec26030866
Gabe Black [Sun, 12 Feb 2006 22:38:10 +0000 (17:38 -0500)]
Pseudo instructions are now passed whatever instructions they need by the decoder, rather than extracting them explicitly. This lets most of the pseudo instruction code to be shared across architectures.
SConscript:
Moved pseudo_inst.hh from targetarch to full system sources
arch/alpha/SConscript:
Moved pseudo_inst.cc out of the alpha specific sources
arch/alpha/isa/decoder.isa:
The decoder now pulls out the arguments for the pseudo instructions based on the alpha ABI
arch/alpha/isa/main.isa:
Registers 16, 17 and 18 are used to get parameters for the pseudo instructions and can be referred to explicitly
sim/pseudo_inst.cc:
Changed some include paths to reflect that pseudo_inst.hh is now outside of the alpha directory. Also, instead of extracting their parameters directly, they're passed in as regular function arguments.
sim/pseudo_inst.hh:
Changed the function prototypes to include the functions parameters, now that they aren't extracted from the execution context.
--HG--
rename : arch/alpha/pseudo_inst.cc => sim/pseudo_inst.cc
rename : arch/alpha/pseudo_inst.hh => sim/pseudo_inst.hh
extra : convert_revision :
76ce768cf1d8a838aa7b64878a7ab4c4215ac999
Gabe Black [Sun, 12 Feb 2006 17:40:58 +0000 (12:40 -0500)]
Removed isa_traits.hh from targetarch, moved vptr.hh from arch/alpha to sim, fixed an include to have the new location, and removed an ambiguating function declaration in byteswap.hh.
SConscript:
Moved isa_fullsys_traits.hh out of targetarch, since the only place it's included, and the only place the comments in the file say it should be included, is in the alpha isa_traits.hh
targetarch/isa_traits.hh is now included through arch/isa_traits.hh
vptr.hh was removed from targetarch, and moved to sim
arch/alpha/pseudo_inst.cc:
Moved vptr.hh from targetarch to sim
base/loader/object_file.hh:
base/loader/symtab.hh:
cpu/base.hh:
dev/ide_disk.cc:
Changed the include of isa_traits.hh from targetarch to arch
cpu/static_inst.hh:
dev/platform.hh:
dev/simple_disk.hh:
kern/tru64/dump_mbuf.cc:
kern/tru64/mbuf.hh:
kern/tru64/tru64_events.cc:
kern/tru64/tru64_system.cc:
kern/tru64/tru64_system.hh:
sim/process.hh:
sim/syscall_emul.hh:
Changed the include of isa_traits.hh from targetarch to arch.
kern/linux/linux_threadinfo.hh:
Changed the include of vptr.hh from targetarch to sim.
sim/byteswap.hh:
Removed the line declaring swap_byte(long), since it ambiguates with swap_byte(int32_t)
sim/vptr.hh:
Fixed the assert in the equals operator.
Changed the AlphaISA namespace reference to TheISA.
Changed arch/alpha/vtophys.hh to targetarch/vtophys.hh, since this file is now for all architectures.
Added an include of arch/isa_traits.hh so that TheISA would be defined.
--HG--
extra : convert_revision :
e3c6ac17ed0277cfeba1d35cd63eba66eba5996f
Gabe Black [Sun, 12 Feb 2006 17:17:51 +0000 (12:17 -0500)]
Merge gblack@m5.eecs.umich.edu:/bk/multiarch
into ewok.(none):/home/gblack/m5/multiarch
--HG--
extra : convert_revision :
baf9b0eb84df7da8152ddf9a25264e041a24b8ca
Gabe Black [Sun, 12 Feb 2006 17:14:14 +0000 (12:14 -0500)]
vptr.hh:
Rename: arch/alpha/vptr.hh -> sim/vptr.hh
--HG--
rename : arch/alpha/vptr.hh => sim/vptr.hh
extra : convert_revision :
345745efec49f6169d1d9f61fd590240a995373b
Gabe Black [Sun, 12 Feb 2006 16:38:26 +0000 (11:38 -0500)]
Merge zizzer.eecs.umich.edu:/z/m5/Bitkeeper/m5
into zizzer.eecs.umich.edu:/z/m5/Bitkeeper/multiarch
--HG--
extra : convert_revision :
427b5c957f91e66271444acebc01e1a861790363
Steve Reinhardt [Sun, 12 Feb 2006 05:31:19 +0000 (00:31 -0500)]
Polishing of isa_parser.py internal operand handling, resulting in
minor change to syntax of 'def operands' in ISA descriptions.
arch/alpha/isa/main.isa:
arch/mips/isa/operands.isa:
arch/sparc/isa/operands.isa:
Change 'def operands' statement to work with new
isa_parser changes.
arch/isa_parser.py:
Merge OperandTraits and OperandDescriptor objects into a
unified hierarchy of Operand objects.
Required a change in the syntax of the 'def operands'
statement in the ISA description.
--HG--
extra : convert_revision :
cb43f1607311497ead88ba13953d410ab5bc6a37
Steve Reinhardt [Sun, 12 Feb 2006 02:26:49 +0000 (21:26 -0500)]
Minor cleanup of operand type and traits code in isa_parser.py.
arch/isa_parser.py:
Minor cleanup of operand type and traits code:
- build operand size map right away when types are defined
instead of waiting to do it lazily
- check that operand types have been defined before operands
- don't use 'type' as a variable name
- use isinstance() instead of checking for types directly
--HG--
extra : convert_revision :
099c1ee8d490f9c38316749bf87209388c55c971
Steve Reinhardt [Sat, 11 Feb 2006 20:11:00 +0000 (15:11 -0500)]
Add keyword parameters and list-valued arguments to
instruction format functions in ISA description language.
Take advantage of these features to clean up memory
instruction definitions in Alpha.
arch/alpha/isa/decoder.isa:
arch/alpha/isa/mem.isa:
arch/alpha/isa/pal.isa:
Take advantage of new keyword parameters to disambiguate
instruction vs. memory-request flags, and to provide
a default EA calculation for memory ops (since 99% of them
are the same).
arch/isa_parser.py:
Add two new features to instruction format functions:
- Keyword parameters, a la Python.
- List-valued arguments.
Also export makeList() function to Python code blocks,
as this is handy for dealing with flags.
--HG--
extra : convert_revision :
99bbbaa2e765230aa96b6a06ed193793325f9fb0
Ali Saidi [Sat, 11 Feb 2006 16:01:51 +0000 (11:01 -0500)]
fix #if. I wonder why my compiler had no issues. Even though it is clearly
wrong
arch/alpha/alpha_linux_process.cc:
fix #if. I wonder why my compiler had no issues
--HG--
extra : convert_revision :
880a0442b28811db5ec548ce940060d4b26ec634
Ali Saidi [Sat, 11 Feb 2006 05:55:36 +0000 (00:55 -0500)]
hello world works on a BE host for a LE guest
arch/alpha/alpha_linux_process.cc:
Add endian conversions to fstat
sim/byteswap.hh:
for some reason I don't understand g++ really wanted a long version defined
even though int32_t should be the same.
--HG--
extra : convert_revision :
5bfe9d3f0b31824fa5a7ae3f51fd0be5ed4d555d
Ali Saidi [Sat, 11 Feb 2006 01:06:44 +0000 (20:06 -0500)]
Merge zizzer:/bk/m5
into pb15.local:/Users/ali/work/m5.head
--HG--
extra : convert_revision :
b8631bcea38e3a75e4442927500ddfc7763ba9cf
Gabe Black [Fri, 10 Feb 2006 22:35:26 +0000 (17:35 -0500)]
Merge zizzer.eecs.umich.edu:/z/m5/Bitkeeper/m5
into zizzer.eecs.umich.edu:/z/m5/Bitkeeper/multiarch
--HG--
extra : convert_revision :
219377d0e4b70c30c17644991f39282b4aef14f8
Ali Saidi [Fri, 10 Feb 2006 19:59:37 +0000 (14:59 -0500)]
confused an ifdef with an if
--HG--
extra : convert_revision :
5b8e8bdff5813cf8846e66de2652246d77c97e88
Ali Saidi [Fri, 10 Feb 2006 19:38:15 +0000 (14:38 -0500)]
Merge zizzer:/bk/m5
into udhcp-macvpn-776.public.engin.umich.edu:/Users/ali/work/m5.head
--HG--
extra : convert_revision :
e9ffaa1d4b7eee1f5bd0c492e162aac1e0806099
Ali Saidi [Fri, 10 Feb 2006 19:21:32 +0000 (14:21 -0500)]
fix problems on darwin/*BSD for syscall emulation mode
arch/alpha/alpha_linux_process.cc:
arch/alpha/alpha_tru64_process.cc:
fixup for bsd hosts. Some headers are included by default which means that
more variables need TGT_ prefixes and there isn't a stat call (everything
is a stat64 call) so we have to work around that a bit
base/intmath.hh:
base/socket.cc:
this is no longer needed with mac os 10.4
cpu/inst_seq.hh:
just use a uint64_t instead of long long
cpu/o3/inst_queue_impl.hh:
I much cleaner way to get max int
sim/syscall_emul.hh:
fix stat64 problems on *BSD
--HG--
extra : convert_revision :
9eef5f896e083ae1774e818a9765dd83e0305942
Steve Reinhardt [Fri, 10 Feb 2006 14:12:55 +0000 (09:12 -0500)]
Change how memory operands are handled in ISA descriptions.
Should enable implementation of split-phase timing loads
with new memory model.
May create slight timing differences under FullCPU, as I
believe we were not handling software prefetches correctly
before when the split MemAcc/Exec model was used. I haven't
looked into this in any detail though.
arch/alpha/isa/decoder.isa:
HwLoadStore format split into separate HwLoad and
HwStore formats.
Copy instructions now fall under MiscPrefetch format.
Mem_write_result is now just write_result in store
conditionals.
arch/alpha/isa/mem.isa:
Split MemAccExecute and LoadStoreExecute templates
into separate templates for loads and stores; now
that memory operands are handled differently from
registers, it's impossible to have a single template
serve both.
Also unified the handling of "regular" prefetches
(loads to r31) and "misc" prefetches (e.g., wh64)
under the new scheme. It looks like SW prefetches
were not handled correctly in FullCPU up til now,
since we generated an execute() method for the outer
instruction but didn't generate a proper method for
MemAcc::execute() (instead getting a default no-op
method for that).
arch/alpha/isa/pal.isa:
Split HwLoadStore into separate HwLoad and HwStore
formats to select proper template (see change to
mem.isa in this changeset).
arch/isa_parser.py:
Stop trying to treat memory operands like register
operands, since we never used them in a uniform way
anyway, and it made it impossible to do split-phase
loads as needed for the new CPU model. Now there's no
more 'op_mem_rd', 'op_nonmem_rd', etc.: 'op_rd' just does
register operands, and the template code is responsible
for formulating the call to the memory system. Right now
the only thing exported by InstObjParams is a new attribute
'mem_acc_size' which gives the memory access size in bits,
though more attributes can be added if needed.
Also moved code in findOperands() method to
OperandDescriptorList.__init__(), which is where it belongs.
--HG--
extra : convert_revision :
6d53d07e0c5e828455834ded4395fa40f9146a34
Korey Sewell [Fri, 10 Feb 2006 08:31:13 +0000 (03:31 -0500)]
Merge zizzer:/bk/multiarch
into zazzer.eecs.umich.edu:/z/ksewell/research/m5-sim/m5-multiarch
--HG--
extra : convert_revision :
c78773ba1acb2c6a45f0e92d80fdfc7f23ea6973
Korey Sewell [Fri, 10 Feb 2006 08:27:19 +0000 (03:27 -0500)]
The first fully coded version of decoder.isa!!!!!
=================================================
-every MIPS32 ISA is represented with some type
of code block.
-any instruction that doesnt have a code block
would be of format WarnUnimpl. Examples of the
ones I am waiting on further info to implement
are the TLB register insts, memory consistency
instructions (ll,sc,etc.) and software debug
insts.
--HG--
extra : convert_revision :
4a26c72e4fa1f63b8689fe2631a7508daf660969
Steve Reinhardt [Fri, 10 Feb 2006 04:02:38 +0000 (23:02 -0500)]
Split Alpha ISA description into multiple files
(thanks to Gabe's include feature!).
arch/alpha/isa/main.isa:
Split out into multiple .isa files.
--HG--
extra : convert_revision :
30d8edf74ea194d4a208febf1e66edc72a7dbd5d
Steve Reinhardt [Fri, 10 Feb 2006 03:27:41 +0000 (22:27 -0500)]
Minor cleanup of include-handling code in isa_parser.py.
arch/isa_parser.py:
Clean up ##include code a bit.
arch/sparc/isa/formats.isa:
arch/sparc/isa/main.isa:
Fix include paths.
--HG--
extra : convert_revision :
0689963c2948e5f1088ecbf2cf6018d29bdaceff
Steve Reinhardt [Thu, 9 Feb 2006 19:58:56 +0000 (14:58 -0500)]
Merge zizzer.eecs.umich.edu:/z/m5/Bitkeeper/m5
into zizzer.eecs.umich.edu:/z/stever/bk/m5
--HG--
extra : convert_revision :
6e30fb802265c6a0d4afc00141b89ee529595549
Steve Reinhardt [Thu, 9 Feb 2006 19:51:56 +0000 (14:51 -0500)]
Merge zizzer.eecs.umich.edu:/z/m5/Bitkeeper/m5
into zizzer.eecs.umich.edu:/z/stever/bk/m5
--HG--
extra : convert_revision :
10146c85d2fa6f565568cc30a4564b3674e4768d
Steve Reinhardt [Thu, 9 Feb 2006 19:51:37 +0000 (14:51 -0500)]
Change how isa_parser.py generates C++ names for isa_desc operands.
arch/isa_parser.py:
Get rid of "munged name" for operands in C++ code.
That is, "Ra.uq" will now be known in the C++ as "Ra"
rather than "Ra_uq". It wasn't legal to use different
type extensions for the same operand at the same time
anyway, and now it will be easier to refer to explicit
operands in template code if necessary.
--HG--
extra : convert_revision :
9ff41e0201aeefe761743084ecdb34f4b9c84fdb
Gabe Black [Thu, 9 Feb 2006 19:48:10 +0000 (14:48 -0500)]
Merge gblack@m5.eecs.umich.edu:/bk/multiarch
into ewok.(none):/home/gblack/m5/multiarch
--HG--
extra : convert_revision :
ae574fbee484019d318ef25034bd4a7e18354aab
Gabe Black [Thu, 9 Feb 2006 19:37:44 +0000 (14:37 -0500)]
Merge zizzer.eecs.umich.edu:/z/m5/Bitkeeper/m5
into zizzer.eecs.umich.edu:/z/m5/Bitkeeper/multiarch
--HG--
extra : convert_revision :
6b218e875e5c6299cd38727071e401a3e729266a
Gabe Black [Thu, 9 Feb 2006 18:56:24 +0000 (13:56 -0500)]
Changed the filenames to the new standard again
arch/sparc/isa/formats.isa:
Changed the file extensions to .isa again.
arch/sparc/isa/main.isa:
Changed the file extensions to .isa again
--HG--
rename : arch/sparc/isa_desc/base.h => arch/sparc/isa/base.isa
rename : arch/sparc/isa_desc/bitfields.h => arch/sparc/isa/bitfields.isa
rename : arch/sparc/isa_desc/decoder.h => arch/sparc/isa/decoder.isa
rename : arch/sparc/isa_desc/formats.h => arch/sparc/isa/formats.isa
rename : arch/sparc/isa_desc/formats/basic.format => arch/sparc/isa/formats/basic.isa
rename : arch/sparc/isa_desc/formats/branch.format => arch/sparc/isa/formats/branch.isa
rename : arch/sparc/isa_desc/formats/integerop.format => arch/sparc/isa/formats/integerop.isa
rename : arch/sparc/isa_desc/formats/mem.format => arch/sparc/isa/formats/mem.isa
rename : arch/sparc/isa_desc/formats/noop.format => arch/sparc/isa/formats/noop.isa
rename : arch/sparc/isa_desc/formats/trap.format => arch/sparc/isa/formats/trap.isa
rename : arch/sparc/isa_desc/includes.h => arch/sparc/isa/includes.isa
rename : arch/sparc/isa_desc/isa_desc => arch/sparc/isa/main.isa
rename : arch/sparc/isa_desc/operands.h => arch/sparc/isa/operands.isa
extra : convert_revision :
acb087e81d06ca5d67fe9b402423d7930f6ae798
Gabe Black [Thu, 9 Feb 2006 18:07:00 +0000 (13:07 -0500)]
Merge gblack@m5.eecs.umich.edu:/bk/multiarch
into ewok.(none):/home/gblack/m5/multiarch
--HG--
extra : convert_revision :
41a0e8c0b2d328bee958126f395369d4549aabfc
Gabe Black [Thu, 9 Feb 2006 18:06:47 +0000 (13:06 -0500)]
A fix for SConscript so it will work with newer versions of scons
SConscript:
Changed the ISAPath function to take 5 arguments to work with scons 0.97.
--HG--
extra : convert_revision :
34fbe131aec9349631b5026d839563380623f3fd
Korey Sewell [Thu, 9 Feb 2006 09:26:04 +0000 (04:26 -0500)]
more code for instructions... Mainly for coprocessor0 and coprocessor1 move instructions
--HG--
extra : convert_revision :
34e017fd0a6f330f2ac17d34af216fc14f09dd42
Korey Sewell [Wed, 8 Feb 2006 21:24:25 +0000 (16:24 -0500)]
Merge zizzer:/bk/multiarch
into zazzer.eecs.umich.edu:/z/ksewell/research/m5-sim/m5-multiarch
--HG--
extra : convert_revision :
2bfc19cfa186776ff94440b01ea51f520f61234f
Korey Sewell [Wed, 8 Feb 2006 21:24:04 +0000 (16:24 -0500)]
Code for more "BasicOp" instructions ... formats for all instructions in place ... Edits to Branch Format
arch/mips/isa/decoder.isa:
Code for di,ei,seb,seh,clz,and clo ....
Every instruction has a format now (of course these are initial formats are still subject to change!)
arch/mips/isa/formats/branch.isa:
Format Branch in MIPS similar to Alpha Format
--HG--
extra : convert_revision :
2118a1d9668610b1e9f1dea66d878b7b36c1ac7e
Korey Sewell [Wed, 8 Feb 2006 19:50:07 +0000 (14:50 -0500)]
add at least BasicOp Format to most if not all instructions
and file name changes ...
arch/mips/isa/decoder.isa:
add at least BasicOp Format to most if not all instructions
--HG--
rename : arch/mips/isa/formats/basic.format => arch/mips/isa/formats/basic.isa
rename : arch/mips/isa/formats/branch.format => arch/mips/isa/formats/branch.isa
rename : arch/mips/isa/formats/fp.format => arch/mips/isa/formats/fp.isa
rename : arch/mips/isa/formats/int.format => arch/mips/isa/formats/int.isa
rename : arch/mips/isa/formats/mem.format => arch/mips/isa/formats/mem.isa
rename : arch/mips/isa/formats/noop.format => arch/mips/isa/formats/noop.isa
rename : arch/mips/isa/formats/tlbop.format => arch/mips/isa/formats/tlbop.isa
rename : arch/mips/isa/formats/trap.format => arch/mips/isa/formats/trap.isa
rename : arch/mips/isa/mips.isa => arch/mips/isa/main.isa
extra : convert_revision :
0b2f3aee13fee3e0e25c0c746af4216c4a596391
Steve Reinhardt [Wed, 8 Feb 2006 15:40:43 +0000 (10:40 -0500)]
Replace ad-hoc or locally defined power-of-2 tests
with isPowerOf2() from intmath.hh.
base/sched_list.hh:
Use isPowerOf2() from intmath.hh.
--HG--
extra : convert_revision :
7b2409531d8ed194aa7e1cfcd1ecb8460c797a16
Gabe Black [Wed, 8 Feb 2006 07:17:47 +0000 (02:17 -0500)]
Moved the alpha isa_desc to conform to the new naming system.
--HG--
rename : arch/alpha/isa_desc => arch/alpha/isa/main.isa
extra : convert_revision :
a3cc14c202ae606db270c2c29847170d90c05216
Gabe Black [Wed, 8 Feb 2006 06:57:47 +0000 (01:57 -0500)]
Some fixups
arch/alpha/alpha_linux_process.cc:
arch/alpha/alpha_tru64_process.cc:
Replaced the namespace declaration with including arch/alpha/isa_traits.hh
--HG--
extra : convert_revision :
07cb73a9f30f0e165809668f9baff6a3e3f94580
Gabe Black [Wed, 8 Feb 2006 06:04:32 +0000 (01:04 -0500)]
Merge gblack@m5.eecs.umich.edu:/bk/multiarch
into ewok.(none):/home/gblack/m5/multiarch
--HG--
extra : convert_revision :
c7caf571575fb0e7136770864371300d3f11787e
Gabe Black [Wed, 8 Feb 2006 06:03:55 +0000 (01:03 -0500)]
Alot of changes to push towards ISA independence. Highlights are renaming of the isa_desc files, movement of byte_swap.hh into sim, and the creation of arch/isa_traits.hh
SConscript:
Moved some files out of targetarch. The either no longer need to be there, never needed to be there, or should be referred to directly in arch/alpha due to there strictly alpha content.
arch/alpha/isa_traits.hh:
Added alpha's endianness to it's isa_traits.hh
arch/mips/isa_traits.hh:
Added MIPS endianness to it's isa_traits.hh
arch/sparc/isa_traits.hh:
Added SPARCs endianess to it's isa_traits.hh
build/SConstruct:
Added MIPS as a valid architecture
cpu/exec_context.hh:
Included arch/isa_traits.hh to bring in the endianness of the system.
cpu/o3/alpha_cpu.hh:
Included arch/isa_traits.hh to bring in the systems endianness, and removed the hardcoding of little endianness
cpu/o3/fetch_impl.hh:
kern/freebsd/freebsd_system.cc:
Included arch/isa_traits.hh to bring in the systems endianness, and removed the hardcoding to little endianness.
sim/system.cc:
Included arch/isa_traits.hh to bring in the systems endianness, and removed the hardcoding to little endian.
--HG--
extra : convert_revision :
b1ab34b7569db531cd1c74f273b24222e63f9007
Korey Sewell [Wed, 8 Feb 2006 00:28:19 +0000 (19:28 -0500)]
Actually we do need a separate class for Integer Ops with Immediates!!!
The extra class is needed because of the necessisty of an immediate member variable.
Also, added some 'very modest' python code to choose between the IntOp and
the IntImmOp based on the instruction name ...
--HG--
extra : convert_revision :
f109c12418202a99b40e270360134e8335739836
Korey Sewell [Tue, 7 Feb 2006 23:36:08 +0000 (18:36 -0500)]
name changes ... minor IntOP format change
arch/mips/isa/formats/int.format:
Looks like Integer Ops with Immediates may not need their own separate class because all those instructions are distinct from
their reg-reg counterparts
--HG--
rename : arch/mips/isa/bitfields.def => arch/mips/isa/bitfields.isa
rename : arch/mips/isa/decoder.def => arch/mips/isa/decoder.isa
rename : arch/mips/isa/formats.def => arch/mips/isa/formats.isa
rename : arch/mips/isa/includes.h => arch/mips/isa/includes.isa
rename : arch/mips/isa/operands.def => arch/mips/isa/operands.isa
extra : convert_revision :
8e354b4232b28c0264d98d333d55ef8b5a6589cc
Korey Sewell [Sat, 4 Feb 2006 23:59:44 +0000 (18:59 -0500)]
1st full draft switch statement actions for all integer arithmetic operations and the majority of the load & store operations (not all of FP-Ops),
Output,Format, & Template code needs to be adjusted to correctly take these "decoder.h" inputs ...
--HG--
extra : convert_revision :
3dcde1f2f587e2766fd61231a93d34d1d7727356
Korey Sewell [Sat, 4 Feb 2006 04:04:06 +0000 (23:04 -0500)]
mainly added minor support for the basic arithmetic operations (add, mult, shift)
arch/mips/isa/bitfields.def:
Add comment, move definition up in file
arch/mips/isa/decoder.def:
add basic arithmetic operations
arch/mips/isa/formats/fp.format:
change Integer -> FP words
arch/mips/isa/formats/int.format:
Add derived IntImm class
arch/mips/isa/operands.def:
change to MIPS sytle operands
--HG--
rename : arch/mips/isa/formats/fpop.format => arch/mips/isa/formats/fp.format
rename : arch/mips/isa/formats/integerop.format => arch/mips/isa/formats/int.format
extra : convert_revision :
a95da47bc981e56a9898421da4eeb9c442d1dc15
Korey Sewell [Fri, 3 Feb 2006 08:56:57 +0000 (03:56 -0500)]
.h -> .def
--HG--
rename : arch/mips/isa/bitfields.h => arch/mips/isa/bitfields.def
rename : arch/mips/isa/decoder.h => arch/mips/isa/decoder.def
rename : arch/mips/isa/formats.h => arch/mips/isa/formats.def
rename : arch/mips/isa/operands.h => arch/mips/isa/operands.def
extra : convert_revision :
45cb5485311d51982ebcaf1c7eec34e8751c31f5
Korey Sewell [Fri, 3 Feb 2006 08:39:08 +0000 (03:39 -0500)]
Rename: arch/mips/isa/formats/tlb.format -> arch/mips/isa/formats/tlbop.format
--HG--
rename : arch/mips/isa/formats/tlb.format => arch/mips/isa/formats/tlbop.format
extra : convert_revision :
5b1cfba4a5b687c9a271e1a3f67f75e3fa6c2dde
Korey Sewell [Fri, 3 Feb 2006 08:38:27 +0000 (03:38 -0500)]
Checkin (Merge?) files ... Added a few new format files
arch/mips/isa/formats/fpop.format:
Floating Point Formats
arch/mips/isa/formats/tlb.format:
TLB Ops Format
arch/mips/isa/mips.isa:
Name change to mips.isa
--HG--
rename : arch/mips/isa_desc/bitfields.h => arch/mips/isa/bitfields.h
rename : arch/mips/isa_desc/decoder.h => arch/mips/isa/decoder.h
rename : arch/mips/isa_desc/formats.h => arch/mips/isa/formats.h
rename : arch/mips/isa_desc/formats/basic.format => arch/mips/isa/formats/basic.format
rename : arch/mips/isa_desc/formats/branch.format => arch/mips/isa/formats/branch.format
rename : arch/mips/isa_desc/formats/integerop.format => arch/mips/isa/formats/integerop.format
rename : arch/mips/isa_desc/formats/mem.format => arch/mips/isa/formats/mem.format
rename : arch/mips/isa_desc/formats/noop.format => arch/mips/isa/formats/noop.format
rename : arch/mips/isa_desc/formats/trap.format => arch/mips/isa/formats/trap.format
rename : arch/mips/isa_desc/includes.h => arch/mips/isa/includes.h
rename : arch/mips/isa_desc/operands.h => arch/mips/isa/operands.h
extra : convert_revision :
069a24da405b613f688e693fd038ac7a30a4faed
Gabe Black [Fri, 3 Feb 2006 05:16:44 +0000 (00:16 -0500)]
byte_swap.hh was removed from arch/alpha/, and replaced by sim/byteswap.hh. The new file uses LittleEndianGuest and BigEndianGuest namespaces to allow selecting the appropriate functions.
arch/alpha/alpha_linux_process.cc:
arch/alpha/alpha_tru64_process.cc:
Added the endianness namespace. This may change.
cpu/exec_context.hh:
Changed the include path for byteswap, and forced LittleEndianness for lack of a better solution.
cpu/o3/alpha_cpu.hh:
Forced LittleEndianness, for lack of a better solution.
cpu/o3/alpha_cpu_impl.hh:
Cleared away some commented out code.
cpu/o3/fetch_impl.hh:
Changed the include patch for byteswap, and forced LittleEndianness for lack of a better solution.
cpu/simple/cpu.cc:
Added an include for byteswap.hh, and fixed the SimpleCPU to LittleEndian. This cpu only does alpha, so that's fine.
dev/disk_image.cc:
Changed the include path of byteswap.hh
kern/freebsd/freebsd_system.cc:
kern/linux/linux_system.cc:
Added an include for byteswap.hh, and forced LittleEndianness for lack of a better solution.
sim/system.cc:
Forced LittleEndianness for lack of a better solution.
--HG--
extra : convert_revision :
b95d3e1265a825e04bd77622a3ac09fbac6bd206
Ali Saidi [Wed, 1 Feb 2006 22:52:40 +0000 (17:52 -0500)]
Merge zizzer:/bk/multiarch
into zeep.eecs.umich.edu:/z/saidi/work/m5.multiarch
--HG--
extra : convert_revision :
88b5214973ecc2f5c0428da21b65b09c767ae31d
Gabe Black [Wed, 1 Feb 2006 22:41:03 +0000 (17:41 -0500)]
Merge zizzer.eecs.umich.edu:/z/m5/Bitkeeper/m5
into zizzer.eecs.umich.edu:/z/m5/Bitkeeper/multiarch
--HG--
extra : convert_revision :
f2339d64cc63709e32c06892f4eabb40a806095e
Ali Saidi [Wed, 1 Feb 2006 18:13:05 +0000 (13:13 -0500)]
Fix a mistake, need to import SCons.Scanner
--HG--
extra : convert_revision :
c6b15c162e9826c6c00dbbf52fb8aa8819d56c23
Ali Saidi [Tue, 31 Jan 2006 18:52:23 +0000 (13:52 -0500)]
Add a scaner for .isa files. Ordering it turns out is rather important
here, so it has to be defined before the rule to that calls
isa_parser.py
--HG--
extra : convert_revision :
dbba3c7ee71ca8ca1fcbf5ee65ae83b4ecb63649