Florent Kermarrec [Mon, 10 Feb 2020 17:00:46 +0000 (18:00 +0100)]
tools: add litex_sim_new based on SoCCore and using add_sdram method
Florent Kermarrec [Mon, 10 Feb 2020 16:43:29 +0000 (17:43 +0100)]
soc_core: use add_rom
Florent Kermarrec [Mon, 10 Feb 2020 16:40:46 +0000 (17:40 +0100)]
soc/add_cpu: simplify CPUNone integration
Florent Kermarrec [Mon, 10 Feb 2020 16:17:31 +0000 (17:17 +0100)]
soc/SoCBusHandler: add add_adapter method and use it to convert Master/Slave before connecting to the Bus
Florent Kermarrec [Mon, 10 Feb 2020 16:02:20 +0000 (17:02 +0100)]
soc/add_sdram: add sdram csr
Florent Kermarrec [Mon, 10 Feb 2020 15:55:15 +0000 (16:55 +0100)]
soc/add_sdram: fix rocket, shorten comments
Florent Kermarrec [Mon, 10 Feb 2020 15:38:20 +0000 (16:38 +0100)]
soc/add_sdram: improve API
Florent Kermarrec [Mon, 10 Feb 2020 15:28:11 +0000 (16:28 +0100)]
soc: add LiteXSoC class and mode add_identifier/uart/sdram to it
Florent Kermarrec [Mon, 10 Feb 2020 15:21:21 +0000 (16:21 +0100)]
soc_core/sdram: cleanup, add disclaimer
Florent Kermarrec [Mon, 10 Feb 2020 15:01:19 +0000 (16:01 +0100)]
soc: add add_sdram
Florent Kermarrec [Mon, 10 Feb 2020 14:10:08 +0000 (15:10 +0100)]
soc: add csr_regions, update copyright
Florent Kermarrec [Mon, 10 Feb 2020 13:48:46 +0000 (14:48 +0100)]
soc: add cpu rom/sram check
Florent Kermarrec [Mon, 10 Feb 2020 13:35:36 +0000 (14:35 +0100)]
soc: add SOCIORegion and manage it
Florent Kermarrec [Mon, 10 Feb 2020 12:07:09 +0000 (13:07 +0100)]
soc: reorder main components/peripherals
Florent Kermarrec [Sun, 9 Feb 2020 20:56:32 +0000 (21:56 +0100)]
soc: add add_cpu method
Florent Kermarrec [Sun, 9 Feb 2020 18:01:03 +0000 (19:01 +0100)]
soc: fix unit-tests
Florent Kermarrec [Sat, 8 Feb 2020 20:57:02 +0000 (21:57 +0100)]
soc: integrate constants/build
Florent Kermarrec [Sat, 8 Feb 2020 20:34:26 +0000 (21:34 +0100)]
soc: show sorted regions (by origin) / locs
Florent Kermarrec [Sat, 8 Feb 2020 20:30:34 +0000 (21:30 +0100)]
soc: simplify color theme
Florent Kermarrec [Sat, 8 Feb 2020 09:19:18 +0000 (10:19 +0100)]
soc: add add_uart method
Florent Kermarrec [Fri, 7 Feb 2020 22:16:29 +0000 (23:16 +0100)]
soc_core: cleanup imports
Florent Kermarrec [Fri, 7 Feb 2020 22:11:08 +0000 (23:11 +0100)]
soc_core: get_csr_address no longer used
Florent Kermarrec [Fri, 7 Feb 2020 18:50:35 +0000 (19:50 +0100)]
soc: integrate CSR master/interconnect/collection and IRQ collection
Florent Kermarrec [Fri, 7 Feb 2020 18:09:54 +0000 (19:09 +0100)]
soc: add add_constant/add_config methods
Florent Kermarrec [Fri, 7 Feb 2020 17:49:20 +0000 (18:49 +0100)]
soc: add add_csr_bridge method
Florent Kermarrec [Fri, 7 Feb 2020 15:21:40 +0000 (16:21 +0100)]
soc: add add_controller/add_identifier/add_timer methods
Florent Kermarrec [Fri, 7 Feb 2020 14:57:46 +0000 (15:57 +0100)]
soc: add add_ram/add_rom methods
Florent Kermarrec [Fri, 7 Feb 2020 14:29:54 +0000 (15:29 +0100)]
soc: add automatic bus data width convertion to add_master/add_slave
Florent Kermarrec [Fri, 7 Feb 2020 14:19:02 +0000 (15:19 +0100)]
soc/soc_core: cleanup, remove some unused attributes
Florent Kermarrec [Fri, 7 Feb 2020 13:52:53 +0000 (14:52 +0100)]
soc: move SoCController from soc_core to soc
Florent Kermarrec [Fri, 7 Feb 2020 12:25:54 +0000 (13:25 +0100)]
soc: create SoCLocHandler and use it to simplify SoCCSRHandler and SoCIRQHandler
Florent Kermarrec [Thu, 6 Feb 2020 18:50:44 +0000 (19:50 +0100)]
soc: add use_loc_if_exists on SoCIRQ.add to use current location is already defined
Florent Kermarrec [Thu, 6 Feb 2020 17:50:17 +0000 (18:50 +0100)]
soc: add use_loc_if_exists on SoCCSR.add to use current location is already defined
Florent Kermarrec [Thu, 6 Feb 2020 10:07:50 +0000 (11:07 +0100)]
soc/integration: initial adaptation to new SoC class
Florent Kermarrec [Thu, 6 Feb 2020 10:06:41 +0000 (11:06 +0100)]
soc/integration: add new soc class prorotype with SoCRegion/SoCBus/SoCCSR/SoCIRQ/SoC
Florent Kermarrec [Thu, 6 Feb 2020 09:50:35 +0000 (10:50 +0100)]
cpu/vexriscv: update submodule
Sean Cross [Wed, 5 Feb 2020 10:05:04 +0000 (11:05 +0100)]
doc: add lxsocdoc.md (README from lxsocdoc repository)
enjoy-digital [Wed, 5 Feb 2020 09:15:21 +0000 (10:15 +0100)]
Merge pull request #375 from xobs/add-lxsocdoc
Add lxsocdoc
Florent Kermarrec [Tue, 4 Feb 2020 18:14:23 +0000 (19:14 +0100)]
bios/main: add LiteX tagline
enjoy-digital [Tue, 4 Feb 2020 17:19:33 +0000 (18:19 +0100)]
Merge pull request #376 from antmicro/build-sim-do-not-override-C-LD-FLAGS
build/sim: allow to use environment's {C,LD}FLAGS
Mariusz Glebocki [Mon, 3 Feb 2020 20:48:51 +0000 (21:48 +0100)]
build/sim: allow to use environment's {C,LD}FLAGS
There are use cases where additional flags should be added to CFLAGS or
LDFLAGS, e.g. when using Conda environment.
Sean Cross [Tue, 4 Feb 2020 15:49:08 +0000 (23:49 +0800)]
integration: svd: move svd generation to `export`
It was suggested that we should move svd generation into `export`,
alongside the rest of the generators such as csv, json, and h. This
performs this move, while keeping a compatible `generate_svd()` function
inside `soc/doc/`.
Signed-off-by: Sean Cross <sean@xobs.io>
Sean Cross [Tue, 4 Feb 2020 12:34:10 +0000 (20:34 +0800)]
soc: doc: use sphinx toctree as it was intended
The sphinx toctree was behaving oddly, and so previously we were
ignoring it completely. This patch causes it to be used correctly,
which removes the need for double-including various sections.
Signed-off-by: Sean Cross <sean@xobs.io>
Sean Cross [Tue, 4 Feb 2020 12:14:41 +0000 (20:14 +0800)]
litex-doc: initial merge of lxsocdoc
lxsocdoc enables automatic documentation of litex projects, including
automatic generation of SVD files.
This merges the existing lxsocdoc distribution into the `soc/doc` directory.
Signed-off-by: Sean Cross <sean@xobs.io>
enjoy-digital [Mon, 3 Feb 2020 11:55:48 +0000 (12:55 +0100)]
Merge pull request #373 from antmicro/l2-reverse
tools/litex_sim: use l2_reverse flag
Piotr Binkowski [Mon, 3 Feb 2020 11:03:57 +0000 (12:03 +0100)]
tools/litex_sim: use l2_reverse flag
Florent Kermarrec [Fri, 31 Jan 2020 18:31:33 +0000 (19:31 +0100)]
wishbone/Cache: add reverse parameter
Florent Kermarrec [Fri, 31 Jan 2020 18:16:54 +0000 (19:16 +0100)]
soc_sdram: add l2_reverse parameter
enjoy-digital [Fri, 31 Jan 2020 17:27:26 +0000 (18:27 +0100)]
Merge pull request #370 from Disasm/fixes
Small fixes
Vadim Kaushan [Fri, 31 Jan 2020 15:54:25 +0000 (18:54 +0300)]
Fix argument descriptions
Vadim Kaushan [Fri, 31 Jan 2020 15:53:50 +0000 (18:53 +0300)]
Pass --csr-json to the Builder
Florent Kermarrec [Fri, 31 Jan 2020 14:12:18 +0000 (15:12 +0100)]
soc_core: add UART bridge support (simplify having to do it externally)
Florent Kermarrec [Thu, 30 Jan 2020 12:55:13 +0000 (13:55 +0100)]
build/altera/quartus: fix fmt_r typo
Florent Kermarrec [Thu, 30 Jan 2020 12:42:02 +0000 (13:42 +0100)]
cpu/minerva: update (use new nMigen API)
Florent Kermarrec [Thu, 30 Jan 2020 08:35:40 +0000 (09:35 +0100)]
inteconnect/stream: use PipeValid implementation for Buffer
Florent Kermarrec [Thu, 30 Jan 2020 08:32:04 +0000 (09:32 +0100)]
inteconnect/stream: cleanup
enjoy-digital [Thu, 30 Jan 2020 07:18:12 +0000 (08:18 +0100)]
Merge pull request #366 from gsomlo/gls-csr-followup
software, integration/export: (re-)expose CSR subregister accessors
Gabriel Somlo [Wed, 29 Jan 2020 15:54:30 +0000 (10:54 -0500)]
software, integration/export: (re-)expose CSR subregister accessors
Expose a pair of `csr_[read|write]_simple()` subregister accessors, and
restore the way dedicated accessors are generated in "generated/csr.h"
to use hard-coded combinations of shifts and subregister accessor calls.
This restores downstream ability to override CSR handling at the
subregister accessor level.
Signed-off-by: Gabriel Somlo <gsomlo@gmail.com>
Florent Kermarrec [Wed, 29 Jan 2020 17:27:29 +0000 (18:27 +0100)]
interconnect/stream: add PipeValid and PipeWait to cut timing paths.
Florent Kermarrec [Wed, 29 Jan 2020 15:16:00 +0000 (16:16 +0100)]
build/xilinx/vivado: improve readability of generated tcl/xdc files
Florent Kermarrec [Wed, 29 Jan 2020 07:31:41 +0000 (08:31 +0100)]
integration/soc_core: revert integrate_sram_size default value (cause issues when using External SPRAM).
When using SoCCore, integrated SRAM can be disabled with integrated_sram_size=0 if not wanted.
enjoy-digital [Tue, 28 Jan 2020 14:36:24 +0000 (15:36 +0100)]
Merge pull request #363 from antmicro/litex-sim-ddr4
tools/litex_sim: add ddr4 PhySettings
Piotr Binkowski [Tue, 28 Jan 2020 13:28:24 +0000 (14:28 +0100)]
tools/litex_sim: add ddr4 PhySettings
Florent Kermarrec [Mon, 27 Jan 2020 20:30:13 +0000 (21:30 +0100)]
tools/litex_sim: add --sdram-init parameter
Florent Kermarrec [Mon, 27 Jan 2020 12:12:37 +0000 (13:12 +0100)]
software/bios: revert M-Labs MiSoC copyright.
Florent Kermarrec [Mon, 27 Jan 2020 11:12:53 +0000 (12:12 +0100)]
README: update copyright year and make sure LICENSE/README both mention MiSoC
Florent Kermarrec [Sun, 26 Jan 2020 13:29:32 +0000 (14:29 +0100)]
platforms/netv2: add pcie pins
enjoy-digital [Sun, 26 Jan 2020 10:44:14 +0000 (11:44 +0100)]
Merge pull request #359 from gregdavill/bios_ddr3_ecp5
soc/software/bios/sdram: On ECP5 strobe dly_sel after read leveling
Greg Davill [Sat, 25 Jan 2020 23:25:38 +0000 (09:55 +1030)]
soc/software/bios/sdram: ECP5 move strobe dly_sel
Greg Davill [Sat, 25 Jan 2020 02:41:39 +0000 (13:11 +1030)]
soc/software/bios/sdram: On ECP5 strobe dly_sel after read leveling
Florent Kermarrec [Fri, 24 Jan 2020 12:58:49 +0000 (13:58 +0100)]
tools/litex_sim: update copyrights and cosmetic changes
enjoy-digital [Fri, 24 Jan 2020 12:33:03 +0000 (13:33 +0100)]
Merge pull request #358 from antmicro/litex_sim_ddr
tools/litex_sim: add support for other sdram types
Piotr Binkowski [Fri, 24 Jan 2020 10:39:14 +0000 (11:39 +0100)]
tools/litex_sim: add support for other sdram types (DDR, LPDDR, DDR2, DDR3)
Right now litex_sim supports only SDR memories because it uses hardcoded
PhySettings. With this change PhySettings will be generated based on
selected sdram type which will allow us to use all the different types
of sdram chips in simulation.
Florent Kermarrec [Fri, 24 Jan 2020 08:06:35 +0000 (09:06 +0100)]
cores/clock/create_clkout: rename clk_ce to ce, improve error reporting
enjoy-digital [Fri, 24 Jan 2020 08:01:57 +0000 (09:01 +0100)]
Merge pull request #357 from betrusted-io/add_clk_ce
Add clk ce
bunnie [Fri, 24 Jan 2020 07:01:13 +0000 (15:01 +0800)]
add BUFIO to clockgen buffer options
bunnie [Fri, 24 Jan 2020 06:58:51 +0000 (14:58 +0800)]
add option for BUFGCE to the clock generator buffer types
Florent Kermarrec [Thu, 23 Jan 2020 14:42:31 +0000 (15:42 +0100)]
tools/litex_sim: review/cleanup sdram-module/sdram-data-width features.
enjoy-digital [Thu, 23 Jan 2020 14:34:53 +0000 (15:34 +0100)]
Merge pull request #354 from antmicro/litex_sim_ddr
tools/litex_sim: specify dram chip and data width via commandline
Piotr Binkowski [Thu, 23 Jan 2020 13:24:21 +0000 (14:24 +0100)]
tools/litex_sim: specify dram chip and data width via commandline
litex_sim used a single predefined DRAM chip, with this it is now
possible to specify which one to use with --sdram-module and also
its data bus width can be set using --sdram-data-width
enjoy-digital [Thu, 23 Jan 2020 13:16:02 +0000 (14:16 +0100)]
Merge pull request #351 from antmicro/fix_sram_size_argument
Fix sram size argument
Mateusz Holenko [Thu, 23 Jan 2020 12:37:02 +0000 (13:37 +0100)]
soc_core: rename integrated_sram_size argument
To keep a consistent naming scheme across all arguments.
Mateusz Holenko [Tue, 21 Jan 2020 15:36:45 +0000 (16:36 +0100)]
soc_core: fix integrated_sram_size argument type
Right now it's kept as a string and crashes
when trying to do math operations on it.
Florent Kermarrec [Tue, 21 Jan 2020 18:00:58 +0000 (19:00 +0100)]
build/xilinx/vivado: add pre_placement/pre_routing commands
Florent Kermarrec [Tue, 21 Jan 2020 13:08:36 +0000 (14:08 +0100)]
cores/icap: add add_timing_constraints method
Florent Kermarrec [Tue, 21 Jan 2020 13:08:17 +0000 (14:08 +0100)]
cores/dna: cleanup and add add_timing_constraints method
Florent Kermarrec [Mon, 20 Jan 2020 20:19:22 +0000 (21:19 +0100)]
tools/litex_sim: cleanup/simplify
Florent Kermarrec [Mon, 20 Jan 2020 11:54:46 +0000 (12:54 +0100)]
build/sim: add -Wl,--no-as-needed to LDFLAGS for Ubuntu 16.04 support (thanks kamejoko80)
Florent Kermarrec [Mon, 20 Jan 2020 11:10:00 +0000 (12:10 +0100)]
targets: use mem_region.origin instead of mem_map definition (prepare for automatic mem_region allocation)
Florent Kermarrec [Mon, 20 Jan 2020 11:05:08 +0000 (12:05 +0100)]
soc_core: add new alloc_mem/add_mem_region to allow automatic allocation of memory regions
With add_memory_region, user needs to provide the memory origin, which should not be needed since
could be retrieved from mem_map and prevent automatic allocation which is already possible for csr
and interrupts.
New add_mem_region method now allows both: defining the memory origin in mem_map (which will then
be used) or let the SoC builder automatically find and allocate a memory region.
bunnie [Sun, 19 Jan 2020 19:55:10 +0000 (20:55 +0100)]
cores/clock/xadc: ease DRP timings
Hard IP blocks are fixed in location, so long/deep combinational paths routing to multiple hard IP blocks can lead to timing closure problems.
XADC and MMCM DRPs currently have their DEN pins triggered by the ".re" output of a CSR. This is asynchronously derived from a fairly complicated set of logic that involves a logic path that goes all the way back through the cache and arbitration mechanisms of the wishbone bus. On more complex designs, this is leading to a failure of timing closure for these paths, because the hard IP blocks can be located in disparate portions of the chip which "pulls" the logic cluster in opposite directions in an attempt to absorb the routing delays to these IP blocks, leading to non-optimal placement for everything else and thus timing closure problems.
This pull request proposes that we add a pipeline delay on these critical paths. This delays the commit of the data to the DRP by one cycle, but greatly relieves timing because the pipeline register can be placed close to the cluster of logic that computes addresses, caching, and arbitration, allowing for the routing slack to the hard IP blocks to be absorbed by the path between the pipe register and the hard IP block.
In general, this shouldn't be a problem because the algorithm to program the DRP is to hit the write or read CSR, and then poll the drdy bit until it is asserted (so the process is already pretty slow). The MMCM in particular should have almost no impact, because MMCM updates are infrequent and the subsequent lock time of the MMCM is pretty long. The XADC is potentially more problematic because it can produce data at up to 1MSPS; but if sysclk is around 100MHz, adding 10ns to the read latency is relatively small compared to the theoretical maximum data rate of one every 1,000ns.
Note that the xadc patch requires introducing a bit of logic into the non-DRP path. This is because without explicitly putting an "if" statement around the logic, you fall back to the non-blocking semantics of the verilog operator, which ultimately leads to a pretty hefty combinational path. By having a default "if" that should get optimized out when DRP is not enabled, when the DRP path /is/ enabled the synthesizer knows it can safely push the async signal into a simple mux as opposed to worrying about enforcing the non-blocking operator semantics to get the desired result.
Florent Kermarrec [Fri, 17 Jan 2020 12:24:45 +0000 (13:24 +0100)]
test/test_targets: limit max_sdram_size to 1GB
Florent Kermarrec [Fri, 17 Jan 2020 12:17:08 +0000 (13:17 +0100)]
targets/nexys4ddr: fix typo
Florent Kermarrec [Fri, 17 Jan 2020 11:45:23 +0000 (12:45 +0100)]
SoCSDRAM: set default max_sdram_size to 1GB (maximum we can map with current mem_map)
Florent Kermarrec [Fri, 17 Jan 2020 11:27:21 +0000 (12:27 +0100)]
targets/kcu105: remove main_ram_size_limit
Florent Kermarrec [Fri, 17 Jan 2020 11:16:08 +0000 (12:16 +0100)]
SoCSDRAM: rename main_ram_size_limit to max_sdram_size and make it a parameter of SoCSDRAM, expose SoCSDRAM parameters to user
Florent Kermarrec [Fri, 17 Jan 2020 07:53:24 +0000 (08:53 +0100)]
build/lattice: add add_false_path_constraint method for API compatibility but false paths are not yet used/translated to .lpf file
Florent Kermarrec [Fri, 17 Jan 2020 05:32:00 +0000 (06:32 +0100)]
soc/cores/uart: set rx_fifo_rx_we to True on UARTCrossover
Florent Kermarrec [Thu, 16 Jan 2020 18:45:41 +0000 (19:45 +0100)]
soc/cores/uart: add rx_fifo_rx_we parameter to pulse rx_fifo.source.ready on rxtx register read.
When UARTCrossover is used over Etherbone, acking data directly with the read avoid the write/read round-trip
and speed up communication a lot (>10x).
Florent Kermarrec [Thu, 16 Jan 2020 15:20:25 +0000 (16:20 +0100)]
cpu/vexriscv: use 32-bit signal for externalResetVector