mesa.git
7 years agost/va: flush pipeline after post processing
sguttula [Thu, 10 Nov 2016 05:59:53 +0000 (00:59 -0500)]
st/va: flush pipeline after post processing

This will flush the pipeline,which will allow to share dma-buf based
buffers.

Signed-off-by: Suresh Guttula <Suresh.Guttula@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
7 years agomain/fbobject: throw invalid operation when get_attachment fails if needed
Alejandro Piñeiro [Thu, 12 Jan 2017 18:09:17 +0000 (16:09 -0200)]
main/fbobject: throw invalid operation when get_attachment fails if needed

In most cases, if a call to get_attachment fails is because attachment
is a INVALID_ENUM. But for some specific cases, if COLOR_ATTACHMENTm
(where m >= MAX_COLOR_ATTACHMENTS) is used, it should raise an
INVALID_OPERATION exception instead.

Fixes:
GL45-CTS.direct_state_access.framebuffers_get_attachment_parameter_errors
GL45-CTS.direct_state_access.framebuffers_renderbuffer_attachment_errors

v2: extra new line before quote block. Include "color attachment" on both
    new message errors (Nicolai).

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
7 years agomain/fboject: return if it is color_attachment on get_attachment
Alejandro Piñeiro [Thu, 12 Jan 2017 18:03:00 +0000 (16:03 -0200)]
main/fboject: return if it is color_attachment on get_attachment

Some callers would need that info to know if they should raise
INVALID_ENUM or INVALID_OPERATION. An alternative would be the caller
to check if the attachment is a GL_COLOR_ATTACHMENTm, but that seems
redundant as get_attachment is already doing that.

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
7 years agomesa/main: fix version/extension checks in _mesa_ClampColor
Nicolai Hähnle [Thu, 12 Jan 2017 09:55:33 +0000 (10:55 +0100)]
mesa/main: fix version/extension checks in _mesa_ClampColor

Add a proper check for feature support, and raise an invalid enum for
GL_CLAMP_VERTEX/FRAGMENT_COLOR unconditionally in core profiles, since
those enums were explicitly removed after the extension was promoted
to core functionality (not in the profile sense) with OpenGL 3.0.

This matches the behavior of the AMD closed source driver and fixes
GL45-CTS.gtf30.GL3Tests.half_float.half_float_textures.

Cc: "12.0 13.0" <mesa-stable@lists.freedesktop.org>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
7 years agoradeonsi: replace si_shader_context::soa by bld_base
Samuel Pitoiset [Thu, 12 Jan 2017 11:23:14 +0000 (12:23 +0100)]
radeonsi: replace si_shader_context::soa by bld_base

We no longer need to use lp_build_tgsi_soa_context.

No regressions founds with full piglit run.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
7 years agoradeonsi: replace ctx->soa.outputs by ctx->outputs
Samuel Pitoiset [Wed, 11 Jan 2017 15:28:51 +0000 (16:28 +0100)]
radeonsi: replace ctx->soa.outputs by ctx->outputs

The plan is to replace si_shader_context::soa with its parent
structure (ie. bld_base).

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
7 years agoradeonsi: move si_shader_context::soa::addr to si_shader_context
Samuel Pitoiset [Wed, 11 Jan 2017 15:21:23 +0000 (16:21 +0100)]
radeonsi: move si_shader_context::soa::addr to si_shader_context

The plan is to replace si_shader_context::soa with its parent
structure (ie. bld_base).

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
7 years agoradeonsi: allocate the array of immediates dynamically
Samuel Pitoiset [Wed, 11 Jan 2017 13:50:41 +0000 (14:50 +0100)]
radeonsi: allocate the array of immediates dynamically

Currently, we can store up to 256 immediates in a static array,
but this is not always enough. Instead, allocate a dynamic array
like what we currently do for temps.

This fixes a segfault with
dEQP-GLES31.functional.ssbo.layout.random.all_shared_buffer.23

No regressions found with full piglit run.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
7 years agoradv: remove some unused macros and functions
Grazvydas Ignotas [Wed, 11 Jan 2017 01:31:24 +0000 (03:31 +0200)]
radv: remove some unused macros and functions

These seem unlikely to be used.
Also remove irrelevant comment about SKL.

v2: forgot to rebase on master

Signed-off-by: Grazvydas Ignotas <notasas@gmail.com>
7 years agoanv: Avoid some resolves for samplable HiZ buffers
Nanley Chery [Thu, 15 Dec 2016 02:20:26 +0000 (18:20 -0800)]
anv: Avoid some resolves for samplable HiZ buffers

v2: Simplify nested ifs (Jason Ekstrand)

Signed-off-by: Nanley Chery <nanley.g.chery@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
7 years agoanv: Enable sampling from HiZ
Nanley Chery [Wed, 11 Jan 2017 16:12:48 +0000 (08:12 -0800)]
anv: Enable sampling from HiZ

v2: Restrict ISL_AUX_USAGE_HIZ to depth aspects

Signed-off-by: Nanley Chery <nanley.g.chery@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
7 years agoanv/blorp: Don't fast depth clear samplable HiZ buffers on BDW
Nanley Chery [Thu, 15 Dec 2016 17:57:48 +0000 (09:57 -0800)]
anv/blorp: Don't fast depth clear samplable HiZ buffers on BDW

Avoid the resolves that would be required if fast depth clears were
allowed for such buffers.

Signed-off-by: Nanley Chery <nanley.g.chery@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
7 years agoanv: Add a helper to determine sampling with HiZ
Nanley Chery [Tue, 10 Jan 2017 03:24:44 +0000 (19:24 -0800)]
anv: Add a helper to determine sampling with HiZ

Signed-off-by: Nanley Chery <nanley.g.chery@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
7 years agoisl/surface_state: Handle ISL_AUX_USAGE_HIZ
Nanley Chery [Mon, 5 Dec 2016 23:24:28 +0000 (15:24 -0800)]
isl/surface_state: Handle ISL_AUX_USAGE_HIZ

v2: Remove redundant x/y offset asserts (Jason Ekstrand)

Signed-off-by: Nanley Chery <nanley.g.chery@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
7 years agoanv: Perform HiZ resolves only on layout transitions
Nanley Chery [Mon, 2 Jan 2017 09:06:15 +0000 (01:06 -0800)]
anv: Perform HiZ resolves only on layout transitions

This is a better mapping to the Vulkan API and improves performance in
all tested workloads.

v2: Remove unnecessary image view aspect checks (Jason Ekstrand)

Signed-off-by: Nanley Chery <nanley.g.chery@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
7 years agoanv: Disable HiZ for input attachments
Nanley Chery [Wed, 11 Jan 2017 23:12:35 +0000 (15:12 -0800)]
anv: Disable HiZ for input attachments

v2 (Jason Ekstrand):
- Add spec citation
- Drop conditional

Signed-off-by: Nanley Chery <nanley.g.chery@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
7 years agoanv: Avoid resolves incurred by fast depth clears
Nanley Chery [Tue, 6 Dec 2016 17:08:09 +0000 (09:08 -0800)]
anv: Avoid resolves incurred by fast depth clears

Signed-off-by: Nanley Chery <nanley.g.chery@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
7 years agoanv: Prepare for transitioning to the requested final layout
Nanley Chery [Mon, 9 Jan 2017 18:44:36 +0000 (10:44 -0800)]
anv: Prepare for transitioning to the requested final layout

Signed-off-by: Nanley Chery <nanley.g.chery@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
7 years agoanv: Store depth stencil layouts
Nanley Chery [Mon, 2 Jan 2017 08:44:08 +0000 (00:44 -0800)]
anv: Store depth stencil layouts

Store the current and requested depth stencil layouts so that we can
perform the appropriate HiZ resolves for a given transition while
recording a render pass.

Signed-off-by: Nanley Chery <nanley.g.chery@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
7 years agoanv: Add helpers to handle depth buffer layout transitions
Nanley Chery [Thu, 15 Dec 2016 01:58:41 +0000 (17:58 -0800)]
anv: Add helpers to handle depth buffer layout transitions

Signed-off-by: Nanley Chery <nanley.g.chery@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
7 years agoanv: Delete anv's HiZ op emit function
Nanley Chery [Fri, 6 Jan 2017 07:34:38 +0000 (23:34 -0800)]
anv: Delete anv's HiZ op emit function

This is no longer used.

Signed-off-by: Nanley Chery <nanley.g.chery@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
7 years agoanv: Use the gen8 BLORP HiZ resolving function
Nanley Chery [Wed, 11 Jan 2017 21:05:13 +0000 (13:05 -0800)]
anv: Use the gen8 BLORP HiZ resolving function

Signed-off-by: Nanley Chery <nanley.g.chery@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
7 years agoanv/blorp: Add a gen8 HiZ op resolve function
Nanley Chery [Fri, 6 Jan 2017 07:32:07 +0000 (23:32 -0800)]
anv/blorp: Add a gen8 HiZ op resolve function

Add an entry point for resolving using BLORP's gen8 HiZ op function.

v2: Manually add the aux info

Signed-off-by: Nanley Chery <nanley.g.chery@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
7 years agoanv: Use gen8 BLORP HiZ clearing functions
Nanley Chery [Fri, 6 Jan 2017 00:46:37 +0000 (16:46 -0800)]
anv: Use gen8 BLORP HiZ clearing functions

Signed-off-by: Nanley Chery <nanley.g.chery@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
7 years agointel/blorp_clear: Add gen8 HiZ clearing functions
Nanley Chery [Wed, 11 Jan 2017 00:17:26 +0000 (16:17 -0800)]
intel/blorp_clear: Add gen8 HiZ clearing functions

Add an entry point for the optimized gen8 BLORP HiZ sequence. commit
c9eaf12de20ac4143fe79d42018bdbb5a391356f fixed a bug that was
unknowingly worked around by forcing additional clear rectangle
alignment restrictions not specified in the PRMs. Now that the bug is no
longer present, omit the additional alignment restrictions.

v2: Adjust code comment about padding

Signed-off-by: Nanley Chery <nanley.g.chery@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
7 years agoanv: Enable HiZ support for multiple subpasses
Nanley Chery [Sun, 8 Jan 2017 02:18:43 +0000 (18:18 -0800)]
anv: Enable HiZ support for multiple subpasses

We'll be using layout transitions later on in the series which can occur
within and between subpasses. Turn this on now to simplify the change
later.

Signed-off-by: Nanley Chery <nanley.g.chery@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
7 years agoanv: Use ::anv_attachment_state for toggling HiZ per subpass
Nanley Chery [Mon, 9 Jan 2017 12:47:31 +0000 (04:47 -0800)]
anv: Use ::anv_attachment_state for toggling HiZ per subpass

We're about to enable HiZ support for multiple subpasses. Use this field
to keep track of whether or not subpass operations should treat the
depth buffer as having an auxiliary HiZ buffer.

Signed-off-by: Nanley Chery <nanley.g.chery@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
7 years agoanv: Replace anv_image_has_hiz() with ISL_AUX_USAGE_HIZ
Nanley Chery [Sat, 7 Jan 2017 23:10:57 +0000 (15:10 -0800)]
anv: Replace anv_image_has_hiz() with ISL_AUX_USAGE_HIZ

The helper doesn't provide additional functionality over the current
infrastructure.

v2: Add comment to anv_image::aux_usage (Jason Ekstrand)
v3: Clarify comment for aux_usage (Jason Ekstrand)

Signed-off-by: Nanley Chery <nanley.g.chery@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
7 years agoanv/blorp: Handle ISL_AUX_USAGE_HIZ
Nanley Chery [Sat, 7 Jan 2017 23:47:36 +0000 (15:47 -0800)]
anv/blorp: Handle ISL_AUX_USAGE_HIZ

Prevent assert failures that would occur in the next patch.

v2: Don't remove asserts from blorp/blit (Jason Ekstrand)

Signed-off-by: Nanley Chery <nanley.g.chery@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
7 years agointel/blorp: Add the BDW+ optimized HZ_OP sequence to BLORP
Nanley Chery [Tue, 10 Jan 2017 20:06:42 +0000 (12:06 -0800)]
intel/blorp: Add the BDW+ optimized HZ_OP sequence to BLORP

We'll be switching to layout-transition based resolves which can occur
outside of a render pass. Add this sequence to BLORP, as using BLORP
will enable emitting depth stencil state outside of a render pass (among
other benefits). The depth buffer extent is ignored to enable eventual
usage in VkCmdClearAttachments().

Signed-off-by: Nanley Chery <nanley.g.chery@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
7 years agoget-typod-pick-list.sh: add new script
Emil Velikov [Fri, 16 Dec 2016 15:08:30 +0000 (15:08 +0000)]
get-typod-pick-list.sh: add new script

Typos do happen as people nominate patches for stable. This script aims
to catch most of those.

Due to the subtle nature of things, one has to pay special attention to
the output, similar to get-extra-pick-list.sh.

At the moment only the following is handled:
 grep -i "CC:.*mesa-dev"

Cc: 12.0 13.0 <mesa-stable@lists.freedesktop.org>
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
7 years agoac: automake: ensure that ./common is generated
Emil Velikov [Thu, 12 Jan 2017 22:13:21 +0000 (22:13 +0000)]
ac: automake: ensure that ./common is generated

Depending on the autoconf (or friends) version one may or may not have
the ./common folder created. Thus in the latter case we'll fail to
generate the file.

Reviewed-by: Thierry Reding <treding@nvidia.com>
Tested-by: Darren Salt <devspam@moreofthesa.me.uk>
Reported-by: Darren Salt <devspam@moreofthesa.me.uk>
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
7 years agonvc0/ir: only try to check for zero LOD if we aren't already forcing it
Ilia Mirkin [Fri, 13 Jan 2017 02:06:40 +0000 (21:06 -0500)]
nvc0/ir: only try to check for zero LOD if we aren't already forcing it

There's a levelZero flag which forces texturing to pick level zero (and
not consume an explicit LOD argument). This is set for MS targets, but
could also be set for any other incoming instruction. As that is what
determines whether a LOD argument is present, check that rather than the
more indirect isMS logic.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
7 years agonouveau: take extra push space into account for pushbuf_space calls
Ilia Mirkin [Wed, 11 Jan 2017 03:07:53 +0000 (22:07 -0500)]
nouveau: take extra push space into account for pushbuf_space calls

Ever since a long time ago when I messed around with fences, I ensure
that after a PUSH_SPACE call there is enough space to write a fence out
into the pushbuf.

However the PUSH_SPACE macro is not all-knowing, and so sometimes we
have to invoke nouveau_pushbuf_space manually with the relocs/pushes
args set. If we don't take the extra allocation from PUSH_SPACE into
account, then we will end up accidentally flushing when the code was not
expecting a flush. This can lead to various runtime and rendering
failures.

The amount of extra allocation isn't that important - it has to be at
least 8 based on the current nouveau_winsys.h setting, but even more
won't hurt. I just rounded up to powers of 2.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=99354
Cc: "12.0 13.0" <mesa-stable@lists.freedesktop.org>
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Acked-by: Ben Skeggs <bskeggs@redhat.com>
7 years agomapi: update the asm code to support x32
Grazvydas Ignotas [Sun, 8 Jan 2017 17:38:09 +0000 (19:38 +0200)]
mapi: update the asm code to support x32

Fixes crashes when both glx-tls and asm are enabled on x32.

Cc: mesa-stable@lists.freedesktop.org
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=94512
Bugzilla: https://bugs.gentoo.org/show_bug.cgi?id=575458
Signed-off-by: Grazvydas Ignotas <notasas@gmail.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Edward O'Callaghan <funfunctor@folklore1984.net>
7 years agoac/nir: use ac_emit_fdiv throughout
Nicolai Hähnle [Tue, 10 Jan 2017 14:46:17 +0000 (15:46 +0100)]
ac/nir: use ac_emit_fdiv throughout

... and eliminate emit_fdiv and nir_to_llvm_context::fpmath_md_*, which
are now unused.

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
7 years agoac/nir: use ac_build_gather_values[_extended] throughout
Nicolai Hähnle [Tue, 10 Jan 2017 14:44:04 +0000 (15:44 +0100)]
ac/nir: use ac_build_gather_values[_extended] throughout

... and eliminate the non-ac copies. Mostly straight-forward
search & replace.

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
7 years agoac/nir: use ac_emit_llvm_intrinsic throughout
Nicolai Hähnle [Tue, 10 Jan 2017 14:39:56 +0000 (15:39 +0100)]
ac/nir: use ac_emit_llvm_intrinsic throughout

... by straight-forward search & replace, and eliminate
emit_llvm_intrinsic.

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
7 years agoradeonsi: remove unused si_prepare_cube_coords
Nicolai Hähnle [Tue, 10 Jan 2017 16:20:57 +0000 (17:20 +0100)]
radeonsi: remove unused si_prepare_cube_coords

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
7 years agoamd/common: unify cube map coordinate handling between radeonsi and radv
Nicolai Hähnle [Tue, 10 Jan 2017 14:35:27 +0000 (15:35 +0100)]
amd/common: unify cube map coordinate handling between radeonsi and radv

Code is taken from a combination of radv (for the more basic functions,
to avoid gallivm dependencies) and radeonsi (for the new and improved
derivative calculations).

v2: add 0.5 offset to tex coords only after derivative calculation

v3:
- really only touch the first three coordinates
- rebase on the removal of the 1.5 --> 0.5 offset change

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl> (v2)
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
7 years agoradeonsi: only touch first three coordinates in si_prepare_cube_coords
Nicolai Hähnle [Tue, 10 Jan 2017 13:54:22 +0000 (14:54 +0100)]
radeonsi: only touch first three coordinates in si_prepare_cube_coords

Sourcing coords_arg[4] is actually never correct, since bias is handled
differently in tex_fetch_args anyway.

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
7 years agoradeonsi: remove unused si_llvm_cube_to_2d_coords
Nicolai Hähnle [Tue, 10 Jan 2017 12:16:11 +0000 (13:16 +0100)]
radeonsi: remove unused si_llvm_cube_to_2d_coords

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
7 years agoradeonsi: restrict cube map derivative computations to the correct plane
Nicolai Hähnle [Tue, 10 Jan 2017 10:47:22 +0000 (11:47 +0100)]
radeonsi: restrict cube map derivative computations to the correct plane

As remarked by the comment in the original code, the old algorithm fails when
(tc + deriv) points at a different cube face. Instead, simply project the
derivative directly to the plane of the selected cube face.

The new code is based on exactly differentiating (using the chain rule)
the projection onto a plane corresponding to a fixed cube map face (which
is still selected in the usual way based on the texture coordinate itself).
The computations end up fairly involved, but we do save two reciprocal
computations.

Fixes GL45-CTS.texture_cube_map_array.sampling.

v2: add 0.5 offset to tex coords only after derivative calculation
v3: go back to 1.5 offset

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl> (v2)
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
7 years agoradeonsi: communicate cube map coordinates more explicitly
Nicolai Hähnle [Tue, 10 Jan 2017 09:57:48 +0000 (10:57 +0100)]
radeonsi: communicate cube map coordinates more explicitly

v2: fix compile error that snuck in during rebase

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
7 years agoac/debug: move .gitignore for sid_tables.h too
Grazvydas Ignotas [Wed, 11 Jan 2017 23:58:59 +0000 (01:58 +0200)]
ac/debug: move .gitignore for sid_tables.h too

b838f642 "ac/debug: Move sid_tables.h generation to common code." moved
sid_tables.h but forgot the corresponding .gitignore.

Signed-off-by: Grazvydas Ignotas <notasas@gmail.com>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
7 years agonir/gcm: Fix a typo in a comment
Jason Ekstrand [Thu, 12 Jan 2017 22:09:30 +0000 (14:09 -0800)]
nir/gcm: Fix a typo in a comment

Reported-by: Matt Turner <mattst88@gmail.com>
7 years agonir/gcm: Rework the schedule late loop
Jason Ekstrand [Thu, 1 Dec 2016 21:51:03 +0000 (13:51 -0800)]
nir/gcm: Rework the schedule late loop

This fixes a bug in code motion that occurred when the best block is the
same as the schedule early block.  In this case, because we're checking
(lca != def->parent_instr->block) at the top of the loop, we never get to
the check for loop depth so we wouldn't move it out of the loop.  This
commit reworks the loop to be a simple for loop up the dominator chain and
we place the (lca != def->parent_instr->block) check at the end of the
loop.

Reviewed-by: Matt Turner <mattst88@gmail.com>
7 years agoglx: Add missing glproto dependency for gallium-xlib glx
Chuck Atkins [Fri, 6 Jan 2017 13:27:44 +0000 (08:27 -0500)]
glx: Add missing glproto dependency for gallium-xlib glx

Cc: mesa-stable@lists.freedesktop.org
Cc: Bruce Cherniak <bruce.cherniak@intel.com>
Signed-of-by: Chuck Atkins <chuck.atkins@kitware.com>
Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
7 years agoac, radeonsi: automake: add missing builddir include
Emil Velikov [Thu, 12 Jan 2017 21:54:03 +0000 (21:54 +0000)]
ac, radeonsi: automake: add missing builddir include

The generated file is correctly stored in the builddir as of earlier
commit. Yet the commit forgot to add the respective include flag thus
the compiler would error out failing to find sid_tables.h

Bugzila: https://bugs.freedesktop.org/show_bug.cgi?id=99389
Fixes: d1dc22eb466 "ac: automake: rework sid_tables.h generation"
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
7 years agoradv: Call NIR passes using NIR_PASS_V.
Bas Nieuwenhuizen [Sun, 8 Jan 2017 22:23:52 +0000 (23:23 +0100)]
radv: Call NIR passes using NIR_PASS_V.

Port of faa1edeeb7bbe9321c79587e592dce812e8caa78
"anv/pipeline: Call NIR passes using NIR_PASS_V"

Signed-off-by: Bas Nieuwenhuizen <basni@google.com>
Reviewed-by: Timothy Arceri <timothy.arceri@collabora.com>
7 years agoradv: Call nir_lower_constant_initializers.
Bas Nieuwenhuizen [Sun, 8 Jan 2017 22:17:38 +0000 (23:17 +0100)]
radv: Call nir_lower_constant_initializers.

Port of c5d664f9dc2d281c74844cef36ecb9f5862a8f6a
"anv/pipeline: Call nir_lower_constant_initializers"

Signed-off-by: Bas Nieuwenhuizen <basni@google.com>
Cc: <mesa-stable@lists.freedesktop.org>
Reviewed-by: Timothy Arceri <timothy.arceri@collabora.com>
7 years agoradv: Only call remove_dead_variables once.
Bas Nieuwenhuizen [Sun, 8 Jan 2017 21:39:36 +0000 (22:39 +0100)]
radv: Only call remove_dead_variables once.

Port of 43e0b0d4b255d910616c10e3e01bfec5db469e0e
"anv/pipeline: Only call remove_dead_variables once"

Signed-off-by: Bas Nieuwenhuizen <basni@google.com>
Reviewed-by: Timothy Arceri <timothy.arceri@collabora.com>
7 years agost/nine: Protect dtors with mutex
Axel Davy [Thu, 5 Jan 2017 22:04:09 +0000 (23:04 +0100)]
st/nine: Protect dtors with mutex

When the flag D3DCREATE_MULTITHREAD is set, a global mutex is used
to protect nine calls.
However for performance reasons, AddRef and Release didn't hold the mutex,
and instead used atomics.

Unfortunately at item release, the item can be destroyed, and that
destruction path should be protected by a mutex (at least for
some objects).

Without this patch, it is possible an app thread is in a dtor
while another thread is making gallium nine calls. It is possible
that two threads are using the same gallium pipe, which is forbiden.
The problem has been made worse with csmt, because it can cause hang,
since nine_csmt_process is not threadsafe.

Fixes Hitman hang, and possibly others.

Signed-off-by: Axel Davy <axel.davy@ens.fr>
7 years agost/nine: Flush the queue at device dtor
Axel Davy [Wed, 28 Dec 2016 17:58:48 +0000 (18:58 +0100)]
st/nine: Flush the queue at device dtor

Flush the queue to get refcounts right, and properly
release the items, instead of throwing away all pending
commands.

Signed-off-by: Axel Davy <axel.davy@ens.fr>
7 years agost/nine: Process pending commands on Reset
Axel Davy [Wed, 28 Dec 2016 17:49:10 +0000 (18:49 +0100)]
st/nine: Process pending commands on Reset

Some nine_state_* and nine_context_* functions
used for Reset() require all pending commands are
flushed.

Signed-off-by: Axel Davy <axel.davy@ens.fr>
7 years agost/nine: Flush pending commands if needed for surface9 changes
Axel Davy [Wed, 28 Dec 2016 17:32:39 +0000 (18:32 +0100)]
st/nine: Flush pending commands if needed for surface9 changes

nine_context uses NineSurface9 fields, thus we need to flush
pending commands using the surface before changing the fields.

Signed-off-by: Axel Davy <axel.davy@ens.fr>
7 years agost/nine: Rework CreatePipeSurface
Axel Davy [Wed, 28 Dec 2016 17:24:12 +0000 (18:24 +0100)]
st/nine: Rework CreatePipeSurface

Create both surfaces in one call.

Signed-off-by: Axel Davy <axel.davy@ens.fr>
7 years agost/nine: Remove duplicated checks
Axel Davy [Wed, 28 Dec 2016 16:54:47 +0000 (17:54 +0100)]
st/nine: Remove duplicated checks

There is no need to check on csmt_active before
calling nine_csmt_process, because the function
checks already.

Signed-off-by: Axel Davy <axel.davy@ens.fr>
7 years agost/nine: Don't call u_box_union_* when dirty region is empty
Masanori Kakura [Wed, 28 Dec 2016 13:21:02 +0000 (22:21 +0900)]
st/nine: Don't call u_box_union_* when dirty region is empty

When dirty region is empty, u_box_union_* incorrectly expands
the new region.

This fixes broken font rendering issue in WOLF RPG Editor v2.10 games.

Signed-off-by: Masanori Kakura <kakurasan@gmail.com>
Reviewed-by: Axel Davy <axel.davy@ens.fr>
7 years agowinsys/etnaviv: automake: introduce Makefile.sources
Emil Velikov [Thu, 12 Jan 2017 18:49:41 +0000 (18:49 +0000)]
winsys/etnaviv: automake: introduce Makefile.sources

... and list the public header within it.

Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
7 years agoetnaviv: automake: include all files in the sources lists
Emil Velikov [Thu, 12 Jan 2017 17:54:34 +0000 (17:54 +0000)]
etnaviv: automake: include all files in the sources lists

Note: the currently mentioned etnaviv_utils.h is typo.

Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
7 years agoac: automake: rework sid_tables.h generation
Emil Velikov [Thu, 12 Jan 2017 17:34:15 +0000 (17:34 +0000)]
ac: automake: rework sid_tables.h generation

Drop $(srcdir)/ prefix analogous to before the file (and rule) movement
and move it outside of the NEED_RADEON_LLVM conditional.

Otherwise the build may fail as below.

make[3]: *** No rule to make target 'common/sid_tables.h', needed by 'distdir'.  Stop.

Fixes: b838f642371 "ac/debug: Move sid_tables.h generation to common
code."
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
7 years agoautomake: use shared llvm libs for make distcheck
Emil Velikov [Thu, 12 Jan 2017 17:18:51 +0000 (17:18 +0000)]
automake: use shared llvm libs for make distcheck

Cc: "12.0 13.0" <mesa-dev@lists.freedesktop.org>
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
7 years agoautomake: add the new drivers etnaviv and imx to make distcheck
Emil Velikov [Thu, 12 Jan 2017 17:17:35 +0000 (17:17 +0000)]
automake: add the new drivers etnaviv and imx to make distcheck

Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
7 years agoimx: gallium driver for imx-drm scanout driver
Christian Gmeiner [Fri, 23 Dec 2016 20:10:29 +0000 (21:10 +0100)]
imx: gallium driver for imx-drm scanout driver

Changes from V1 -> V2:
 - updated Copyright
 - added $(top_srcdir)/src/gallium/winsys to include path (suggested by Emil)
 - adapted driver to new renderonly API

Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Acked-by: Emil Velikov <emil.velikov@collabora.com>
7 years agoetnaviv: gallium driver for Vivante GPUs
The etnaviv authors [Fri, 23 Dec 2016 19:58:23 +0000 (20:58 +0100)]
etnaviv: gallium driver for Vivante GPUs

This driver supports a wide range of Vivante IP cores like GC880,
GC1000, GC2000 and GC3000.

Changes from V1 -> V2:
 - added missing files to actually integrate the driver into build system.
 - adapted driver to new renderonly API

Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
Signed-off-by: Rob Herring <robh@kernel.org>
Signed-off-by: Russell King <rmk@arm.linux.org.uk>
Signed-off-by: Wladimir J. van der Laan <laanwj@gmail.com>
Acked-by: Emil Velikov <emil.velikov@collabora.com>
7 years agogallium: add renderonly library
Christian Gmeiner [Fri, 23 Dec 2016 19:33:10 +0000 (20:33 +0100)]
gallium: add renderonly library

This a very lightweight library to add basic support for renderonly
GPUs. A kms gallium driver must specify how a renderonly_scanout
objects gets created. Also it must provide file handles to the used
kms device and the used gpu device.

This could look like:
struct renderonly ro = {
   .create_for_resource = renderonly_create_gpu_import_for_resource,
   .kms_fd = fd,
   .gpu_fd = open("/dev/dri/renderD128", O_RDWR | O_CLOEXEC)
};

The renderonly_scanout object exits for two reasons:
 - Do any special treatment for a scanout resource like importing the
   GPU resource into the scanout hw.
 - Make it easier for a gallium driver to detect if anything special
   needs to be done in flush_resource(..) like a resolve to linear.

A GPU gallium driver which gets used as renderonly GPU needs to be
aware of the renderonly library.

This library will likely break android support and hopefully will get
replaced with a better solution based on gbm2.

Changes from V1 -> V2:
 - reworked the lifecycle of renderonly object (suggested by Nicolai Hähnle)
 - killed the midlayer (suggested by Thierry Reding)
 - made the API more explicit regarding gpu and kms fd's
 - added some docs

Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Acked-by: Emil Velikov <emil.velikov@collabora.com>
Tested-by: Alexandre Courbot <acourbot@nvidia.com>
7 years agospirv: Handle patch decorations up-front
Jason Ekstrand [Thu, 12 Jan 2017 02:04:57 +0000 (18:04 -0800)]
spirv: Handle patch decorations up-front

Once again, SPIR-V is insane... It allows you to place "patch"
decorations on structure members.  Presumably, this is so that you can
do something such as

out struct S {
   layout(location = 0) patch vec4 thing1;
   layout(location = 0) vec4 thing2;
} str;

And have your I/O "nicely" organized.  While this is a bit silly, it's
allowed and well-defined so whatever.  Where it really gets interesting
is when you have an array of struct.  SPIR-V says nothing about not
allowing you to have those qualifiers on the members of a struct that's
inside an array and GLSLang does this.  Specifically, if you have

layout(location = 0) out patch struct S {
   vec4 thing1;
   vec4 thing2;
} str[2];

then GLSLang will place the "patch" decorations on the struct members.
This is ridiculous there is no way that having some of them be patch and
some not would be well-defined given that patch and non-patch outputs
are in effectively different storage classes.  This commit moves around
the way we handle the "patch" decoration so that we can detect even the
crazy cases and handle them.

Fixes: dEQP-VK.tessellation.user_defined_io.per_patch_block_array.*
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
7 years agoanv: Support loader interface version 3 (patch v2)
Chad Versace [Wed, 11 Jan 2017 01:29:08 +0000 (17:29 -0800)]
anv: Support loader interface version 3 (patch v2)

This patch implements vk_icdNegotiateLoaderICDInterfaceVersion(), which
brings us to loader interface v3.

v2:
  - Drop the pragmas. [emil]
  - Advertise v3 instead of v2. Anvil supported more than I
    thought.  [jason]
  - s/Surface/SurfaceKHR/ in comments. [emil]

Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
Cc: mesa-stable@lists.freedesktop.org
Cc: Jason Ekstrand <jason@jlekstrand.net>
7 years agovulkan: Update vk_icd.h to interface version 3
Chad Versace [Tue, 10 Jan 2017 20:40:55 +0000 (12:40 -0800)]
vulkan: Update vk_icd.h to interface version 3

Import from commit f2aeefec on branch 'master'
of https://github.com/KhronosGroup/Vulkan-LoaderAndValidationLayers.

Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
Cc: mesa-stable@lists.freedesktop.org
7 years agovulkan: Add new cast macros for VkIcd types
Chad Versace [Tue, 10 Jan 2017 21:23:06 +0000 (13:23 -0800)]
vulkan: Add new cast macros for VkIcd types

We can't import the latest vk_icd.h because the new header breaks the
Mesa build. This patch defines new casting macros,
ICD_DEFINE_NONDISP_HANDLE_CASTS() and ICD_FROM_HANDLE(), which can
handle both the old and new vk_icd.h, and will prevent the build from
breaking when we update the header.

In the old vk_icd.h, types were defined as:

  typedef struct _VkIcdFoo {
    ...
  } VkIcdFoo;

Commit 6ebba1f6 in the Vulkan loader changed the above to

  typedef {
    ...
  } VkIcdFoo;

because the old definitions violated the C and C++ specs. According to
the specs, identifiers that begins with an underscore followed by an
uppercase letter are reserved. (It's pedantic, I know), See the Github
issue referenced below.

References: https://github.com/KhronosGroup/Vulkan-LoaderAndValidationLayers/issues/7
References: https://github.com/KhronosGroup/Vulkan-LoaderAndValidationLayers/commit/6ebba1f630015af7a78767a15c1e74ba9b23601c
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
Cc: mesa-stable@lists.freedesktop.org
7 years agoAlways defer memory free in swr_resource_destroy
George Kyriazis [Tue, 10 Jan 2017 23:12:03 +0000 (17:12 -0600)]
Always defer memory free in swr_resource_destroy

Defer delete on regular resources.  This ensures that any work being done
on the resource is completed before freeing up the resource's memory.

Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
7 years agonir/i965: assert first is always less than 64
Juan A. Suarez Romero [Thu, 12 Jan 2017 09:31:34 +0000 (10:31 +0100)]
nir/i965: assert first is always less than 64

This fixes a defect detected by Coverity Scan.

Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
7 years agonvc0: enable GL 4.3 on gm107+
Samuel Pitoiset [Mon, 22 Aug 2016 18:42:39 +0000 (20:42 +0200)]
nvc0: enable GL 4.3 on gm107+

Although, arb_shader_image_load_store-atomicity will most likely
hang your box, I think it's now quite reasonable to enable GL 4.3
on Maxwell/Pascal GPUs. I suspect that test to be wrong because
it doesn't even work on the NVIDIA blob.

I have tested a bunch of benchmarks (UE4 demos) and real games
like Shadow of Mordor and they all work fine.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
7 years agonvc0: use sched control codes for gm107 MP counters code
Samuel Pitoiset [Tue, 20 Dec 2016 12:46:14 +0000 (13:46 +0100)]
nvc0: use sched control codes for gm107 MP counters code

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Pierre Moreau <pierre.morrow@free.fr>
7 years agonvc0: use sched control codes for gm107 blitter shader
Samuel Pitoiset [Sun, 11 Dec 2016 22:17:10 +0000 (23:17 +0100)]
nvc0: use sched control codes for gm107 blitter shader

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Pierre Moreau <pierre.morrow@free.fr>
Acked-by: Ilia Mirkin <imirkin@alum.mit.edu>
7 years agonv50/ir: use sched control codes for gm107 builtins
Samuel Pitoiset [Mon, 19 Dec 2016 23:11:33 +0000 (00:11 +0100)]
nv50/ir: use sched control codes for gm107 builtins

Yes, IMUL/IMAD require dependency barriers and we should
definitely replace these instructions by XMAD but the
different flags need to be figured out. Note that XMAD only
supports 16-bits integers.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Pierre Moreau <pierre.morrow@free.fr>
7 years agonv50/ir: improve instruction pipelining on gm107
Samuel Pitoiset [Fri, 16 Dec 2016 13:28:14 +0000 (14:28 +0100)]
nv50/ir: improve instruction pipelining on gm107

This makes use of scheduling control codes which are very useful
for improving the instruction pipelining.

This patch will increase performance on Maxwell GPUs by, at least,
x1.5 up to x3.5 for some benchmarks.

Although this has been fairly well tested, I would not be suprised
if someone hit a corner case somewhere. That way, the scheduler
is enabled by default but it can be deactivated by using
NV50_PROG_SCHED=0.

Thanks to Scott Gray for the reverse engineering work available from
https://github.com/NervanaSystems/maxas/wiki/Control-Codes.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Acked-by: Pierre Moreau <pierre.morrow@free.fr>
Tested-by: Alexandre Courbot <acourbot@nvidia.com>
Tested-by: Jan Vesely <jan.vesely@rutgers.edu>
7 years agonv50/ir: do not insert texture barriers on gm107
Samuel Pitoiset [Fri, 16 Dec 2016 13:22:16 +0000 (14:22 +0100)]
nv50/ir: do not insert texture barriers on gm107

It's actually useless to insert those texture barriers post RA
because the current control code (ie. st 0x0) will wait for all
dependencies before issuing a new instruction.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Pierre Moreau <pierre.morrow@free.fr>
7 years agoi965/gen7: expose OpenGL 4.2 on Haswell when supported
Juan A. Suarez Romero [Tue, 11 Oct 2016 15:05:36 +0000 (15:05 +0000)]
i965/gen7: expose OpenGL 4.2 on Haswell when supported

GL_ARB_vertex_attrib_64bit was the last piece missing.

v2: update docs (Jordan)

Signed-off-by: Juan A. Suarez Romero <jasuarez@igalia.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
7 years agoi965: enable ARB_shader_precision to HSW+
Samuel Iglesias Gonsálvez [Mon, 17 Oct 2016 11:59:18 +0000 (13:59 +0200)]
i965: enable ARB_shader_precision to HSW+

v2: update docs (Jordan)

Signed-off-by: Samuel Iglesias Gonsálvez <siglesias@igalia.com>
Signed-off-by: Juan A. Suarez Romero <jasuarez@igalia.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
7 years agoi965: unify the code to enable of ARB_gpu_shader_fp64 and ARB_vertex_attrib_64bit...
Samuel Iglesias Gonsálvez [Mon, 17 Oct 2016 11:58:27 +0000 (13:58 +0200)]
i965: unify the code to enable of ARB_gpu_shader_fp64 and ARB_vertex_attrib_64bit for HSW+

Signed-off-by: Samuel Iglesias Gonsálvez <siglesias@igalia.com>
Signed-off-by: Juan A. Suarez Romero <jasuarez@igalia.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
7 years agoi965: Enable ARB_vertex_attrib_64bit for Haswell
Alejandro Piñeiro [Thu, 7 Jul 2016 09:49:33 +0000 (11:49 +0200)]
i965: Enable ARB_vertex_attrib_64bit for Haswell

v2: update docs (Jordan)

Signed-off-by: Alejandro Piñeiro <apinheiro@igalia.com>
Signed-off-by: Juan A. Suarez Romero <jasuarez@igalia.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
7 years agoi965: check for dual slot attributes on any gen
Juan A. Suarez Romero [Wed, 14 Dec 2016 17:12:24 +0000 (17:12 +0000)]
i965: check for dual slot attributes on any gen

Those not supporting 64 bit input vertex attributes will have the
dual_slot value as false.

Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
7 years agoi965/vec4: emit correctly load_inputs for 64bit data
Juan A. Suarez Romero [Wed, 6 Jul 2016 10:40:49 +0000 (12:40 +0200)]
i965/vec4: emit correctly load_inputs for 64bit data

For dvec3 and dvec4 types, a single GRF do not have enough space to
allocate two inputs from two different vertices (SIMD4x2).

So the GRF only contains first two components for the two vertices, and
the next GRF has the remaining components.

We want to put all the components for the same vertex in the same
register. Thus, we do a shuffle to reorder the data.

Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
7 years agoi965/vec4: take into account doubles when creating attribute mapping
Alejandro Piñeiro [Thu, 21 Apr 2016 12:16:18 +0000 (14:16 +0200)]
i965/vec4: take into account doubles when creating attribute mapping

Doubles needs more that one slot per attribute. So when filling the
attribute_map we check if it is a double in order to allocate one
extra register.

Signed-off-by: Alejandro Piñeiro <apinheiro@igalia.com>
Signed-off-by: Juan A. Suarez Romero <jasuarez@igalia.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
7 years agoi965/vec4/nir: vec4 also needs to remap vs attributes
Alejandro Piñeiro [Fri, 22 Apr 2016 08:49:24 +0000 (10:49 +0200)]
i965/vec4/nir: vec4 also needs to remap vs attributes

Doubles need extra space, so we would need to do a remapping for vec4
too in order to take that into account. We reuse the already
existing remap_vs_attrs, but passing is_scalar, so they could
remap accordingly.

v2: code-format remap_vs_attrs_params initialization (Matt)

Signed-off-by: Alejandro Piñeiro <apinheiro@igalia.com>
Signed-off-by: Juan A. Suarez Romero <jasuarez@igalia.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
7 years agoi965/vec4: use attribute slots for first non payload GRF
Alejandro Piñeiro [Thu, 21 Apr 2016 10:23:47 +0000 (12:23 +0200)]
i965/vec4: use attribute slots for first non payload GRF

As part of the payload setup, setup_attributes is called with the first
GRF that can be used for the attributes (first ones are used for
uniforms for example) and returns the first GRF that is not part of the
payload. Before this patch, it adds directly the number of attributes.
But as with 64-bit attributes can consume more than one slot, that is
not valid anymore. This patch change the addition to use the number of
slots consumed.

gen >= 8 would not be affected, as they use the scalar mode. For that
case, the vs configuration is done at fs_visitor::assign_vs_urb_setup.

v2: add explanation in commit log (Jordan)

Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
7 years agoi965: downsize *64*PASSTHRU formats to equivalent *32*FLOAT formats on gen < 8
Alejandro Piñeiro [Mon, 11 Apr 2016 08:05:24 +0000 (10:05 +0200)]
i965: downsize *64*PASSTHRU formats to equivalent *32*FLOAT formats on gen < 8

gen < 8 doesn't support *64*PASSTHRU formats when emitting
vertices. So in order to provide the equivalent functionality, we need
to downsize the format to equivalent *32*FLOAT, and in some cases
(R64G64B64 and R64G64B64A64) submit two 3DSTATE_VERTEX_ELEMENTS for
each vertex element.

Signed-off-by: Alejandro Piñeiro <apinheiro@igalia.com>
Signed-off-by: Juan A. Suarez Romero <jasuarez@igalia.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
7 years agoi965: return PASSTHRU surface types also on gen7
Alejandro Piñeiro [Fri, 15 Apr 2016 17:08:04 +0000 (19:08 +0200)]
i965: return PASSTHRU surface types also on gen7

Although gen7 doesn't include surface types as a valid conversion format,
we return it, as it reflects what we want to achieve, even if we need
to workaround it on gen < 8.

Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
7 years agomain/buffers: take into account FRONT_AND_BACK on ReadBuffer
Alejandro Piñeiro [Wed, 11 Jan 2017 20:11:55 +0000 (18:11 -0200)]
main/buffers: take into account FRONT_AND_BACK on ReadBuffer

From OpenGL 3.1 spec, section 4.3.1 "Reading Pixels", page 190 (203 PDF)

  "When READ FRAMEBUFFER BINDING is zero, i.e. the default
   framebuffer, src must be one of the values listed in table 4.4,
   including NONE . FRONT_AND_BACK , FRONT , and LEFT refer to the
   front left buffer."

There is an equivalent text on OpenGL 4.5 spec, section 18.2.1
"Selecting Buffers for Reading", page 502 (524 PDF), so the behaviour
is still the same.

Part of the fix for:
GL45-CTS.direct_state_access.framebuffers_draw_read_buffers_errors

Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com>
7 years agomain/buffers: update error handling on DrawBuffers for 4.5
Alejandro Piñeiro [Tue, 13 Dec 2016 10:58:59 +0000 (08:58 -0200)]
main/buffers: update error handling on DrawBuffers for 4.5

Before 4.5, GL_BACK was not allowed as a value of bufs. Since 4.5 it
is allowed under some circumstances:

From the OpenGL 4.5 specification, Section 17.4.1 "Selecting Buffers
for Writing", page 493 (page 515 of the PDF):
 "An INVALID_ENUM error is generated if any value in bufs is FRONT,
  LEFT, RIGHT, or FRONT_AND_BACK . This restriction applies to both
  the de- fault framebuffer and framebuffer objects, and exists
  because these constants may themselves refer to multiple buffers, as
  shown in table 17.4."

And on page 492 (page 514 of the PDF):
 "If the default framebuffer is affected, then each of the constants
  must be one of the values listed in table 17.6 or the special value
  BACK . When BACK is used, n must be 1 and color values are written
  into the left buffer for single-buffered contexts, or into the back
  left buffer for double-buffered contexts."

This patch keeps the same behaviour if OpenGL version is < 4. We
assume that for 4.x this is the intended behaviour, so a fix, but for
3.x the intended behaviour is the already in place.

Part of the fix for:
GL45-CTS.direct_state_access.framebuffers_draw_read_buffers_errors

v2: remove forgot printf
v3: remove spaces before commas on spec quote, split line too
    long (Anuj)

Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com>
7 years agoradeonsi: num_records is in units of stride for swizzled buffers even on VI
Nicolai Hähnle [Thu, 15 Dec 2016 15:11:54 +0000 (16:11 +0100)]
radeonsi: num_records is in units of stride for swizzled buffers even on VI

The old setting didn't hurt, but this is cleaner.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
7 years agodocs: document INTEL_PRECISE_TRIG envvar
Juan A. Suarez Romero [Wed, 11 Jan 2017 17:51:35 +0000 (18:51 +0100)]
docs: document INTEL_PRECISE_TRIG envvar

v2: use more generic description (Jordan)

Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
7 years agospirv: fix typo in warning message
Iago Toral Quiroga [Mon, 9 Jan 2017 15:09:55 +0000 (16:09 +0100)]
spirv: fix typo in warning message

Reviewed-by: Samuel Iglesias Gonsálvez <siglesias@igalia.com>
7 years agoi965: Enable predicate support on gen >= 8.
Rafael Antognolli [Thu, 5 Jan 2017 18:33:53 +0000 (10:33 -0800)]
i965: Enable predicate support on gen >= 8.

Predication needs cmd parser only on gen7. For newer platforms, it
should be available without it.

v2 (Ken): rebase on recent changes.

Signed-off-by: Rafael Antognolli <rafael.antognolli@intel.com>
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
7 years agoutil: fix list_is_singular()
Timothy Arceri [Wed, 11 Jan 2017 04:13:35 +0000 (15:13 +1100)]
util: fix list_is_singular()

Currently its dependant on the user calling and checking the result
of list_empty() before using the result of list_is_singular().

Cc: "13.0" <mesa-stable@lists.freedesktop.org>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
7 years agoanv/image: Disable HiZ for depth buffer arrays
Nanley Chery [Thu, 5 Jan 2017 14:58:03 +0000 (06:58 -0800)]
anv/image: Disable HiZ for depth buffer arrays

We currently don't perform clears or resolves on multiple array layers
with HiZ.

Cc: mesa-stable@lists.freedesktop.org
Signed-off-by: Nanley Chery <nanley.g.chery@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
7 years agoanv/cmd_buffer: Fix programmed HiZ qpitch
Nanley Chery [Thu, 5 Jan 2017 09:23:27 +0000 (01:23 -0800)]
anv/cmd_buffer: Fix programmed HiZ qpitch

Match the comment above the field by using units of pixels and not HiZ
blocks.

Cc: mesa-stable@lists.freedesktop.org
Suggested-by: Jason Ekstrand <jason@jlekstrand.net>
Signed-off-by: Nanley Chery <nanley.g.chery@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
7 years agoanv/cmd_buffer: Fix arrayed depth/stencil attachments
Nanley Chery [Mon, 19 Dec 2016 17:37:03 +0000 (09:37 -0800)]
anv/cmd_buffer: Fix arrayed depth/stencil attachments

Enable multiple layers of the depth/stencil buffers to be accessible.

Fixes the crucible test, func.depthstencil.arrayed_clear.

Cc: mesa-stable@lists.freedesktop.org
Signed-off-by: Nanley Chery <nanley.g.chery@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>