ac/gpu_info: add has_2d_tiling

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

ac/gpu_info: add has_sparse_vm_mappings

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

ac/gpu_info: add has_unaligned_shader_loads

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

radeonsi: expose ARB_query_buffer_object on ancient kernels too

It doesn't use indirect dispatches.

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

ac/gpu_info: add has_indirect_compute_dispatch

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

ac/gpu_info: add kernel_flushes_tc_l2_after_ib

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

ac/gpu_info: add has_format_bc1_through_bc7

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

ac/gpu_info: add has_eqaa_surface_allocator

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

radeonsi: clean up the reset status query implementation

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

ac/gpu_info: add has_bo_metadata

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

ac/gpu_info: add si_TA_CS_BC_BASE_ADDR_allowed

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

ac/gpu_info: add htile_cmask_support_1d_tiling

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

ac/gpu_info: add kernel_flushes_hdp_before_ib

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

radeonsi: add an environment variable that forces EQAA for MSAA allocations

This is for testing and experiments.

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

radeonsi: set up EQAA image descriptors properly

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

radeonsi: add EQAA SC,DB,CB register programming

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

radeonsi: support creating EQAA color textures

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

ac/surface: add EQAA support

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

radeonsi: use better sample locations for 8x EQAA

Verified with the piglit MSAA accuracy test.

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

radeonsi: improve quality of 16 sample locations

This results in better 16x and 8x quality when using these locations.
Verified with the piglit MSAA accuracy test.

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

radeonsi: use better sample locations for 4x MSAA

Discovered by luck. Verified with the piglit MSAA accuracy test.
It also shows that the worst case EQAA 16s4f results in very good 4x MSAA
in the worst case.

Nine might not like these positions, but they are prettier to the eye and
GL doesn't care.

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

radeonsi: reorder sample locations as required by EQAA

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

radeonsi: simplify si_get_sample_position

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

radeonsi: simplify arrays of sample locations

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

radeonsi: set DB_EQAA the same as Vulkan

These never change, but they only affect EQAA, which isn't implemented.

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

radeonsi: remove CM_ prefixes

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

radeonsi: don't update clear color registers if they don't change

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

radeonsi: remove r600_fmask_info

radeon_surf contains almost everything.

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

ac/surface: unify common legacy and gfx9 fmask fields

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

ac/surface/gfx6: compute FMASK together with the color surface

instead of invoking FMASK computation separately.

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

ac/surface/gfx9: fix a typo in CMASK RB/pipe alignment

No change in behavior because it's always aligned.

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

ac: set correct LLVM processor names for Raven & Vega12

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

ac: sort raster configs

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

ac: remove 1 RB raster config for Iceland

Iceland always reports 2 RBs.

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

ac: move the Fiji kernel workaround for raster config out of the switch

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

ac: enable both RBs on Kaveri

This can result in 2x increase in performance on non-harvested Kaveris.

v2: don't do it on radeon

Tested-by: Michel Dänzer <michel.daenzer@amd.com>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

radeonsi/gfx9: work around a GPU hang due to broken indirect indexing in LLVM

Fixes: 6d19120da85 "radeonsi/gfx9: workaround for INTERP with indirect indexing"
Cc: 18.1 <mesa-stable@lists.freedesktop.org>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

intel/isl/storage: Don't lower most UNORM formats on gen11+

Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com>
Tested-by: Anuj Phogat <anuj.phogat@gmail.com>

intel/isl: Several UNORM formats support typed writes on gen11+

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com>
Tested-by: Anuj Phogat <anuj.phogat@gmail.com>

mesa: revert GL_[SECONDARY_]COLOR_ARRAY_SIZE glGet type to TYPE_INT

Since size can be 3, 4 or GL_BGRA we need to keep these glGet types
as TYPE_INT, not TYPE_UBYTE.

Fixes: d07466fe18522 ("mesa: fix glGetInteger/Float/etc queries for
vertex arrays attribs")
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=106462
cc: mesa-stable@lists.freedesktop.org
Reviewed-by: Mathias Fröhlich <mathias.froehlich@web.de>

radv: disable DCC for shareable images on GFX9+

This seems to be broken at the moment for opengl interop.

Signed-off-by: Andres Rodriguez <andresx7@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>

configure.ac: rework -latomic check

The configure.ac logic added in commit
2ef7f23820a67e958c2252bd81eb0458903ebf33 ("configure: check if
-latomic is needed for __atomic_*") makes the assumption that if a
64-bit atomic intrinsic test program fails to link without -latomic,
it is because we must use -latomic.

Unfortunately, this is not completely correct: libatomic only appeared
in gcc 4.8, and therefore gcc versions before that will not have
libatomic, and therefore don't provide atomic intrinsics for all
architectures. This issue was for example encountered on PowerPC with
a gcc 4.7 toolchain, where the build fails with:

powerpc-ctng_e500v2-linux-gnuspe/bin/ld: cannot find -latomic

This commit aims at fixing that, by not assuming -latomic is
available. The commit re-organizes the atomic intrinsics detection as
follows:

 (1) Test if a program using 64-bit atomic intrinsics links properly,
     without -latomic. If this is the case, we have atomic intrinsics,
     and we're good to go.

 (2) If (1) has failed, then test to link the same program, but this
     time with -latomic in LDFLAGS. If this is the case, then we have
     atomic intrinsics, provided we link with -latomic.

This has been tested in three situations:

 - On x86-64, where atomic instrinsics are all built-in, with no need
   for libatomic. In this case, config.log contains:

   GCC_ATOMIC_BUILTINS_SUPPORTED_FALSE='#'
   GCC_ATOMIC_BUILTINS_SUPPORTED_TRUE=''
   LIBATOMIC_LIBS=''

   This means: atomic intrinsics are available, and we don't need to
   link with libatomic.

 - On NIOS2, where atomic intrinsics are available, but some of them
   (64-bit ones) require using libatomic. In this case, config.log
   contains:

   GCC_ATOMIC_BUILTINS_SUPPORTED_FALSE='#'
   GCC_ATOMIC_BUILTINS_SUPPORTED_TRUE=''
   LIBATOMIC_LIBS='-latomic'

   This means: atomic intrinsics are available, and we need to link
   with libatomic.

 - On PowerPC with an old gcc 4.7 toolchain, where 32-bit atomic
   instrinsics are available, but not 64-bit atomic instrinsics, and
   there is no libatomic. In this case, config.log contains:

   GCC_ATOMIC_BUILTINS_SUPPORTED_FALSE=''
   GCC_ATOMIC_BUILTINS_SUPPORTED_TRUE='#'

   With means that atomic intrinsics are not usable.

Reviewed-by: Matt Turner <mattst88@gmail.com>
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@bootlin.com>

mesa: fix glGetInteger/Float/etc queries for vertex arrays attribs

The vertex array Size and Stride attributes are now ubyte and short,
respectively.  The glGet code needed to be updated to handle those
types, but wasn't.

Fixes the new piglit test gl-1.5-get-array-attribs test.

v2: fix inadvertant whitespace change, change COLOR_ARRAY_SIZE to UBYTE,
misc fixes suggested by Justin

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=106450
Fixes: d5f42f96e16 ("mesa: shrink size of gl_array_attributes (v2)")
Cc: mesa-stable@lists.freedesktop.org
Reviewed-by: Mathias Fröhlich <mathias.froehlich@web.de>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>

winsys/radeon: Destroy fd_hash table when the last winsys is removed.

Fixes memory leak on module unload.
v2: Use util_hash_table helper function

CC: <mesa-stable@lists.freedesktop.org>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Jan Vesely <jan.vesely@rutgers.edu>

gallium/auxiliary: Add helper function to count the number of entries in hash table

CC: <mesa-stable@lists.freedesktop.org>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Jan Vesely <jan.vesely@rutgers.edu>

radv: move handling nosisched option in a better place

It's a per-application optimization, so it makes more sense
to do that in radv_handle_per_app_options().

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>

radv: assorted typo fixes

Trivial.

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>

mesa/vbo/tnl: Move gl_vertex_array related stuff to tnl.

The only remaining users of gl_vertex_array are tnl based
drivers. So move everything related to that into tnl and
rename it accordingly.

Reviewed-by: Brian Paul <brianp@vmware.com>
Signed-off-by: Mathias Fröhlich <Mathias.Froehlich@web.de>

mesa: Remove Array._DrawArrays.

Only tnl based drivers still use this array. So remove it
from core mesa and use Array._DrawVAO instead.

Reviewed-by: Brian Paul <brianp@vmware.com>
Signed-off-by: Mathias Fröhlich <Mathias.Froehlich@web.de>

i965: Remove the now unused gl_vertex_array.

Was meant to be temporary in i965.

Reviewed-by: Brian Paul <brianp@vmware.com>
Signed-off-by: Mathias Fröhlich <Mathias.Froehlich@web.de>

i965: Remove the gl_vertex_array indirection.

For now store binding and attrib in brw_vertex_element.
The i965 driver still provides lots of opportunity to make use
of the unique binding information in the VAO which is currently not
taken from the VAO.

Reviewed-by: Brian Paul <brianp@vmware.com>
Signed-off-by: Mathias Fröhlich <Mathias.Froehlich@web.de>

i965: Implement all_varyings_in_vbos in terms of Array._DrawVAO.

Reviewed-by: Brian Paul <brianp@vmware.com>
Signed-off-by: Mathias Fröhlich <Mathias.Froehlich@web.de>

st/mesa: Remove the now unused gl_vertex_array.

Was meant to be temporary in gallium.

Reviewed-by: Brian Paul <brianp@vmware.com>
Signed-off-by: Mathias Fröhlich <Mathias.Froehlich@web.de>

st/mesa: Make feedback draw and rasterpos use _DrawVAO.

Instead of playing with Array._DrawArrays, make the feedback draw
path use Array._DrawVAO. Also st_RasterPos needs to use the VAO then.

v2: Use helper methods to get the offset values for array and binding.
    Update comments.

Reviewed-by: Brian Paul <brianp@vmware.com>
Signed-off-by: Mathias Fröhlich <Mathias.Froehlich@web.de>

st/mesa: Use Array._DrawVAO in st_atom_array.c.

Finally make use of the binding information in the VAO when
setting up arrays for draw.

v2: Emit less relocations also for interleaved userspace arrays.

Reviewed-by: Brian Paul <brianp@vmware.com>
Signed-off-by: Mathias Fröhlich <Mathias.Froehlich@web.de>

st/mesa: Make the input_to_index array available.

The input_to_index array is already available internally
when preparing vertex programs. Store the map in
struct st_vertex_program.
Also store the bitmask of mesa vertex processing inputs in
struct st_vp_variant.

Reviewed-by: Brian Paul <brianp@vmware.com>
Signed-off-by: Mathias Fröhlich <Mathias.Froehlich@web.de>

st/mesa: Use _DrawVAO for edgeflag enabled check.

Reviewed-by: Brian Paul <brianp@vmware.com>
Signed-off-by: Mathias Fröhlich <Mathias.Froehlich@web.de>

mesa: Compute effective buffer bindings in the vao.

Compute VAO buffer binding information past the position/generic0 mapping.
Scan for duplicate buffer bindings and collapse them into derived
effective buffer binding index and effective attribute mask variables.
Provide a set of helper functions to access the distilled
information in the VAO. All of them prefixed with _mesa_draw_...
to indicate that they are meant to query draw information.

v2: Also group user space arrays containing interleaved arrays.
    Add _Eff*Offset to be copied on attribute and binding copy.
    Update comments.

Reviewed-by: Brian Paul <brianp@vmware.com>
Signed-off-by: Mathias Fröhlich <Mathias.Froehlich@web.de>

virgl: Add support for passing GL_ANY_SAMPLES_PASSED_CONSERVATIVE

This is needed for fixing CTS:
   dEQP-GLES3.functional.occlusion_query.conservative*

Reviewed-by: Dave Airlie <airlied@redhat.com>
Signed-off-by: Gert Wollny <gert.wollny@collabora.com>

r600: fix constant buffer bounds.

If you have an indirect access to a constant buffer on r600/eg
use a vertex fetch in the shader. However apps have expected
behaviour on those out of bounds accessess (even if illegal).

If the constants were being uploaded as part of a larger
upload buffer, we'd set the range of allowed access to a lot
larger than required so apps would get values back from
other parts of the upload buffer instead of the expected out
of bounds access.

This fixes rendering bugs in Trine and Witcher 1, thanks
to iive for nagging me effectively until I figured it out :-)

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=91808
Cc: <mesa-stable@lists.freedesktop.org>
Reviewed-by: Roland Scheidegger <sroland@vmware.com>

i965,anv: Set the CS stall bit on the ISP disable PIPE_CONTROL

From the bspec docs for "Indirect State Pointers Disable":

    "At the completion of the post-sync operation associated with this
    pipe control packet, the indirect state pointers in the hardware are
    considered invalid"

So the ISP disable is a post-sync type of operation which means that it
should be combined with a CS stall.  Without this, the simulator throws
an error.

Fixes: 766d801ca "anv: emit pixel scoreboard stall before ISP disable"
Fixes: f536097f6 "i965: require pixel scoreboard stall prior to ISP disable"
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>

radv: handle arrays in the fmask descriptor.

This fixes the fmask descriptor generation to handle 2d ms arrays.

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>

gallium/tests: Fix assignment of EXTRA_DIST

Fixes: 6754c2e83d79 ("autotools: Include new meson files")

configure.ac: Check for grep with AC_PROG_GREP

Perhaps with a new version of autoconf, I began seeing:

| checking the name lister (/usr/bin/nm -B) interface... ./configure: line 6973: External.*some_variable: command not found
| BSD nm

This is because AC_PROG_NM expands to

...
if $GREP 'External.*some_variable' conftest.out > /dev/null; then
    lt_cv_nm_interface="MS dumpbin"
fi
...

I'm not sure if it's a bug in AC_PROG_NM that it doesn't call
AC_PROG_GREP, but it's easy enough for us to do it.

main: fail texture_storage() call if the size is not okay

Signed-off-by: Xiong, James <james.xiong@intel.com>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

main: return 0 length when the queried program object's not linked

Signed-off-by: Xiong, James <james.xiong@intel.com>
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>

i965: Shut up unused variable warnings.

These are only used in assertions.

src/intel/Makefile.vulkan.am: add missing MKDIR_GEN

Out of tree builds can try to write into a directory that doesn't exist yet:

| Traceback (most recent call last):
|   File "../../../mesa-18.0.2/src/intel/vulkan/anv_icd.py", line 46, in <module>
|     with open(args.out, 'w') as f:
| IOError: [Errno 2] No such file or directory: 'vulkan/intel_icd.x86_64.json'
| Makefile:4882: recipe for target 'vulkan/intel_icd.x86_64.json' failed

Add missing MKDIR_GEN calls to solve this.

Cc: <mesa-stable@lists.freedesktop.org>
Reviewed-by: Matt Turner <mattst88@gmail.com>

mesa: fix error handling in get_framebuffer_parameteriv

CC: <mesa-stable@lists.freedesktop.org>
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>

anv: emit pixel scoreboard stall before ISP disable

We want to make sure that all indirect state data has been loaded into
the EUs before disable the pointers.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Rafael Antognolli <rafael.antognolli@intel.com>
Fixes: 78c125af3904c ("anv/gen10: Ignore push constant packets during context restore.")

i965: require pixel scoreboard stall prior to ISP disable

Invalidating the indirect state pointers might affect a previously
scheduled & still running 3DPRIMITIVE (causing page fault). So stall
on pixel scoreboard before that.

v2: Fix compile issue :(

v3: Stall on pixel scoreboard

v4: Drop the post sync operation (Lionel)

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Rafael Antognolli <rafael.antognolli@intel.com>
Fixes: ca19ee33d7d39 ("i965/gen10: Ignore push constant packets during context restore.")
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=106243

intel/isl: Allow CCS_E on 1010102 formats

On CNL and above, CCS_E supports 1010102 formats and R11G11B10F.  We had
shut them off during early enabling because blorp_copy couldn't handle
them.  Now it can handle 1010102 formats so we can turn them back on.

Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>

intel/blorp: Allow CCS copies of 1010102 formats

Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>

intel/blorp: Add support for more format bitcasting

nir_format_bitcast_uint_vec_unmasked can only be used to cast between
formats with uniform channel sizes.  In particular, it cannot handle
10_10_10_2 formats.  By making use of the NIR helper for uint vector
casts, we should now be able to bitcast between any two uint formats so
long as their channels are in RGBA order (possibly with channels
missing).  In order to do this we need to rework the key a bit to pass
the actual formats instead of just the number of bits in each.

Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>

intel/blorp: Use nir_format_bitcast_uint_vec_unmasked

Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>

nir/format_convert: Add code for bitcasting vectors

This is a fairly direct port from blorp.  The only real change is that
the nir_format_convert version doesn't assume that everything is a vec4.

Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>

intel/blorp: Use ISL instead of bitcast_color_value_to_uint

Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>

intel/isl: Add format conversion code

This adds helpers to ISL to convert an isl_color_value to and from
binary data encoded with a given isl_format.  The conversion is done
using ISL's built-in format introspection so it's fairly slow as format
conversions go but it should be fine for a single pixel value.  In
particular, we can use this to convert clear colors.

As a side-effect, we now rely on the sRGB helpers in libmesautil so we
need to tweak the build system a bit.  All prior uses of src/util in ISL
were header-only.

Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>

intel/isl/format: Get rid of the ALPHA colorspace

Alpha-only formats are just linear.  There's no need to specially
deliminate them as being in their own colorspace.

Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>

intel/isl/format: Add field locations informations to channel_layout

Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>

intel/isl/format: Add a column for channel order to the table

Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>

i965/blorp: Remove a pile of blorp_blit restrictions

Previously, blorp could only blit into something that was renderable.
Thanks to recent additions to blorp, it can now blit into basically
anything so long as it isn't compressed.

Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>

i965/blorp: Allow blorp blits for 16x MSAA

BLORP has supported 16x MSAA for quite a while now, we just never
bothered to enable it for CopyTexSubImage.

Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>

anv: Allow blitting to/from any supported format

Now that blorp handles all the cases, why not?  The only real change we
have to make is to stop using anv_swizzle_for_render() in blorp_blit
because it doesn't work for B4G4R4A4 and blorp now natively handles that.

Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>

intel/blorp: Support the RGB workaround on more formats

Previously we only supported UINT formats because that's what blorp_copy
required.  If we want to use it in blorp_blit, however, we need to
support everything.

Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>

intel/blorp: Silently convert RGBX destination formats to RGBA

Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>

intel/isl: Add some helpers for working with RGBX formats

Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>

intel/blorp: Handle more exotic destination formats

This commit adds support for the following formats as destination
formats even though the hardware does not support rendering to them:

 - ISL_FORMAT_R24_UNORM_X8_TYPELESS
 - ISL_FORMAT_A4B4G4R4_UNORM
 - ISL_FORMAT_L8_UNORM_SRGB
 - ISL_FORMAT_R9G9B9E5_SHAREDEXP

This is done by using a different format and emitting shader code to
fake it the rest of the way.

Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>

intel/blorp: Include nir_format_convert.h in blorp_blit.c

nir_mask_shift_or is now defined in nir_format_convert.h so we can
delete the copy in blorp_blit.c.

Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>

nir/format_convert: Add a function to pack RGB9_E5 formats

Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>

nir/format_convert: Add pack/unpack for R11F_G11F_B10F

Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>

nir/format_convert: Add linear <-> sRGB helpers

Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>

nir: Add the start of a format conversion helper header

Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>

intel/blorp: Add swizzle support for all hardware

This commit makes blorp capable of swizzling anything even on hardware
that doesn't support texture swizzle.

Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>

intel/isl: Add a helper for inverting swizzles

Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>

intel/isl: Add a helper for composing swizzles

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

intel/isl: Add an isl_swizzle_supports_rendering helper

This helper encodes more details, specifically about Haswell, than the
previous asserts in isl_surface_state.c.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

i965/surface_state: Use an identity swizzle pre-Haswell

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

blorp: Handle the RGB workaround more like other workarounds

The previous version was sort-of strapped on in that it just adjusted
the blit rectangle and trusted in the fact that we would use texelFetch
and round to the nearest integer to ensure that the component positions
matched.  This new version, while slightly more complicated, is more
accurate because all three components end up with exactly the same
dst_pos and so they will get interpolated and sampled at the same
texture coordinate.  This makes the workaround suitable for using with
scaled blits.

Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>

i965: silence unused variable

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Fixes: 2dc29e095f9da ("i965: Don't leak blorp on Gen4-5.")
Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>