Gabe Black [Thu, 6 Dec 2018 02:02:14 +0000 (18:02 -0800)]
systemc: Update test output for longer lived processes.
In the systemc spec, process handles can be invalidated if they have no
children and are terminated. The implementation is not required to do
so however, and for the sake of simplicity gem5 currently does not. To
quote:
"When the underlying process instance terminates, if the process
instance has no surviving children, an implementation may choose to
invalidate any associated process handles, but it is not obliged to do
so."
Two tests have reference output which is affected by this (legal)
difference in behavior. In one case, the test creates new processes
which reuse the names of processes that have been terminated. Since
gem5 doesn't invalidate the old processes, a standard mechanism is
activated which renames the processes to something which is unique.
The other test has this same problem, and also prints the hierarchy
of processes several times during the test. In that hierarchy, the
terminated tests with no live children are still present, where in the
old reference output they've been removed.
This change updates the reference output to match gem5's behavior.
Change-Id: I363448de10080bdce01a4df92f991c67b31a2401
Reviewed-on: https://gem5-review.googlesource.com/c/14919
Reviewed-by: Matthias Jung <jungma@eit.uni-kl.de>
Maintainer: Gabe Black <gabeblack@google.com>
Gabe Black [Wed, 5 Dec 2018 00:30:45 +0000 (16:30 -0800)]
systemc: Update the ordering in the reference output for some tests.
There are a number of cases where systemc leaves the decision of what
order things happen up to the kernel, and any ordering is legal and
conformant with the spec as long as it's repeatable. The reference
outputs reflect a particular choice of ordering which is implementation
specific, and while considerable effort has been made to make the gem5
ordering match the Accellera ordering, at a certain point that's no
longer practical or desirable.
This change manually updates the reference output for the tests that
haven't been excluded for other reasons which have this sort of ordering
problem. They have been individually examined, and as best as I can
tell changing the output this way does not mask any underlying error.
One or two real problems were discovered in addition to the ordering
issues, and those were fixed in earlier changes.
Change-Id: I915269998de3f33d5ab5d1fd754a830fd620184d
Reviewed-on: https://gem5-review.googlesource.com/c/14918
Reviewed-by: Matthias Jung <jungma@eit.uni-kl.de>
Maintainer: Gabe Black <gabeblack@google.com>
Gabe Black [Thu, 6 Dec 2018 01:45:31 +0000 (17:45 -0800)]
systemc: Ignore process control functions on terminated processes.
These functions can descend to the children of a terminated process,
but should have no effect on that process itself.
Change-Id: I6e4bdec8c492dd03d05bc1397aa080e8a51397c1
Reviewed-on: https://gem5-review.googlesource.com/c/14917
Reviewed-by: Matthias Jung <jungma@eit.uni-kl.de>
Maintainer: Gabe Black <gabeblack@google.com>
Gabe Black [Sat, 1 Dec 2018 00:57:02 +0000 (16:57 -0800)]
systemc: Update signals before initing processes.
We were supposed to do one update phase before adding all processes
which didn't have dont_initialize() called to the run queue. We were
doing that in the opposite order.
Change-Id: I6dd4108040d455dc78029da029a2eb5e7af819cb
Reviewed-on: https://gem5-review.googlesource.com/c/14915
Reviewed-by: Matthias Jung <jungma@eit.uni-kl.de>
Maintainer: Gabe Black <gabeblack@google.com>
Giacomo Travaglini [Fri, 7 Dec 2018 11:21:24 +0000 (11:21 +0000)]
base, systemc: Fix clang compilation
This patch is fixing the following issues:
- base: typename should be used only for types
- systemc: 'GCC_VERSION' is not defined for clang
Change-Id: I27c94445d65691a08a0a14a0ffe6b6942f6c455f
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/14976
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Gabe Black <gabeblack@google.com>
Giacomo Travaglini [Fri, 7 Dec 2018 11:05:55 +0000 (11:05 +0000)]
mem: Compile tracePacket only when TRACING_ON is defined
If TRACING_ON is not defined (e.g. when building gem5.fast), clang
compilations will fail reporting an unused function.
Change-Id: I959dba6e9fcf74b951e16365077939ae4d4ef924
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/14975
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
Daniel R. Carvalho [Fri, 7 Dec 2018 09:50:31 +0000 (10:50 +0100)]
mem-cache: Workaround for setWhenReady assertion
Change
174da8e2da6a896d2e97bc264f9c827a0f4c35ac added an assert that
is not satisfiable with current implementation, breaking some
regression tests.
Change-Id: Ibafaf0c51906384364f0b2a4b931f8ec6126d858
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/14955
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
Matteo Andreozzi [Tue, 2 Oct 2018 14:33:28 +0000 (15:33 +0100)]
ext: Remove unused bankwiseMode variable
Apple LLVM version 10.0.0 (clang-1000.11.45.2) complains about
unused members variables
Change-Id: If1f2210c09e80b632cb3688aaa7df0594f9e49c9
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/13228
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Rekai Gonzalez-Alberquilla [Thu, 6 Apr 2017 11:27:20 +0000 (12:27 +0100)]
base: Ported circlebuf to CircularQueue
Ported the existing circlebuf on top of the CircularQueue to condense
shared functionality and minimise code/functionality replication.
Additional contributors: Gabor Dozsa.
Change-Id: Ib4e67c638f0fb66b54cef77007a03439218bda7f
Signed-off-by: Giacomo Gabrielli <giacomo.gabrielli@arm.com>
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/13128
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Rekai Gonzalez-Alberquilla [Wed, 26 Apr 2017 16:44:33 +0000 (17:44 +0100)]
base: Iterable CircularQueue implementation
The former implementation of CircleBuf is functional but a bit too
tailored to match a use-case. This patches introduces a new iterable
circular queue, which adds some more functionality so it can also be
used for the newer LSQ implementation, where iteration and iterators
are a very desirable feature.
Additional contributors: Gabor Dozsa.
Change-Id: I5cfb95c8abc1f5e566a114acdbf23fc52a38ce5e
Signed-off-by: Giacomo Gabrielli <giacomo.gabrielli@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/13127
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Giacomo Travaglini [Mon, 3 Dec 2018 11:37:51 +0000 (11:37 +0000)]
ext: Build googlemock with googletest
googlemock needs to be built together with googletest. This patch
is enabling it by doing the following things
* Moving googletest and googlemock under the same top level directory,
so that we have a single SConscript for building them.
This also matches googletest directory structure:
googletest
|_googletest
|_googlemock
* Adding a shared SConscript which is building gmock and gtest as libgtest
* Removing googletest/SConscript
Change-Id: I88accbdd2e80fb47efaa17819233371fbad6acaa
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Ciro Santilli <ciro.santilli@arm.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/14696
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>
Giacomo Travaglini [Wed, 14 Nov 2018 18:41:19 +0000 (18:41 +0000)]
ext: Import googlemock, release version 1.8.0
gtest 1.8.0 is already part of gem5; this patch adds a matching gmock
so that it is possible to create Mocks in gem5 unit tests.
Please note: the commit is just importing the source code as it is
without adding any SConscript; it is hence unbuildable at the moment.
Next commits will integrate the mocking framework into the gem5
build system
Change-Id: Iaf05ad91b1964aac7ea37085f839027a8d34ba3e
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Ciro Santilli <ciro.santilli@arm.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/14695
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com>
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>
Tony Gutierrez [Fri, 30 Nov 2018 17:19:21 +0000 (12:19 -0500)]
arch-x86: Add sys/syscall.h to x86 process.cc/syscall_emul.cc
Change
a66d12c guards the selection of getdents()
in x86's process.cc file with SYS_getdents, however
process.cc does not include the right header for
SYS_getdents, which leads to x86 choosing the
unimplemented call. This change adds sys/syscall.h to
address the problem.
This change also adds sys/syscall.hh to syscall_emu.cc,
which only includes syscall.hh and may not be supported on
all systems.
Change-Id: If1adcf41e9e455de5f2827ba98c542fdcacdc22e
Reviewed-on: https://gem5-review.googlesource.com/c/14775
Reviewed-by: Ciro Santilli <ciro.santilli@arm.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Brandon Potter <Brandon.Potter@amd.com>
Daniel R. Carvalho [Wed, 5 Dec 2018 14:06:56 +0000 (15:06 +0100)]
mem-cache: Remove writebacks parameter from serviceMSHRTargets
Change
8ba77ae8fc98a355082da2bd9fdc6ecf4928f725 introduced the
writebacks parameter, but it was never used.
Change-Id: I225e5b399de42d77c72fc0012d3dc93ef39b8853
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/14896
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
Daniel R. Carvalho [Wed, 28 Nov 2018 12:54:42 +0000 (13:54 +0100)]
mem-cache: Add getter and setter to CacheBlk::whenReady
Add a getter and a setter function to access CacheBlk::whenReady
to encapsulate the variable and allow error checking. This error
checking consists on verifying that writes to a block after it
has been inserted follow a chronological order.
As a side effect, tickInserted retain its value until updated,
that is, it is not reset in invalidate().
Change-Id: Idc3c5a99c3f002ee9acc2424f00e554877fd3a69
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/14715
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
Nikos Nikoleris [Sat, 1 Dec 2018 14:52:23 +0000 (14:52 +0000)]
base: Fix fiber compilation issue for Mac OS
Mac OS has deprecated the use of ucontext and at the moment we are
using a workaround to enable it. A side-effect is that the code is
marked as _POSIX_C_SOURCE and consequently <sys/mman.h> requires the
code to be also marked as _DARWIN_C_SOURCE to include the definition
of MAP_ANONYMOUS.
Change-Id: I65550d11a0a21cd36d832a7de6320e7e3f332a9d
Signed-off-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/14817
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>
Nikos Nikoleris [Wed, 28 Nov 2018 08:16:33 +0000 (08:16 +0000)]
base, sim: Add missing destructors
Derived classes with virtual functions need to define a virtual
destructor or a protected destructor otherwise calling the base class
destructor has undefined behavior. This change adds a virtual
distructor in the base class.
Change-Id: I1c855aa56dff6585ff99b9147bdb4eb9729a0a53
Signed-off-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/14815
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Giacomo Gabrielli [Mon, 22 Oct 2018 16:21:45 +0000 (17:21 +0100)]
base: Add type alias for raw pointer in RefCountingPtr
Change-Id: Ied2204566a8fc5c34fb4702301051b8e5ab84ffe
Signed-off-by: Giacomo Gabrielli <giacomo.gabrielli@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/13717
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Daniel R. Carvalho [Thu, 25 Oct 2018 15:52:26 +0000 (17:52 +0200)]
mem-cache: Optimize sector valid and secure check
Previously a loop was being done to check whether the
block was valid/secure or not. Variables have been
added to skip this loop and save and update sector
block state when sub-blocks are validated, invalidated
and secured.
Change-Id: Ie1734f7dfda9698c7bf22a1fcbfc47ffb9239cea
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/14363
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Rekai Gonzalez-Alberquilla [Wed, 1 Mar 2017 13:49:08 +0000 (13:49 +0000)]
cpu: Change raw pointers to STL Containers
This patch changes two members from being raw pointers to being STL
containers. The reason behind, other than cleanlyness and arguable OO
best practices is that containers have more intronspections capabilities
than naked pointers do, as the size is known.
Using STL containers adds little overhead and eases the automation of
process during debugging (gdb).
Change-Id: I4d9d3eedafa8b5e50ac512ea93b458a4200229f2
Signed-off-by: Giacomo Gabrielli <giacomo.gabrielli@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/13126
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Ciro Santilli [Thu, 15 Nov 2018 00:00:00 +0000 (00:00 +0000)]
arch-arm: correctly set floats from GDB on aarch64
aarch64 floating point registers are now stored as vector type, but this
was not updated in the stub.
Change-Id: I4a2bc1cea0eec9beeb5bbd49e2a868b9d5ed0a42
Reviewed-on: https://gem5-review.googlesource.com/c/14498
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Ciro Santilli [Wed, 14 Nov 2018 00:00:01 +0000 (00:00 +0000)]
base: increase the GDB buffer size dynamically
The size was not large enough for the 'G' packet on aarch64, which the
client sends to set registers.
This would lead to the stub not to be able to find the end of the input
packet and keep waiting forever.
Change-Id: Icb149f15a6c769371ebcb6ec5fbebc6170c31fc6
Reviewed-on: https://gem5-review.googlesource.com/c/14497
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>
Ciro Santilli [Wed, 14 Nov 2018 00:00:00 +0000 (00:00 +0000)]
arch-arm: only change the pc address when GDB registers are set
The entire pcState was being reset, which made the simulation incorrectly
switch to aarch32 from aarch64.
Change-Id: I9ba7dd0ed95bc6120d94393bba272e0cb8c081c5
Reviewed-on: https://gem5-review.googlesource.com/c/14496
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Ciro Santilli [Wed, 18 Jul 2018 17:00:51 +0000 (18:00 +0100)]
arch-arm: fix the aarch64 GDB stub
The main change is to remove vector registers from the GDB stub.
Those registers were intended for SVE, which is a new architecture feature
and not yet treated by default on the GDB present in Ubuntu 18.04, and
possibly not even on GDB master.
As a result, aarch64 GDB stub connections would fail with:
Remote 'g' packet reply is too long
The correct way to support those registers is to send XML GDB target
description files to the client. This feature is not yet available for
any architecture, and should be implemented in future patches.
Other smaller fixes are:
* cpsr is uint32_t in aarch64 as well as arm
* use M5_ATTR_PACKED on the register structs since they are being cast and
sent as byte arrays
Change-Id: I77cd8a98e322ecc60799e5b11fe5cd414d893cc7
Reviewed-on: https://gem5-review.googlesource.com/c/14495
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Gabe Black [Fri, 30 Nov 2018 01:33:46 +0000 (17:33 -0800)]
systemc: Disable systemc when using gcc versions older than 5.0.
These versions don't support the std::put_time function. Since versions
of gcc older than 5.0 aren't going to be supported at all in the fairly
near future, this should only be temporary. The number of people using
both systemc and older versions of gcc should be very small, or even
zero.
Change-Id: Ie9572fdf83ba9569df6bc0457c98d86565dcdcd8
Reviewed-on: https://gem5-review.googlesource.com/c/14755
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Gabe Black <gabeblack@google.com>
Gabe Black [Thu, 29 Nov 2018 01:40:17 +0000 (17:40 -0800)]
base: Change the unit test binary names to use .test, and to be consistent.
Most tests were named *test where * was the base name of the file being
tested, but some were named differently based on, for instance, the
name of the class that file implemented.
This change makes all the test names consistently based off of the file
name they test, and also brings in the new .test convention to make
them easier to read.
Now, if you have a file like fiber.cc you want to test, you'd have a
unit test in a file called fiber.test.cc, and a test called fiber.test
which would generate a binary called fiber.test.opt, fiber.test.debug,
etc.
Change-Id: I61d59016090371a9bae72066e7473a34aecea21f
Reviewed-on: https://gem5-review.googlesource.com/c/14677
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Gabe Black <gabeblack@google.com>
Gabe Black [Thu, 29 Nov 2018 01:36:28 +0000 (17:36 -0800)]
base: Rename unit test cc files to be *.test.cc.
This makes the name easier to read, looks ok if the file is named with
underscores between words or not, is easy to grep for, and shouldn't
introduce any ambiguities in the file names.
Change-Id: I34b7bcccea2d87c10c0de417dd5e3ef27c4b5666
Reviewed-on: https://gem5-review.googlesource.com/c/14676
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Maintainer: Gabe Black <gabeblack@google.com>
Gabe Black [Tue, 27 Nov 2018 03:18:26 +0000 (19:18 -0800)]
util: Add the scons configuration cache to .gitignore for util/tlm.
Change-Id: Ife31e1bbf862d10bbe8e2c0fa36c8c168cfafa84
Reviewed-on: https://gem5-review.googlesource.com/c/14656
Reviewed-by: Matthias Jung <jungma@eit.uni-kl.de>
Maintainer: Gabe Black <gabeblack@google.com>
Gabe Black [Thu, 22 Nov 2018 01:59:16 +0000 (17:59 -0800)]
systemc: Update the gem5-within-systemc README to mention USE_SYSTEMC.
When linking with an external systemc host, the native gem5 systemc API
should be disabled to avoid linking conflicts.
Change-Id: If7f9b3718fcdbdab5ebc9ef52e746f6bf9f2fb9c
Reviewed-on: https://gem5-review.googlesource.com/c/14520
Reviewed-by: Matthias Jung <jungma@eit.uni-kl.de>
Maintainer: Gabe Black <gabeblack@google.com>
Gabe Black [Thu, 29 Nov 2018 01:34:33 +0000 (17:34 -0800)]
base: Fix include order in the inifile unit test.
Even though gtest.h is a C++ header, it looks like a C header which
makes the style check hook upset. Lets move it up so the hook doesn't
complain when the file is changed.
Change-Id: Ibcc2d0b7bf3b254c70e55b30379ebd4b70933c26
Reviewed-on: https://gem5-review.googlesource.com/c/14675
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Gabe Black [Thu, 22 Nov 2018 01:51:46 +0000 (17:51 -0800)]
systemc: Run the systemc tests directly from their build directories.
We were previously running them from the current directory to start
with, and then having the config script switch to the build directory.
That worked, except when output streams might be opened as part of the
global constructors which would run before the config script.
This change makes us start from the build directory directly, making
the switch in the config script unnecessary and ensuring that no files
leak outside of the build when running tests.
Change-Id: I484168793bfc5abc4e5631fb3468733fb9d829af
Reviewed-on: https://gem5-review.googlesource.com/c/14519
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>
Gabe Black [Thu, 22 Nov 2018 01:35:28 +0000 (17:35 -0800)]
systemc: Run the systemc tests with the CWD in the build directory.
This will prevent some (but not all) output files the tests generate
from ending up outside the build directory. Because some output file
streams are constructed as global objects, their paths are resolved
relative to the CWD when gem5 starts, before the config script has a
chance to change it.
Subsequent changes will make verify.py should make gem5 start with the
correct working directory, cleaning up the remaining leaking files.
Change-Id: I75a1256719dab4c98ab868c209d09b9dcdabb458
Reviewed-on: https://gem5-review.googlesource.com/c/14518
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>
Gabe Black [Thu, 22 Nov 2018 01:34:36 +0000 (17:34 -0800)]
systemc: Add DEPS files for some tests with non-source file dependencies.
This ensures that those files will be available when running the test
relative to its build directory.
Change-Id: If775ca328b3e1165baa968e4b39c36db0172837c
Reviewed-on: https://gem5-review.googlesource.com/c/14517
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>
Gabe Black [Thu, 22 Nov 2018 00:59:32 +0000 (16:59 -0800)]
systemc: Make verify.py recognize a DEPS file in test dirs.
This file lists additional files beyond the sources that the test
relies on, like files it uses when running.
Change-Id: Ifc4958b26eed08689e0e72bd87f84388dbcf1898
Reviewed-on: https://gem5-review.googlesource.com/c/14516
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>
Nikos Nikoleris [Wed, 28 Nov 2018 08:00:57 +0000 (08:00 +0000)]
base: Add missing overrides in statistics header
Change-Id: Id5ee2a970a3dceee1b7e24ce3b452b7fece87875
Signed-off-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/14619
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Nikos Nikoleris [Wed, 28 Nov 2018 07:58:32 +0000 (07:58 +0000)]
arch-arm: Add missing template declaration
The lack of a template declaration for IllegalInstSetStateFault was
causing errors when compiling with clang.
Change-Id: If7f19d7e879330226c80df2baca73d88d818f673
Signed-off-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/14618
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Pau Cabre [Thu, 22 Nov 2018 13:48:30 +0000 (14:48 +0100)]
cpu: Added new stats to TAGE and LTAGE branch predictors
They are basically used to tell wich component of the predictor is
providing the prediction and whether it is correct or wrong
Change-Id: I7b3db66535f159091f1b37d70c2d942d50b20fb2
Signed-off-by: Pau Cabre <pau.cabre@metempsy.com>
Reviewed-on: https://gem5-review.googlesource.com/c/14535
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Pau Cabre [Tue, 20 Nov 2018 00:04:56 +0000 (01:04 +0100)]
cpu: split LTAGE implementation into a base TAGE and a derived LTAGE
The new derived LTAGE is equivalent to the original LTAGE implementation
The default values of the TAGE branch predictor match the settings of the
8C-TAGE configuration described in https://www.jilp.org/vol8/v8paper1.pdf
Change-Id: I8323adbfd5c9a45db23cfff234218280e639f9ed
Signed-off-by: Pau Cabre <pau.cabre@metempsy.com>
Reviewed-on: https://gem5-review.googlesource.com/c/14435
Reviewed-by: Sudhanshu Jha <sudhanshu.jha@arm.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Rekai Gonzalez-Alberquilla [Fri, 10 Feb 2017 17:30:22 +0000 (17:30 +0000)]
cpu,arch-arm: Initialise data members
The value that is not initialized has a bogus value that manifests when
using some debug-flags what makes the usage of tracediff a bit more
challenging.
In addition, while debugging with other techniques, it introduces the
problem of understanding if the value of a field is 'intended' or just
an effect of the lack of initialisation.
Change-Id: Ied88caa77479c6f1d5166d80d1a1a057503cb106
Signed-off-by: Giacomo Gabrielli <giacomo.gabrielli@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/13125
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Matteo Andreozzi [Mon, 26 Feb 2018 16:40:12 +0000 (10:40 -0600)]
arch-arm: clang compilation fixes
Fix 1: std::pair constructor is not a constexpr in clang implementation
Fix 2: static const templates need to be defined in their
translation unit
Change-Id: I3d9b9b47e1d148e44555f40e2e2aeff06707ff8f
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/14617
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Giacomo Travaglini [Thu, 22 Nov 2018 15:09:04 +0000 (15:09 +0000)]
tests: Convert IniFile unit test to a GTest
Change-Id: I47d6c9cbae21877420a15ffcf8489e3c26959139
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/14615
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>
Gabe Black [Tue, 27 Nov 2018 03:12:52 +0000 (19:12 -0800)]
hsail: Fix a warning/build failure for HSAIL_X86.
The Bitselect operation definition used ~ to invert the bits of a mask
value, but if that mask value is of type bool, that generates a
warning. This change casts that value to a uint64_t so that it can
always have ~ applied to it.
Change-Id: I7fbfc6ff264bc32a265f2724c772b8fae08590f7
Reviewed-on: https://gem5-review.googlesource.com/c/14655
Reviewed-by: Brandon Potter <Brandon.Potter@amd.com>
Maintainer: Gabe Black <gabeblack@google.com>
Gabe Black [Tue, 27 Nov 2018 01:51:16 +0000 (17:51 -0800)]
arch, base, cpu, gpu, mem: Replace assert(0 or false with panic.
Neither assert(0) nor assert(false) give any hint as to why control
getting to them is bad, and their more descriptive versions,
assert(0 && "description") and assert(false && "description"), jury
rig assert to add an error message when the utility function panic()
already does that directly with better formatting options.
This change replaces that flavor of call to assert with panic, except
in the actual code which processes the formatting that panic uses (to
avoid infinitely recurring error handling), and in some *.sm files
since I don't know what rules those have to follow and don't want to
accidentaly break them.
Change-Id: I8addfbfaf77eaed94ec8191f2ae4efb477cefdd0
Reviewed-on: https://gem5-review.googlesource.com/c/14636
Reviewed-by: Brandon Potter <Brandon.Potter@amd.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Ciro Santilli [Tue, 20 Nov 2018 16:45:07 +0000 (16:45 +0000)]
sim-se: only implement getdentsFunc on supported hosts
The implementation of the getdents syscall relies on SYS_getdents, which
is not available on all archs, because the getdents syscall has been
superseded by getdents64, and does not exist on newer archs such as
aarch64.
This leads the build to break on aarch64 hosts with error:
error: 'SYS_getdents' was not declared in this scope
Change-Id: I8701fb5b61c0418b14a9463ef135a391a7f7a9ba
Reviewed-on: https://gem5-review.googlesource.com/c/14596
Reviewed-by: Brandon Potter <Brandon.Potter@amd.com>
Maintainer: Brandon Potter <Brandon.Potter@amd.com>
Ciro Santilli [Wed, 21 Nov 2018 16:27:28 +0000 (16:27 +0000)]
systemc: set endianess to fix build for ARM host
ARM architectures were not covered in the endianess #if cases, which
lead the build to fail on an arm host with message:
error The file boost/detail/endian.hpp needs to be set up for your CPU
type.
Change-Id: Id012cf37810da113174a51746e290e25138739cb
Reviewed-on: https://gem5-review.googlesource.com/c/14595
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>
Gabe Black [Tue, 20 Nov 2018 00:06:03 +0000 (16:06 -0800)]
base: Add some functions to convert floats to bits and vice versa.
These make it easier to extract the binary representation of floats and
doubles, and given a binary representation convert it back again.
The versions with a size prefix are safer to use since they make it
clear what size inputs/outputs are expected. The versions without are
to make writing generic code easier in case the same code snippet,
templated function, etc., needs to be applied in both circumstances.
Change-Id: Ib1f35a7e88e00806a7c639c211c5699b4af5a472
Reviewed-on: https://gem5-review.googlesource.com/c/14455
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Gabe Black <gabeblack@google.com>
Daniel R. Carvalho [Thu, 25 Oct 2018 15:26:02 +0000 (17:26 +0200)]
mem-cache: Add setters to validate and secure block
In order to allow polymorphism of the block these two
functions have been added, and all direct status
assignments to these bits have been substituted.
We also assert that the block has been invalidated
before insertion. Then the block is validated in
the insertion.
Change-Id: Ie7be42408721ad4c2c9dc880f82a62cb594f8668
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/14362
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
Pau Cabre [Sun, 18 Nov 2018 01:40:13 +0000 (02:40 +0100)]
cpu: Made LTAGE parameters configurable
This includes TAGE tag sizes, TAGE table sizes, U counters reset period,
loop predictor associativity, path history size, the USE_ALT_ON_NA size
and the WITHLOOP size
Change-Id: I935823f0a5794f5d55b744263798897a813dc1bd
Signed-off-by: Pau Cabre <pau.cabre@metempsy.com>
Reviewed-on: https://gem5-review.googlesource.com/c/14417
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Pau Cabre [Sat, 17 Nov 2018 22:21:15 +0000 (23:21 +0100)]
cpu: Fixed useful counter handling in LTAGE
Increased to 2 bits of useful counter per TAGE entry as described in the
LTAGE paper (and made the size configurable)
Changed how the useful counters are incremented/decremented as described
in the LTAGE paper
Change-Id: I8c692cc7c180d29897cb77781681ff498a1d16c8
Signed-off-by: Pau Cabre <pau.cabre@metempsy.com>
Reviewed-on: https://gem5-review.googlesource.com/c/14215
Reviewed-by: Ilias Vougioukas <ilias.vougioukas@arm.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Pau Cabre [Sun, 11 Nov 2018 22:43:33 +0000 (23:43 +0100)]
cpu: Fixes on the loop predictor part of LTAGE
Fixed the following fields of the loop predictor entries as described on
the LTAGE paper:
- Age counter (it was 3 bits and it should be 8 bits)
- Tag (it was 16 bits and it should be 14 bits). Also some times it used
int variables and some times uint16_t, leading to wrong behaviour
- Confidence counter (it was 2 bits ins some parts of the code and 3 bits
in some other parts. It should be 2 bits)
- Iteration counters (they were 16 bits and they should be 14 bits)
All the new sizes are now configurable
Change-Id: I8884c7454c1e510b65160eb4d5749d3259d34096
Signed-off-by: Pau Cabre <pau.cabre@metempsy.com>
Reviewed-on: https://gem5-review.googlesource.com/c/14216
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Gabe Black [Wed, 21 Nov 2018 00:22:26 +0000 (16:22 -0800)]
x86: Get rid of a problematic DPRINTF in PremFp.
This DPRINTF shouldn't be necessary since it shows the operands and
results of the instruction which the trace should already make
available. Also by passing the destination register to DPRINTF, the ISA
parser will assume that it's also a source when tracking dependencies.
Change-Id: I820387c82578bdbb8d2e3d91652a6c0185077f54
Reviewed-on: https://gem5-review.googlesource.com/c/14475
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Gabe Black <gabeblack@google.com>
Gabe Black [Sat, 17 Nov 2018 00:27:58 +0000 (16:27 -0800)]
sim: Deschedule existing events when destructing an event queue.
Other objects in the simulation may try to deschedule their events when
destructed, and if they're cleaned up after the event queue is then
they might try to deschedule events on an event queue that no longer
exists.
Change-Id: I9452ce52fba78297ce3dc4b3884289b5e2f2574d
Reviewed-on: https://gem5-review.googlesource.com/c/14400
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Gabe Black <gabeblack@google.com>
Gabe Black [Sat, 17 Nov 2018 01:57:41 +0000 (17:57 -0800)]
base: Don't let exceptions leak from the to_number utility function.
This function catches a couple types of exceptions the functions it
calls might throw, but if one that it doesn't catch is thrown, then
it will propogate that exception to its own callers, and not initialize
the value it was asked to convert.
This might be considered desirable behavior since it lets errors
propogate and avoids handling them in code that might not know the
context of when it's called. On the other hand, it upsets g++ since it
thinks that there might be an uninitialized value used elsewhere, even
though that value will only be uninitialized if an exception is
propogating, and the code that would use it is after a point where that
exception would have been caught and execution would have resumed.
To satisfy g++ and to also avoid silently hiding errors, this change
adds a catch all which will panic if an unexpected exception is raised.
Change-Id: Ie94dcef3a50f7902566328a3fa2eac59b3cf9aad
Reviewed-on: https://gem5-review.googlesource.com/c/14399
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Gabe Black [Fri, 9 Nov 2018 00:16:10 +0000 (16:16 -0800)]
systemc: Stop explicitly adding the systemc ext dir to CPPPATH.
That's now handled automatically when the native systemc API is
enabled.
Change-Id: If1f88929af335a40554a9fd8df6f68aa1a4c0ba4
Reviewed-on: https://gem5-review.googlesource.com/c/14398
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Gabe Black <gabeblack@google.com>
Gabe Black [Thu, 8 Nov 2018 23:49:03 +0000 (15:49 -0800)]
systemc: Put systemc headers in the include path when supported.
When the native systemc API support is built in, put the systemc and
systemc.h header files in the include path so they can be used as
normal. We don't want any external systemc headers being included and
getting mixed in with our local ones.
Change-Id: I5fc01ff5f069cfadb7c19a9dead13e7ce7272976
Reviewed-on: https://gem5-review.googlesource.com/c/14397
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Gabe Black <gabeblack@google.com>
Gabe Black [Sat, 17 Nov 2018 02:01:30 +0000 (18:01 -0800)]
systemc: Increase the stack size for the sc_main fiber to 8MB.
This is a reasonable size for a stack, and the default size for a stack
on Linux as determined by some quick Googling. The sc_main fiber would
normally use the primary program stack if run under the standard
systemc implementation, and so might expect to have more room to play
with.
Change-Id: Ie12344939e7b249da203630ebc7dc773a387d716
Reviewed-on: https://gem5-review.googlesource.com/c/14396
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Gabe Black <gabeblack@google.com>
Gabe Black [Sat, 17 Nov 2018 01:07:42 +0000 (17:07 -0800)]
base: Set up a guard page for fiber stacks.
This will help detect stack overflow for fibers.
Change-Id: Iff2b102120ec351709e495291d6bead597f8d10c
Reviewed-on: https://gem5-review.googlesource.com/c/14395
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Maintainer: Gabe Black <gabeblack@google.com>
Javier Bueno [Sat, 17 Nov 2018 23:59:09 +0000 (00:59 +0100)]
mem-cache: a missing cast was truncating addresses
High bits were truncated when computing the block address
Change-Id: Iab2a4c6063ece2d1d4c24ce5686045a6d6d35434
Reviewed-on: https://gem5-review.googlesource.com/c/14415
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
Pau Cabre [Fri, 9 Nov 2018 23:12:30 +0000 (00:12 +0100)]
cpu: Fix LTAGE max number of allocations on update
The LTAGE paper states that only one TAGE entry can be
allocated when updating
Change-Id: I6cfb4d80ce835e93d4bf5099ef88a7d425abaddd
Signed-off-by: Pau Cabre <pau.cabre@metempsy.com>
Reviewed-on: https://gem5-review.googlesource.com/c/14195
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Ilias Vougioukas <ilias.vougioukas@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Pau Cabre [Wed, 7 Nov 2018 22:22:05 +0000 (23:22 +0100)]
configs: Added an option for choosing branch predictor type
Added the parameter "--bp-type" to set the branch predictor type
Added the parameter "--list-bp-types" to list all the available branch
predictor types
Change-Id: Ia6aae90c784aef359b6d8233c8383cd7a871aca1
Signed-off-by: Pau Cabre <pau.cabre@metempsy.com>
Reviewed-on: https://gem5-review.googlesource.com/c/14015
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Srikant Bharadwaj [Fri, 16 Nov 2018 19:24:43 +0000 (14:24 -0500)]
sim: Fix data type of ticks per second before passing it to C++
Casts ticks per second value to int before passing it to C++. Python
throws an error because of incompatible type because of the recent
change.
Change-Id: Ibcaf8c327f1be0dba38763975d389584addd8373
Reviewed-on: https://gem5-review.googlesource.com/c/14375
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>
Matteo Andreozzi [Wed, 7 Sep 2016 13:04:45 +0000 (14:04 +0100)]
mem: avoid calling regStat twice on a QoSPolicy
Change-Id: I216c57073fabe29c3f898a5d89cee41efd4277d5
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/13696
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
Rekai Gonzalez-Alberquilla [Mon, 6 Feb 2017 11:10:06 +0000 (11:10 +0000)]
cpu: Fix the usage of const DynInstPtr
Summary: Usage of const DynInstPtr& when possible and introduction of
move operators to RefCountingPtr.
In many places, scoped references to dynamic instructions do a copy of
the DynInstPtr when a reference would do. This is detrimental to
performance. On top of that, in case there is a need for reference
tracking for debugging, the redundant copies make the process much more
painful than it already is.
Also, from the theoretical point of view, a function/method that
defines a convenience name to access an instruction should not be
considered an owner of the data, i.e., doing a copy and not a reference
is not justified.
On a related topic, C++11 introduces move semantics, and those are
useful when, for example, there is a class modelling a HW structure that
contains a list, and has a getHeadOfList function, to prevent doing a
copy to an internal variable -> update pointer, remove from the list ->
update pointer, return value making a copy to the assined variable ->
update pointer, destroy the returned value -> update pointer.
Change-Id: I3bb46c20ef23b6873b469fd22befb251ac44d2f6
Signed-off-by: Giacomo Gabrielli <giacomo.gabrielli@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/13105
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Javier Bueno [Thu, 15 Nov 2018 15:19:45 +0000 (16:19 +0100)]
mem-cache: fix invalid iterator access
An iterator was assigned end() and then it was used to access
its corresponding element.
Change-Id: I87246cf56cbc694dd6b4e2cabbe84a08429d2ac3
Reviewed-on: https://gem5-review.googlesource.com/c/14361
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
Daniel [Sun, 11 Nov 2018 14:52:08 +0000 (15:52 +0100)]
mem-cache: Make StridePrefetcher use Replacement Policies
Previously StridePrefetcher was only able to use random
replacement policy. This change allows all replacement
policies to be applied to the pc table.
Change-Id: I8714e71a6a4c9c31fbca49a07a456dcacd3e402c
Signed-off-by: Daniel <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/14360
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
Daniel [Sun, 11 Nov 2018 16:56:08 +0000 (17:56 +0100)]
mem-cache: Add invalidation function to StrideEntry
Add invalidation function to StrideEntry so that every
entry can be invalidated appropriately.
Change-Id: I38c42b7d7c93d839f797d116f1d2c88572123c0e
Signed-off-by: Daniel <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/14359
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
Daniel [Sun, 11 Nov 2018 15:11:40 +0000 (16:11 +0100)]
mem-cache: Make PCTable context independent
Move the unordered_map outside of the PCTable, as it
belongs to the StridePrefetcher. By doing so we are
moving towards a table that ressembles the ones of
the Tags classes.
Some functions have been moved from the prefetcher to
the PCTable, as they didn't belong there. As such, they
have been renamed to remove the unnecessary prefix.
Change-Id: I3e54bc7dee65e1f78d96b0d548ac8345b7bd4364
Signed-off-by: Daniel <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/14358
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
Daniel [Tue, 13 Nov 2018 19:47:51 +0000 (20:47 +0100)]
mem-cache: Vectorize StridePrefetcher's entries.
Turn StridePrefetcher::PCTable::entries into a vector of vectors.
Change-Id: I2a4589a76eb205910c43723638b7989eddd5ca24
Reviewed-on: https://gem5-review.googlesource.com/c/14357
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
Daniel [Tue, 13 Nov 2018 19:59:50 +0000 (20:59 +0100)]
mem-cache: Return entry in StridePrefetcher::pcTableHit()
Return a pointer to the entry instead of returning a
boolean and passing a pointer reference. As a side
effect, change the name of the function to be more
descriptive of the functionality.
Change-Id: Iad44979e98031754c1d0857b1790c0eaf77e9765
Signed-off-by: Daniel <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/14356
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
Daniel [Sun, 11 Nov 2018 10:55:37 +0000 (11:55 +0100)]
mem-cache: Cleanup prefetchers
Prefetcher code had extra variables, dependencies
that could be removed, code duplication, and missing
overrides.
Change-Id: I6e9fbf67a0bdab7eb591893039e088261f52d31a
Signed-off-by: Daniel <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/14355
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
Ciro Santilli [Wed, 7 Nov 2018 00:00:00 +0000 (00:00 +0000)]
scons: add --gold-linker to link with the gold linker
This option can significantly speedup link time on Linux systems, which is
the main bottleneck to rebuild after small changes.
Change-Id: I3b0bdd61f7dcef0d73629c8ee2ee98091953fec3
Reviewed-on: https://gem5-review.googlesource.com/c/14075
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Gabe Black <gabeblack@google.com>
Pau Cabre [Thu, 8 Nov 2018 23:30:15 +0000 (00:30 +0100)]
cpu: Fixed ratio of pred to hyst bits for LTAGE Bimodal
The LTAGE paper states 1 hyst bit shared for 4 pred bits.
Made this ratio configurable use 4 by default.
Also changed the Bimodal structure to use two std::vector<bool> (one for
pred and one for hyst bits)
Change-Id: I6793e8e358be01b75b8fd181ddad50f259862d79
Signed-off-by: Pau Cabre <pau.cabre@metempsy.com>
Reviewed-on: https://gem5-review.googlesource.com/c/14120
Reviewed-by: Ilias Vougioukas <ilias.vougioukas@arm.com>
Reviewed-by: Sudhanshu Jha <sudhanshu.jha@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Daniel R. Carvalho [Wed, 14 Nov 2018 11:04:38 +0000 (12:04 +0100)]
mem-cache: Remove Cache dependency from Tags
Tags do not need to be aware of caches.
Change-Id: Ib6a082b74dcd9b2f10852651634b59512732fb2a
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/14296
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
Daniel R. Carvalho [Thu, 18 Oct 2018 13:31:51 +0000 (15:31 +0200)]
mem-cache: Move access latency calculation to Cache
Access latency was not being calculated properly, as it was
always assuming that for hits reads take as long as writes,
and that parallel accesses would produce the same latency
for read and write misses.
By moving the calculation to the Cache we can use the write/
read information, reduce latency variables duplication and
remove Cache dependency from Tags.
The tag lookup latency is still calculated by the Tags.
Change-Id: I71bc68fb5c3515b372c3bf002d61b6f048a45540
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/13697
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
Giacomo Travaglini [Mon, 12 Nov 2018 16:46:52 +0000 (16:46 +0000)]
arch-arm: Print register name when warning on AT instructions
With this patch we don't print anymore the enum value when warning
on any AT instruction usage, but we print the sys reg name instead
Change-Id: Ic6831b98ad6b0582be69883dc9519a9d3324da30
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Anouk Van Laer <anouk.vanlaer@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/14316
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Javier Bueno [Fri, 9 Nov 2018 15:02:04 +0000 (16:02 +0100)]
mem-cache: implement a probe-based interface
The HW Prefetcher of a cache can now listen events
from their associated CPUs and from its own cache.
Change-Id: I28aecd8faf8ed44be94464d84485bd1cea2efae3
Reviewed-on: https://gem5-review.googlesource.com/c/14155
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
Giacomo Travaglini [Wed, 17 Oct 2018 17:08:30 +0000 (18:08 +0100)]
sim: Move BitUnion overloading to show/parseParams
This patch is moving template overloading for BitUnions into the
showParam, parseParams functions. Henceforth BitUnion types will use the
common param wrapper.
This patch implicitly implements (UN)SERIALIZE_CONTAINER for BitUnions.
Change-Id: I0e1faadb4afd4dc9de5dc5fca40041e349c9ba73
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/13636
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Giacomo Travaglini [Wed, 17 Oct 2018 16:17:48 +0000 (17:17 +0100)]
sim: Move paramIn/Out definition to header file
This patch is moving the definitions of paramIn/Out templates to
the header file. In this way we gain:
1) We don't have to do explicit instantiation anymore for user defined
types. This spares us from including data type header files into
serialize.cc
2) We can overload show/parseParam for BitUnions or any other type
that requires special handling when serializing. Just by overloading
the two templates we get all the containers' (list, vector, array..)
serialization for free
2) gtest: With the idea of adding unit tests for Serializable objects,
we can avoid importing serialize.cc and just redefine Serializable
methods in the test source, implementing a Serializable stub
Change-Id: I45a9bb87d5ef886a3668fd477005cd105f612e36
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/13635
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Pau Cabre [Wed, 7 Nov 2018 22:32:55 +0000 (23:32 +0100)]
cpu: Fixed PC shifting on LTAGE branch predictor
The PC needs to be shifted according to the instShiftAmt parameter
Change-Id: I272619c093695b56cf7f8ff7163e3b5d23205d16
Signed-off-by: Pau Cabre <pau.cabre@metempsy.com>
Reviewed-on: https://gem5-review.googlesource.com/c/14035
Reviewed-by: Sudhanshu Jha <sudhanshu.jha@arm.com>
Reviewed-by: Ilias Vougioukas <ilias.vougioukas@arm.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Nikos Nikoleris [Tue, 6 Nov 2018 11:24:01 +0000 (11:24 +0000)]
mem-cache: Align how we handle requests in atomic with timing
Requests, for which a cache has already committed to respond do not
perform any lookups. Previously in atomic mode the packet would pay
the lookup latency while in timing it wouldn't. This patch aligns
recvAtomic with recvTimingReq and removes the lookup latency from the
the handling of such requests.
Change-Id: I50a0631f8058e5086d94d55af0e1788a60e2883f
Signed-off-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/14175
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Giacomo Travaglini [Fri, 9 Nov 2018 09:18:13 +0000 (09:18 +0000)]
systemc: Push python headers on top of sources
Some build failures has been seen after USE_SYSTEMC being True by
default and that has been caused by double definition of _XOPEN_SOURCE
and _POSIX_C_SOURCE in some python versions (like 2.7.5, 2.7.13) and
/usr/include/features.h (used by gcc)
Python definition should preceed features.h one, since the latter will
manually #undef them before #define them.
Change-Id: I774711aaf8145df9ad7677a393a60cf3662d6816
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/14095
Maintainer: Gabe Black <gabeblack@google.com>
Gabe Black [Thu, 8 Nov 2018 01:56:54 +0000 (17:56 -0800)]
systemc: Stop using python to set/manage the global time resolution.
Now that that's managed in c++, we can do that directly without having
to depend on the python code being available, the code which lets us
call from c++ to python, or for the embedded python interpretter to
have started running and have loaded the appropriate modules.
Change-Id: Ied110d8f22181095f8c0c645636a9bd67964263e
Reviewed-on: https://gem5-review.googlesource.com/c/14056
Maintainer: Gabe Black <gabeblack@google.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Gabe Black [Thu, 8 Nov 2018 01:34:11 +0000 (17:34 -0800)]
sim: Push the global frequency management code into C++.
That makes it available when python is left out, and makes it available
to c++ code without having to call back into python.
Change-Id: If82e7e8eff526f2b957f84afe046e1d56fed4aa2
Reviewed-on: https://gem5-review.googlesource.com/c/14055
Reviewed-by: Srikant Bharadwaj <srikant.bharadwaj@amd.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Nikos Nikoleris [Thu, 4 Oct 2018 15:15:52 +0000 (16:15 +0100)]
configs: Revamp ruby mem test to align with MemTest
The test script was broken as it was based on an older version of
MemTest, this changes revamps the creation of MemTest and removes
parameters that are not any longer valid.
Change-Id: Ib87369c1e4717c2da23e8108c72eec871e56f6ed
Signed-off-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/13596
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Gabe Black [Fri, 9 Nov 2018 01:18:58 +0000 (17:18 -0800)]
systemc: Get rid of a duplicated base class initializer for sc_fifo.
These were consistent, but redundant and incorrect none the less.
Change-Id: I9ff7fdb9c83f9a8af6fbe969c6c73b9aab8967ad
Reviewed-on: https://gem5-review.googlesource.com/c/14136
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Gabe Black <gabeblack@google.com>
Gabe Black [Fri, 9 Nov 2018 01:18:20 +0000 (17:18 -0800)]
systemc: Add a missing "const" on one of the sc_event operators.
Change-Id: I073ccb0f2c6d1bfebadb95869d6acf7f4ce565af
Reviewed-on: https://gem5-review.googlesource.com/c/14135
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Gabe Black <gabeblack@google.com>
Gabe Black [Wed, 7 Nov 2018 08:17:42 +0000 (00:17 -0800)]
systemc: Only build python utility code if python is enabled.
Change-Id: I58054ddd0d5ef0dbee18028c4218e7418347f959
Reviewed-on: https://gem5-review.googlesource.com/c/13979
Maintainer: Gabe Black <gabeblack@google.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Gabe Black [Wed, 7 Nov 2018 08:15:03 +0000 (00:15 -0800)]
systemc: Separate and conditionalize exposing sc_main to python.
Change-Id: Ib39dd79c607b277ba94f90dee41c09c1b3b66481
Reviewed-on: https://gem5-review.googlesource.com/c/13978
Maintainer: Gabe Black <gabeblack@google.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Gabe Black [Wed, 7 Nov 2018 08:00:29 +0000 (00:00 -0800)]
systemc: Seperate out the sc_main fiber and its bookkeeping.
By pulling out the sc_main fiber (scMainFiber), we can make it
available to different entities in the simulator and avoid having to
have parallel bookkeeping.
Also this will make it possible to hook into sc_main without putting
the code in sc_main.cc.
Change-Id: I7689441424238e9b2e4d2b48e945dea35fd8cc5d
Reviewed-on: https://gem5-review.googlesource.com/c/13977
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Gabe Black <gabeblack@google.com>
Gabe Black [Wed, 7 Nov 2018 06:54:45 +0000 (22:54 -0800)]
systemc: Stop using python init to set up predefined message ids.
We can now be sure register_id will work even mid static initializers,
so we don't have to use python initialization as a hook to install
these predefined message ids.
Change-Id: I2e4d0c678ddda0a9ce5b114bdf1710f36e955f23
Reviewed-on: https://gem5-review.googlesource.com/c/13976
Maintainer: Gabe Black <gabeblack@google.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Gabe Black [Wed, 7 Nov 2018 01:48:58 +0000 (17:48 -0800)]
systemc: Wrap some report maps in functions.
By declaring the map as a static variable in that function and then
returning it, we can guarantee that it's initialized relative to other
static initializers so that we don't try to use a data structure that
isn't constructed yet. This will let us get rid of the dependence on
python for setting up that mapping.
Change-Id: I031ce2039de8f5f79fbb9d76cf1363f15207b64b
Reviewed-on: https://gem5-review.googlesource.com/c/13975
Maintainer: Gabe Black <gabeblack@google.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Daniel R. Carvalho [Wed, 7 Nov 2018 09:24:24 +0000 (10:24 +0100)]
configs: Add missing path to ruby imports
Add missing addToPath to ruby files, so that import
modules from previous folder are visible.
Change-Id: I912d78a2f709974f72fe768e73abac1617126f46
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/13995
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Daniel R. Carvalho [Mon, 15 Oct 2018 10:25:25 +0000 (12:25 +0200)]
mem-ruby: Use Packet writing functions instead of memcpy
Classes were using memcpy instead of the Packet functions
created for writing to/from the packet. This allows these
writes to be better checked and tracked.
Change-Id: Iae3fba1351330916ee1d4103809c71e151b1639e
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/13915
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
Tony Gutierrez [Thu, 25 Oct 2018 16:56:20 +0000 (12:56 -0400)]
misc: Update workflow requirements in CONTRIBUTING.md
Change-Id: I5394ef58930fccea343414964c1fc3e18829d609
Reviewed-on: https://gem5-review.googlesource.com/c/13755
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Giacomo Travaglini [Mon, 29 Oct 2018 11:10:33 +0000 (11:10 +0000)]
arch-arm: Deprecate usage of legacy bootloader patching
This patch is implicitly deprecating the usage of bootloader patching,
which is injecting instructions from gem5 into the bootloader
binary. This was probably meant to provide a dynamic bootloader
entry point.
This is not needed in ARMv8.0, since we can simply update the
ArmSystem::resetAddress with the bootloader entry point.
Change-Id: I0c469873b8d69f7b49a7383e0754468bc1f2bd72
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/14001
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Giacomo Travaglini [Wed, 31 Oct 2018 17:12:30 +0000 (17:12 +0000)]
arch-arm: ArmSystem::resetAddr64 renamed to be used in AArch32
ARMv8 differs from ARMv7 with the presence of RVBAR register, which
contains the implementation defined reset address when EL3 is not
implemented.
The entry 0x0 in the AArch32 vector table, once used for the Reset
Vector, is now marked as "Not used", stating that it is now IMPLEMENTATION
DEFINED. An implementation might still use this vector table entry to
hold the Reset vector, but having a Reset address != than the general
vector table (for any other exception) is allowed.
At the moment any Reset exception is still using 0 as a vector table
base address. This patch is extending the ArmSystem::resetAddr64 to
ArmSystem::resetAddr so that it can be used for initializing
MVBAR/RVBAR. In order to do so, we are providing a specialized behavior
for the Reset exception when evaluating the vector base address.
Change-Id: I051a730dc089e194db3b107bbed19251c661f87e
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/14000
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Giacomo Travaglini [Wed, 31 Oct 2018 16:45:48 +0000 (16:45 +0000)]
arch-arm: Implement AArch32 RVBAR
RVBAR has been added to the system register list since ARMv8.0-A. It is
implemented only if the highest Exception Level is different (minor)
than EL3. If that's not the case, MVBAR is used. Since the two
registers are mutually exclusive (depending on the presence of EL3),
they share the same coprocessor numbers:
p15, 0, c12, c0, 1
Rather than introducing a new register alias, we overload MVBAR so that
it is treated as RVBAR if ArmSystem::highestEL() < EL3. This patch is
changing the MiscReg info so that EL1 or EL2 access MVBAR (as RVBAR).
N.B MVBAR is RW, whereas RVBAR is RO
Change-Id: Ida3070413fd151ce79c446e99a2a389298d5f5bd
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/13999
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Giacomo Travaglini [Fri, 2 Nov 2018 10:33:30 +0000 (10:33 +0000)]
arch-arm: Remove SCTLR.VE bit
ARMv8 has removed SCTLR.VE bit which is now hardcoded to 0. We are
removing it from gem5 since we were not handling it anyway.
Change-Id: Ibde2db45c7f8add4a3188f2cb8c23701a6088d03
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/13998
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Giacomo Travaglini [Wed, 31 Oct 2018 14:57:30 +0000 (14:57 +0000)]
arch-arm: Refactor ISA::clear by adding a ISA::clear32 method
The patch is also moving some initialization code to be used
by AArch64 as well since the registers are mapped to AArch64 ones.
Change-Id: I0089df25275434172c6e0e9cb125ee535c04d1b8
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/13997
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Giacomo Travaglini [Wed, 31 Oct 2018 14:24:26 +0000 (14:24 +0000)]
arch-arm: Remove MISCREG commented numbers
Having an enum number might be useful in case we wanted to know how many
miscregs we have, but on the other hand it makes it tedious to update
the register list, since every commented number must be bumped. This
patch is removing the comments holding the MISCREG numbers
Change-Id: Ic5aba93885e4b8d6cb3bd6a4c49900b9e5474276
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/13996
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>