Jean THOMAS [Fri, 24 Jul 2020 12:58:55 +0000 (14:58 +0200)]
Fix code styling
Jean THOMAS [Fri, 24 Jul 2020 12:58:28 +0000 (14:58 +0200)]
Removing superfluous variables in multiplexer
Jean THOMAS [Fri, 24 Jul 2020 12:49:20 +0000 (14:49 +0200)]
Remove commented test
Jean THOMAS [Fri, 24 Jul 2020 12:40:26 +0000 (14:40 +0200)]
Fix code styling
Jean THOMAS [Fri, 24 Jul 2020 12:36:32 +0000 (14:36 +0200)]
Fix AntiStarvation
Jean THOMAS [Fri, 24 Jul 2020 12:30:21 +0000 (14:30 +0200)]
Use the correct value for test depth
Jean THOMAS [Thu, 23 Jul 2020 13:25:35 +0000 (15:25 +0200)]
Parametric test size, add delay option between write and read
Jean THOMAS [Thu, 23 Jul 2020 13:08:36 +0000 (15:08 +0200)]
Revert to timings from LiteDRAM
Jean THOMAS [Thu, 23 Jul 2020 12:34:11 +0000 (14:34 +0200)]
Fix code styling
Jean THOMAS [Thu, 23 Jul 2020 12:33:08 +0000 (14:33 +0200)]
Use clk pin definition from upstream nmigen-boards
Jean THOMAS [Thu, 23 Jul 2020 12:26:39 +0000 (14:26 +0200)]
Update nMigen version requirement
Jean THOMAS [Thu, 23 Jul 2020 10:27:02 +0000 (12:27 +0200)]
Fix burstdet CSR code
Jean THOMAS [Thu, 23 Jul 2020 10:00:43 +0000 (12:00 +0200)]
Fix platform code for simulation
Jean THOMAS [Wed, 22 Jul 2020 21:21:47 +0000 (23:21 +0200)]
Remove DQSPattern import
Jean THOMAS [Wed, 22 Jul 2020 15:24:09 +0000 (17:24 +0200)]
Add notes regarding CI usage
Jean THOMAS [Wed, 22 Jul 2020 15:22:34 +0000 (17:22 +0200)]
Handle rdly customization
Jean THOMAS [Wed, 22 Jul 2020 15:13:13 +0000 (17:13 +0200)]
Remove unnecessary signal reset
Jean THOMAS [Wed, 22 Jul 2020 14:44:38 +0000 (16:44 +0200)]
Rework burstdet CSR code
Jean THOMAS [Wed, 22 Jul 2020 14:43:46 +0000 (16:43 +0200)]
Fix granularity and sel in UARTBridge
Jean THOMAS [Wed, 22 Jul 2020 14:41:29 +0000 (16:41 +0200)]
Fix ECPIX585Platform to work with the latest commits in nmigen-boards
Jean THOMAS [Tue, 21 Jul 2020 14:14:00 +0000 (16:14 +0200)]
Rework CSR interface for PHY
Jean THOMAS [Tue, 21 Jul 2020 12:21:22 +0000 (14:21 +0200)]
Use 0x00BA0BAB instead of 0x12345678 for better readability
Jean THOMAS [Tue, 21 Jul 2020 12:20:20 +0000 (14:20 +0200)]
Remove commented DDR3 resource definition
Jean THOMAS [Tue, 21 Jul 2020 12:20:01 +0000 (14:20 +0200)]
Fix write timings
Jean THOMAS [Tue, 21 Jul 2020 11:30:08 +0000 (13:30 +0200)]
Replace Switch with If statement, indentation fixup
Jean THOMAS [Mon, 20 Jul 2020 16:23:18 +0000 (18:23 +0200)]
Remove DQSPattern
Jean THOMAS [Mon, 20 Jul 2020 16:18:13 +0000 (18:18 +0200)]
Apply changes from LiteDRAM#
fa7d91a
Jean THOMAS [Mon, 20 Jul 2020 14:46:28 +0000 (16:46 +0200)]
Fix code styling
Jean THOMAS [Mon, 20 Jul 2020 14:34:26 +0000 (16:34 +0200)]
Adding test for tXXDController
Jean THOMAS [Mon, 20 Jul 2020 14:05:44 +0000 (16:05 +0200)]
Add simple test for DQSPattern
Jean THOMAS [Mon, 20 Jul 2020 13:58:07 +0000 (15:58 +0200)]
Disable SSH access for successful builds
Jean THOMAS [Mon, 20 Jul 2020 13:50:19 +0000 (15:50 +0200)]
Simplify parameters code for DQSPattern
Jean THOMAS [Mon, 20 Jul 2020 13:47:40 +0000 (15:47 +0200)]
Remove unused code (PHYPadsCombiner/PHYPadsReducer)
Jean THOMAS [Mon, 20 Jul 2020 13:18:05 +0000 (15:18 +0200)]
Fix code styling
Jean THOMAS [Mon, 20 Jul 2020 11:18:40 +0000 (13:18 +0200)]
Set SEL when reading
Jean THOMAS [Mon, 20 Jul 2020 11:08:47 +0000 (13:08 +0200)]
Remove useless signal
Jean THOMAS [Mon, 20 Jul 2020 10:41:46 +0000 (12:41 +0200)]
Use PinsN when possible (fixes #27)
Jean THOMAS [Mon, 20 Jul 2020 10:15:25 +0000 (12:15 +0200)]
Simplify PHY read code
Jean THOMAS [Fri, 17 Jul 2020 16:46:14 +0000 (18:46 +0200)]
Use XDR for RAS#, CAS#, WE#, CLK_EN and ODT
Jean THOMAS [Fri, 17 Jul 2020 16:39:09 +0000 (18:39 +0200)]
Code cleaning in ECP5 PHY
Jean THOMAS [Fri, 17 Jul 2020 16:37:56 +0000 (18:37 +0200)]
Use XDR for ba pins
Jean THOMAS [Fri, 17 Jul 2020 16:32:54 +0000 (18:32 +0200)]
Use XDR for address pins
Jean THOMAS [Fri, 17 Jul 2020 16:31:48 +0000 (18:31 +0200)]
Fix when there are multiple clocks
Jean THOMAS [Fri, 17 Jul 2020 16:22:56 +0000 (18:22 +0200)]
Use nMigen's XDR for DDR clk
Jean THOMAS [Fri, 17 Jul 2020 16:10:44 +0000 (18:10 +0200)]
Remove unused signal
Jean THOMAS [Fri, 17 Jul 2020 15:54:45 +0000 (17:54 +0200)]
Fix code styling
Jean THOMAS [Fri, 17 Jul 2020 15:53:45 +0000 (17:53 +0200)]
Remove adaptation code
Jean THOMAS [Fri, 17 Jul 2020 15:51:18 +0000 (17:51 +0200)]
Remove get_port() function
Jean THOMAS [Fri, 17 Jul 2020 15:22:27 +0000 (17:22 +0200)]
Add test for _AntiStarvation timer duration
Jean THOMAS [Fri, 17 Jul 2020 15:21:30 +0000 (17:21 +0200)]
Fix code styling
Jean THOMAS [Fri, 17 Jul 2020 15:21:19 +0000 (17:21 +0200)]
Use the right domain
Jean THOMAS [Fri, 17 Jul 2020 15:20:53 +0000 (17:20 +0200)]
Fix PHY issues
Jean THOMAS [Fri, 17 Jul 2020 14:52:39 +0000 (16:52 +0200)]
Reduce delay between wishbone_write
Jean THOMAS [Fri, 17 Jul 2020 14:45:03 +0000 (16:45 +0200)]
Factor MRx setting code
Jean THOMAS [Fri, 17 Jul 2020 14:39:36 +0000 (16:39 +0200)]
Log DRAM commands
Jean THOMAS [Fri, 17 Jul 2020 14:39:13 +0000 (16:39 +0200)]
Put proc_rmdead after proc_mux
Jean THOMAS [Fri, 17 Jul 2020 14:38:36 +0000 (16:38 +0200)]
Name each BankMachine instance to improve VCD output
Jean THOMAS [Fri, 17 Jul 2020 14:37:38 +0000 (16:37 +0200)]
Fix CRG parameters
Jean THOMAS [Fri, 17 Jul 2020 14:00:59 +0000 (16:00 +0200)]
Fix DQS_N errors
Jean THOMAS [Fri, 17 Jul 2020 13:13:26 +0000 (15:13 +0200)]
Add more read transactions, add checks, ASAP
Jean THOMAS [Fri, 17 Jul 2020 09:25:38 +0000 (11:25 +0200)]
Remove event in ECP5DDRPHY
Jean THOMAS [Fri, 17 Jul 2020 09:25:20 +0000 (11:25 +0200)]
Remove comment
Jean THOMAS [Thu, 16 Jul 2020 13:36:00 +0000 (15:36 +0200)]
Use assertions in simsoc testbench
Jean THOMAS [Thu, 16 Jul 2020 13:23:08 +0000 (15:23 +0200)]
Add logging and delays to the simulation to make it run better at faster speeds
Jean THOMAS [Thu, 16 Jul 2020 13:22:22 +0000 (15:22 +0200)]
Tweak yosys script
Jean THOMAS [Thu, 16 Jul 2020 13:21:24 +0000 (15:21 +0200)]
Backport modifications from example's CRG
Jean THOMAS [Wed, 15 Jul 2020 16:09:08 +0000 (18:09 +0200)]
Write logic equivalences in a clearer way
Jean THOMAS [Wed, 15 Jul 2020 15:08:49 +0000 (17:08 +0200)]
Make Micron model read the mem_init.txt file
Jean THOMAS [Wed, 15 Jul 2020 15:08:26 +0000 (17:08 +0200)]
Make gram simulations faster
Jean THOMAS [Wed, 15 Jul 2020 15:07:33 +0000 (17:07 +0200)]
Add initial memory content
Jean THOMAS [Wed, 15 Jul 2020 15:07:12 +0000 (17:07 +0200)]
Add early code for RAM calibration
Jean THOMAS [Wed, 15 Jul 2020 15:06:31 +0000 (17:06 +0200)]
Expose DFII functions to other objects
Jean THOMAS [Wed, 15 Jul 2020 10:44:41 +0000 (12:44 +0200)]
Increase UART bridge speed in simulation, decrease simulation time
Jean THOMAS [Wed, 15 Jul 2020 10:18:28 +0000 (12:18 +0200)]
Log RAM signals
Jean THOMAS [Wed, 15 Jul 2020 10:02:27 +0000 (12:02 +0200)]
Fix code styling
Jean THOMAS [Wed, 15 Jul 2020 09:53:11 +0000 (11:53 +0200)]
Remove arbiter from headless-ecpix5 example
Jean THOMAS [Wed, 15 Jul 2020 09:16:04 +0000 (11:16 +0200)]
Use random values for memtest
Jean THOMAS [Mon, 13 Jul 2020 13:20:49 +0000 (15:20 +0200)]
Per bytes error highlighting
Jean THOMAS [Mon, 13 Jul 2020 12:08:13 +0000 (14:08 +0200)]
Make _AddressSlicer an elaboratable
Jean THOMAS [Mon, 13 Jul 2020 12:00:34 +0000 (14:00 +0200)]
Update amount of tests
Jean THOMAS [Mon, 13 Jul 2020 12:00:06 +0000 (14:00 +0200)]
Remove unnecessary arbiter
Jean THOMAS [Mon, 13 Jul 2020 11:08:17 +0000 (13:08 +0200)]
Fix timings in libgram
Jean THOMAS [Mon, 13 Jul 2020 11:07:50 +0000 (13:07 +0200)]
Reduce POR duration
Jean THOMAS [Mon, 13 Jul 2020 11:06:58 +0000 (13:06 +0200)]
Fix gearing and UART speed
Jean THOMAS [Mon, 13 Jul 2020 11:06:31 +0000 (13:06 +0200)]
Add additional opt+clean and print stats
Jean THOMAS [Mon, 13 Jul 2020 11:05:05 +0000 (13:05 +0200)]
Make full use of the native port
Jean THOMAS [Mon, 13 Jul 2020 09:58:47 +0000 (11:58 +0200)]
Fix gearing
Jean THOMAS [Mon, 13 Jul 2020 09:18:16 +0000 (11:18 +0200)]
Fix FakePHY bank emulation
Jean THOMAS [Mon, 13 Jul 2020 08:49:49 +0000 (10:49 +0200)]
Remove UnusedElaboratable warning
Jean THOMAS [Fri, 10 Jul 2020 17:20:20 +0000 (19:20 +0200)]
Fix memtest tests (missing parenthesis)
Jean THOMAS [Fri, 10 Jul 2020 17:13:09 +0000 (19:13 +0200)]
Add more memory tests
Jean THOMAS [Fri, 10 Jul 2020 16:39:35 +0000 (18:39 +0200)]
Remove unused files
Jean THOMAS [Fri, 10 Jul 2020 16:39:04 +0000 (18:39 +0200)]
Put every gram component in the dramsync clock domain
Jean THOMAS [Fri, 10 Jul 2020 16:38:35 +0000 (18:38 +0200)]
Use clock freq from platform
Jean THOMAS [Fri, 10 Jul 2020 16:37:24 +0000 (18:37 +0200)]
Use R02 platform file
Jean THOMAS [Fri, 10 Jul 2020 16:35:10 +0000 (18:35 +0200)]
Externalize CRG
Jean THOMAS [Fri, 10 Jul 2020 16:32:32 +0000 (18:32 +0200)]
Fix DDR3 module parameter
Jean THOMAS [Fri, 10 Jul 2020 16:27:45 +0000 (18:27 +0200)]
Fix code styling
Jean THOMAS [Fri, 10 Jul 2020 16:27:05 +0000 (18:27 +0200)]
Add a name to timing_checker submodule
Jean THOMAS [Fri, 10 Jul 2020 16:26:02 +0000 (18:26 +0200)]
Rework headless client interface