Merge remote-tracking branch 'origin/master' into xc7srl

Merge pull request #943 from YosysHQ/clifford/whitebox

[WIP] Add "whitebox" attribute, add "read_verilog -wb"

Merge remote-tracking branch 'origin/pmux2shiftx' into xc7srl

Merge remote-tracking branch 'origin' into xc7srl

Add "techmap -wb", use in formal flows

Signed-off-by: Clifford Wolf <clifford@clifford.at>

Check blackbox attribute in techmap/simplemap

Signed-off-by: Clifford Wolf <clifford@clifford.at>

Add "wbflip" command

Signed-off-by: Clifford Wolf <clifford@clifford.at>

Merge pull request #942 from YosysHQ/clifford/fix931

Improve proc full_case detection and handling

Improve "show" handling of 0/1/X/Z padding

Signed-off-by: Clifford Wolf <clifford@clifford.at>

Change "ne" to "neq" in btor2 output

we need to do this because they changed the parser:
https://github.com/Boolector/btor2tools/commit/e97fc9cedabadeec4f621de22096e514f862c690

Signed-off-by: Clifford Wolf <clifford@clifford.at>

Add tests/aiger/.gitignore

Signed-off-by: Clifford Wolf <clifford@clifford.at>

Spelling fixes

Revert "write_json to not write contents (cells/wires) of whiteboxes"

This reverts commit 4ef03e19a8eafc324d3442f0642abf858071fdd4.

Update to ABC 3709744

Signed-off-by: Clifford Wolf <clifford@clifford.at>

Merge pull request #917 from YosysHQ/eddie/fix_retime

Retime by default when abc -dff

write_json to not write contents (cells/wires) of whiteboxes

Ignore 'whitebox' attr in flatten with "-wb" option

Fix abc's remap_name to not ignore [^0-9] when extracting sid

ABC to call retime all the time

Add "whitebox" attribute, add "read_verilog -wb"

Signed-off-by: Clifford Wolf <clifford@clifford.at>

Revert "synth_* with -retime option now calls abc with -D 1 as well"

This reverts commit 9a6da9a79a22e984ee3eec02caa230b66f10e11a.

Merge branch 'master' into eddie/fix_retime

Improve proc full_case detection and handling, fixes #931

Signed-off-by: Clifford Wolf <clifford@clifford.at>

Update to ABC d1b6413

Signed-off-by: Clifford Wolf <clifford@clifford.at>

Merge pull request #939 from YosysHQ/revert895

Revert #895 (mux-to-shiftx optimisation)

Revert #895

Merge pull request #937 from YosysHQ/revert-932-eddie/fixdlatch

Revert "Recognise default entry in case even if all cases covered (fix for #931)"

Revert "Recognise default entry in case even if all cases covered (fix for #931)"

Merge pull request #936 from YosysHQ/README-fix-quotes

README: fix some incorrect quoting

README: fix some incorrect quoting.

Merge pull request #928 from litghost/add_xc7_sim_models

Add additional cells sim models for core 7-series primitives.

Remove BUFGCTRL, BUFHCE and LUT6_2 from cells_xtra.

Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>

Merge pull request #933 from dh73/master

Fixing issues in CycloneV cell sim

Merge pull request #932 from YosysHQ/eddie/fixdlatch

Recognise default entry in case even if all cases covered (fix for #931)

Fixing issues in CycloneV cell sim

Fix ordering of when to insert zero index

More unused

Remove unused

Fixes

WIP

Spelling fixes

Add default entry to testcase

Recognise default entry in case even if all cases covered (#931)

synth_* with -retime option now calls abc with -D 1 as well

Revert "abc -dff now implies "-D 0" otherwise retiming doesn't happen"

This reverts commit 19271bd996a79cb4be1db658fcf18227ee0a1dff.

Revert ""&nf -D 0" fails => use "-D 1" instead"

This reverts commit 3c253818cab2013dc4db55732d3e21cfa0dc3f19.

Merge remote-tracking branch 'origin/master' into eddie/fix_retime

Fix LUT6_2 definition.

Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>

Add additional cells sim models for core 7-series primatives.

Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>

Fix a few typos

$_XILINX_SHREG_ to preserve src attribute

Update CHANGELOG

Merge branch 'undo_pr895' into xc7srl

Undo #895 by instead setting an attribute

Cope with undoing #895

Merge pull request #919 from YosysHQ/multiport_transp

memory_bram: Fix multiport make_transp

Revert "Remove handling for $pmux, since #895"

This reverts commit aa693d5723ef1438d42cd35a26673703b1eff79f.

memory_bram: Fix multiport make_transp

Signed-off-by: David Shah <dave@ds0.me>

Call shregmap twice -- once for variable, another for fixed

Merge branch 'eddie/fix_retime' into xc7srl

Add retime test

Fix S0 -> S1

Move dffinit til after abc

Merge branch 'eddie/fix_retime' into xc7srl

Move techamp t:$_DFF_?N? to before abc call

Retry

"&nf -D 0" fails => use "-D 1" instead

Resolve @daveshah1 comment, update synth_xilinx help

synth_xilinx to techmap FFs after abc call, otherwise -retime fails

abc -dff now implies "-D 0" otherwise retiming doesn't happen

techmap inside map_cells stage

Add "read_ilang -lib"

Signed-off-by: Clifford Wolf <clifford@clifford.at>

Added missing argument checking to "mutate" command

Signed-off-by: Clifford Wolf <clifford@clifford.at>

Merge branch 'map_cells_before_map_luts' into xc7srl

Missing techmap entry in help

Use soft-logic, not LUT3 instantiation

Merge branch 'map_cells_before_map_luts' into xc7srl

synth_xilinx to map_cells before map_luts

Cleanup comments

t:$dff* -> t:$dff t:$dffe

Remove handling for $pmux, since #895

-nosrl meant when -nobram

Remove duplicate STARTUPE2

Disable shregmap in synth_xilinx if -retime

Add changelog entry

Merge pull request #913 from smunaut/fix_proc_mux

proc_mux: Fix crash when trying to optimize non-existant mux to shiftx

proc_mux: Fix crash when trying to optimize non-existant mux to shiftx

last_mux_cell can be NULL ...

Signed-off-by: Sylvain Munaut <tnt@246tNt.com>

Merge remote-tracking branch 'origin/master' into xc7srl

Merge pull request #912 from YosysHQ/bram_addr_en

memory_bram: Consider read enable for address expansion register

Merge pull request #910 from ucb-bar/memupdates

Refine memory support to deal with general Verilog memory definitions.

memory_bram: Consider read enable for address expansion register

Signed-off-by: David Shah <dave@ds0.me>

Merge pull request #895 from YosysHQ/pmux2shiftx

RFC: Add a pmux-to-shiftx optimisation to proc_mux

Refine memory support to deal with general Verilog memory definitions.

Merge pull request #907 from YosysHQ/clifford/fix906

Build Verilog parser with -DYYMAXDEPTH=100000

Build Verilog parser with -DYYMAXDEPTH=100000, fixes #906

Signed-off-by: Clifford Wolf <clifford@clifford.at>

Merge pull request #901 from trcwm/libertyfixes

Libertyfixes: accept superfluous ; at end of group.

Merge pull request #903 from YosysHQ/bram_reset_transp

memory_bram: Reset make_transp when growing read ports

memory_bram: Reset make_transp when growing read ports

Signed-off-by: David Shah <dave@ds0.me>

Liberty file parser now accepts superfluous ;

Liberty file parser now accepts superfluous ;