yosys.git
3 years agoMerge pull request #2585 from YosysHQ/dave/nexus-dotproduct
gatecat [Fri, 12 Feb 2021 12:07:12 +0000 (12:07 +0000)]
Merge pull request #2585 from YosysHQ/dave/nexus-dotproduct

nexus: Add MULTADDSUB9X9WIDE sim model

3 years agoGanulate Verific support
Miodrag Milanovic [Fri, 12 Feb 2021 09:08:43 +0000 (10:08 +0100)]
Ganulate Verific support

3 years agoBump version
Yosys Bot [Fri, 12 Feb 2021 00:10:05 +0000 (00:10 +0000)]
Bump version

3 years agoMerge pull request #2573 from zachjs/repeat-call
whitequark [Thu, 11 Feb 2021 19:56:41 +0000 (19:56 +0000)]
Merge pull request #2573 from zachjs/repeat-call

verilog: refactored constant function evaluation

3 years agoMerge pull request #2578 from zachjs/genblk-port
Zachary Snow [Thu, 11 Feb 2021 15:26:49 +0000 (10:26 -0500)]
Merge pull request #2578 from zachjs/genblk-port

verlog: allow shadowing module ports within generate blocks

3 years agoMerge pull request #2584 from antmicro/atom_type_signedness
Zachary Snow [Thu, 11 Feb 2021 15:26:06 +0000 (10:26 -0500)]
Merge pull request #2584 from antmicro/atom_type_signedness

verilog_parser: fix missing is_signed attribute in type_atom

3 years agoAdd missing is_signed to type_atom
Kamil Rakoczy [Thu, 11 Feb 2021 11:53:07 +0000 (12:53 +0100)]
Add missing is_signed to type_atom

Signed-off-by: Kamil Rakoczy <krakoczy@antmicro.com>
3 years agoverlog: allow shadowing module ports within generate blocks
Zachary Snow [Sun, 7 Feb 2021 04:54:17 +0000 (23:54 -0500)]
verlog: allow shadowing module ports within generate blocks

This is a somewhat obscure edge case I encountered while working on test
cases for earlier changes. Declarations in generate blocks should not be
checked against the list of ports. This change also adds a check
forbidding declarations within generate blocks being tagged as inputs or
outputs.

3 years agoBump version
Yosys Bot [Sun, 7 Feb 2021 00:10:04 +0000 (00:10 +0000)]
Bump version

3 years agoMerge pull request #2576 from zachjs/port-bind-sign-uniop
whitequark [Sat, 6 Feb 2021 19:25:32 +0000 (19:25 +0000)]
Merge pull request #2576 from zachjs/port-bind-sign-uniop

genrtlil: fix signed port connection codegen failures

3 years agogenrtlil: fix signed port connection codegen failures
Zachary Snow [Sat, 6 Feb 2021 00:38:10 +0000 (19:38 -0500)]
genrtlil: fix signed port connection codegen failures

This fixes binding signed memory reads, signed unary expressions, and
signed complex SigSpecs to ports. This also sets `is_signed` for wires
generated from signed params when -pwires is used. Though not necessary
for any of the current usages, `is_signed` is now appropriately set when
the `extendWidth` helper is used.

3 years agoBump version
Yosys Bot [Sat, 6 Feb 2021 00:10:05 +0000 (00:10 +0000)]
Bump version

3 years agoMerge pull request #2572 from antmicro/check-labels
whitequark [Fri, 5 Feb 2021 06:49:34 +0000 (06:49 +0000)]
Merge pull request #2572 from antmicro/check-labels

verilog_parser: add label check to gen_block

3 years agoBump version
Yosys Bot [Fri, 5 Feb 2021 00:10:05 +0000 (00:10 +0000)]
Bump version

3 years agoAdd check of begin/end labels for genblock
Kamil Rakoczy [Thu, 4 Feb 2021 11:12:59 +0000 (12:12 +0100)]
Add check of begin/end labels for genblock

Signed-off-by: Kamil Rakoczy <krakoczy@antmicro.com>
3 years agoverilog: refactored constant function evaluation
Zachary Snow [Wed, 27 Jan 2021 18:21:13 +0000 (13:21 -0500)]
verilog: refactored constant function evaluation

Elaboration now attempts constant evaluation of any function call with
only constant arguments, regardless of the context or contents of the
function. This removes the concept of "recommended constant evaluation"
which previously applied to functions with `for` loops or which were
(sometimes erroneously) identified as recursive. Any function call in a
constant context (e.g., `localparam`) or which contains a constant-only
procedural construct (`while` or `repeat`) in its body will fail as
before if constant evaluation does not succeed.

3 years agoMerge pull request #2529 from zachjs/unnamed-genblk
whitequark [Thu, 4 Feb 2021 09:57:28 +0000 (09:57 +0000)]
Merge pull request #2529 from zachjs/unnamed-genblk

verilog: significant block scoping improvements

3 years agoBump version
Yosys Bot [Thu, 4 Feb 2021 00:10:05 +0000 (00:10 +0000)]
Bump version

3 years agoMerge pull request #2436 from dalance/fix_generate
whitequark [Wed, 3 Feb 2021 09:43:23 +0000 (09:43 +0000)]
Merge pull request #2436 from dalance/fix_generate

Fix begin/end in generate

3 years agoverilog: significant block scoping improvements
Zachary Snow [Wed, 27 Jan 2021 18:30:22 +0000 (13:30 -0500)]
verilog: significant block scoping improvements

This change set contains a number of bug fixes and improvements related to
scoping and resolution in generate and procedural blocks. While many of the
frontend changes are interdependent, it may be possible bring the techmap
changes in under a separate PR.

Declarations within unnamed generate blocks previously encountered issues
because the data declarations were left un-prefixed, breaking proper scoping.
The LRM outlines behavior for generating names for unnamed generate blocks. The
original goal was to add this implicit labelling, but doing so exposed a number
of issues downstream. Additional testing highlighted other closely related scope
resolution issues, which have been fixed. This change also adds support for
block item declarations within unnamed blocks in SystemVerilog mode.

1. Unlabled generate blocks are now implicitly named according to the LRM in
   `label_genblks`, which is invoked at the beginning of module elaboration
2. The Verilog parser no longer wraps explicitly named generate blocks in a
   synthetic unnamed generate block to avoid creating extra hierarchy levels
   where they should not exist
3. The techmap phase now allows special control identifiers to be used outside
   of the topmost scope, which is necessary because such wires and cells often
   appear in unlabeled generate blocks, which now prefix the declarations within
4. Some techlibs required modifications because they relied on the previous
   invalid scope resolution behavior
5. `expand_genblock` has been simplified, now only expanding the outermost
   scope, completely deferring the inspection and elaboration of nested scopes;
   names are now resolved by looking in the innermost scope and stepping outward
6. Loop variables now always become localparams during unrolling, allowing them
   to be resolved and shadowed like any other identifier
7. Identifiers in synthetic function call scopes are now prefixed and resolved
   in largely the same manner as other blocks
     before: `$func$\func_01$tests/simple/scopes.blk.v:60$5$\blk\x`
      after: `\func_01$func$tests/simple/scopes.v:60$5.blk.x`
8. Support identifiers referencing a local generate scope nested more
   than 1 level deep, i.e. `B.C.x` while within generate scope `A`, or using a
   prefix of a current or parent scope, i.e. `B.C.D.x` while in `A.B`, `A.B.C`,
   or `A.B.C.D`
9. Variables can now be declared within unnamed blocks in SystemVerilog mode

Addresses the following issues: 656, 2423, 2493

3 years agoBump version
Yosys Bot [Sun, 31 Jan 2021 00:10:05 +0000 (00:10 +0000)]
Bump version

3 years agoRequire latest Verific build
Miodrag Milanovic [Sat, 30 Jan 2021 08:23:46 +0000 (09:23 +0100)]
Require latest Verific build

3 years agoBump version
Yosys Bot [Sat, 30 Jan 2021 00:10:05 +0000 (00:10 +0000)]
Bump version

3 years agoast: fix dump_vlog display of casex/casez
Marcelina Kościelnicka [Wed, 27 Jan 2021 23:31:50 +0000 (00:31 +0100)]
ast: fix dump_vlog display of casex/casez

The first child of AST_CASE is the case expression, it's subsequent
childrean that are AST_COND* and can be used to discriminate the type of
the case.

3 years agoMerge pull request #2564 from whitequark/flatten-improve-error
whitequark [Fri, 29 Jan 2021 02:55:51 +0000 (02:55 +0000)]
Merge pull request #2564 from whitequark/flatten-improve-error

flatten: clarify confusing error message

3 years agoBump version
Yosys Bot [Fri, 29 Jan 2021 00:10:05 +0000 (00:10 +0000)]
Bump version

3 years agoMerge pull request #2569 from zachjs/macro-arg-surrounding-spaces
whitequark [Thu, 28 Jan 2021 21:32:27 +0000 (21:32 +0000)]
Merge pull request #2569 from zachjs/macro-arg-surrounding-spaces

verilog: strip leading and trailing spaces in macro args

3 years agoMerge pull request #2535 from Ravenslofty/scc-specify
Claire Xen [Thu, 28 Jan 2021 18:01:29 +0000 (19:01 +0100)]
Merge pull request #2535 from Ravenslofty/scc-specify

scc: Add -specify option to find loops in boxes

3 years agoverilog: strip leading and trailing spaces in macro args
Zachary Snow [Thu, 28 Jan 2021 16:26:21 +0000 (11:26 -0500)]
verilog: strip leading and trailing spaces in macro args

3 years agoBump version
Yosys Bot [Wed, 27 Jan 2021 00:10:04 +0000 (00:10 +0000)]
Bump version

3 years agoxilinx_dffopt: Don't crash on missing IS_*_INVERTED.
Marcelina Kościelnicka [Mon, 25 Jan 2021 12:01:18 +0000 (13:01 +0100)]
xilinx_dffopt: Don't crash on missing IS_*_INVERTED.

The presence of IS_*_INVERTED on FD* cells follows Vivado, which
apparently has been decided by a dice roll.  Just assume false if the
parameter doesn't exist.

Fixes #2559.

3 years agoxilinx: Add FDRSE_1, FDCPE_1.
Marcelina Kościelnicka [Mon, 25 Jan 2021 12:01:24 +0000 (13:01 +0100)]
xilinx: Add FDRSE_1, FDCPE_1.

3 years agoMerge pull request #2563 from whitequark/cxxrtl-msvc
whitequark [Tue, 26 Jan 2021 21:55:12 +0000 (21:55 +0000)]
Merge pull request #2563 from whitequark/cxxrtl-msvc

cxxrtl: do not use `->template` for non-dependent names

3 years agoMerge pull request #2544 from modwizcode/fix-clock
whitequark [Tue, 26 Jan 2021 21:18:06 +0000 (21:18 +0000)]
Merge pull request #2544 from modwizcode/fix-clock

CXXRTL: Fix sliced bits as clock inputs

3 years agoflatten: clarify confusing error message.
whitequark [Tue, 26 Jan 2021 18:29:16 +0000 (18:29 +0000)]
flatten: clarify confusing error message.

3 years agocxxrtl: do not use `->template` for non-dependent names.
whitequark [Tue, 26 Jan 2021 17:42:23 +0000 (17:42 +0000)]
cxxrtl: do not use `->template` for non-dependent names.

This breaks build on MSVC but not GCC/Clang.

3 years agoscc: Add -specify option to find loops in boxes
Dan Ravensloft [Mon, 11 Jan 2021 18:37:27 +0000 (18:37 +0000)]
scc: Add -specify option to find loops in boxes

3 years agoBump version
Yosys Bot [Tue, 26 Jan 2021 00:10:05 +0000 (00:10 +0000)]
Bump version

3 years agoMerge pull request #2549 from pgadfort/support-multiple-libs
whitequark [Mon, 25 Jan 2021 10:36:14 +0000 (10:36 +0000)]
Merge pull request #2549 from pgadfort/support-multiple-libs

adding support for passing multiple liberty files to abc

3 years agoMerge pull request #2550 from zachjs/macro-arg-spaces
whitequark [Mon, 25 Jan 2021 10:36:07 +0000 (10:36 +0000)]
Merge pull request #2550 from zachjs/macro-arg-spaces

verilog: allow spaces in macro arguments

3 years agoBump version
Yosys Bot [Mon, 25 Jan 2021 00:10:07 +0000 (00:10 +0000)]
Bump version

3 years agoMerge pull request #2558 from YosysHQ/dave/chandle-dpi
Claire Xen [Sun, 24 Jan 2021 01:45:08 +0000 (02:45 +0100)]
Merge pull request #2558 from YosysHQ/dave/chandle-dpi

dpi: Support for chandle type

3 years agodpi: Support for chandle type
David Shah [Sat, 23 Jan 2021 22:24:31 +0000 (22:24 +0000)]
dpi: Support for chandle type

Signed-off-by: David Shah <dave@ds0.me>
3 years agoBump version
Yosys Bot [Fri, 22 Jan 2021 00:10:05 +0000 (00:10 +0000)]
Bump version

3 years agoMerge pull request #2553 from zachjs/rand-const-modifiers
Miodrag Milanović [Thu, 21 Jan 2021 15:56:19 +0000 (16:56 +0100)]
Merge pull request #2553 from zachjs/rand-const-modifiers

Allow combination of rand and const modifiers

3 years agoAllow combination of rand and const modifiers
Zachary Snow [Thu, 21 Jan 2021 15:30:55 +0000 (08:30 -0700)]
Allow combination of rand and const modifiers

3 years agoBump version
Yosys Bot [Thu, 21 Jan 2021 00:10:05 +0000 (00:10 +0000)]
Bump version

3 years agoMerge pull request #2552 from YosysHQ/claire/yosyshq
Claire Xen [Wed, 20 Jan 2021 23:54:45 +0000 (00:54 +0100)]
Merge pull request #2552 from YosysHQ/claire/yosyshq

Switch verific bindings from Symbiotic EDA flavored Verific to YosysHQ flavored Verific

3 years agoSwitch verific bindings from Symbiotic EDA flavored Verific to YosysHQ flavored Verific
Claire Xenia Wolf [Wed, 20 Jan 2021 19:48:10 +0000 (20:48 +0100)]
Switch verific bindings from Symbiotic EDA flavored Verific to YosysHQ flavored Verific

Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
3 years agoMerge pull request #2536 from TobiasFaller/master
Miodrag Milanović [Wed, 20 Jan 2021 19:42:02 +0000 (20:42 +0100)]
Merge pull request #2536 from TobiasFaller/master

Fixed missing goto statement in passes/techmap/abc.cc

3 years agoMerge pull request #2551 from zachjs/wire-logic
Miodrag Milanović [Wed, 20 Jan 2021 17:31:49 +0000 (18:31 +0100)]
Merge pull request #2551 from zachjs/wire-logic

sv: fix support wire and var data type modifiers

3 years agosv: fix support wire and var data type modifiers
Zachary Snow [Wed, 20 Jan 2021 16:15:48 +0000 (09:15 -0700)]
sv: fix support wire and var data type modifiers

3 years agoverilog: allow spaces in macro arguments
Zachary Snow [Wed, 20 Jan 2021 15:49:32 +0000 (08:49 -0700)]
verilog: allow spaces in macro arguments

3 years agoBump version
Yosys Bot [Tue, 19 Jan 2021 00:10:05 +0000 (00:10 +0000)]
Bump version

3 years agoadding support for passing multiple liberty files to abc
Peter Gadfort [Mon, 18 Jan 2021 21:47:49 +0000 (16:47 -0500)]
adding support for passing multiple liberty files to abc

3 years agoMerge pull request #2547 from zachjs/plugin-so-dsym
whitequark [Mon, 18 Jan 2021 20:21:20 +0000 (20:21 +0000)]
Merge pull request #2547 from zachjs/plugin-so-dsym

Add plugin.so.dSYM to .gitignore

3 years agoMerge pull request #2312 from antmicro/typedef-inout
whitequark [Mon, 18 Jan 2021 20:20:52 +0000 (20:20 +0000)]
Merge pull request #2312 from antmicro/typedef-inout

Add support for user types in IOs

3 years agoAdd plugin.so.dSYM to .gitignore
Zachary Snow [Mon, 18 Jan 2021 18:13:21 +0000 (11:13 -0700)]
Add plugin.so.dSYM to .gitignore

This artifact is automatically generated by the builtin clang on macOS
when -g is used.

3 years agoAdd typedef input/output test
Kamil Rakoczy [Wed, 8 Jul 2020 11:44:03 +0000 (13:44 +0200)]
Add typedef input/output test

Signed-off-by: Kamil Rakoczy <krakoczy@antmicro.com>
3 years agoFix input/output attributes when resolving typedef of wire
Kamil Rakoczy [Tue, 9 Jun 2020 07:53:00 +0000 (09:53 +0200)]
Fix input/output attributes when resolving typedef of wire

Signed-off-by: Kamil Rakoczy <krakoczy@antmicro.com>
3 years agoParse package user type in module port list
Lukasz Dalek [Tue, 19 May 2020 15:13:04 +0000 (17:13 +0200)]
Parse package user type in module port list

Signed-off-by: Lukasz Dalek <ldalek@antmicro.com>
Signed-off-by: Kamil Rakoczy <krakoczy@antmicro.com>
3 years agoImproves the previous commit with a more complete coverage of the cases
Iris Johnson [Fri, 15 Jan 2021 19:59:20 +0000 (13:59 -0600)]
Improves the previous commit with a more complete coverage of the cases

3 years agoBump version
Yosys Bot [Fri, 15 Jan 2021 00:10:05 +0000 (00:10 +0000)]
Bump version

3 years agoHandle sliced bits as clock inputs (fixes #2542)
Iris Johnson [Thu, 14 Jan 2021 22:26:20 +0000 (16:26 -0600)]
Handle sliced bits as clock inputs (fixes #2542)

3 years agoopt_share: Fix X and CO signal width for shifted $alu in opt_share.
Marcelina Kościelnicka [Thu, 14 Jan 2021 08:58:33 +0000 (09:58 +0100)]
opt_share: Fix X and CO signal width for shifted $alu in opt_share.

These need to be the same length as actual Y, not visible part of Y.

Fixes #2538.

3 years agoBump version
Yosys Bot [Thu, 14 Jan 2021 00:10:05 +0000 (00:10 +0000)]
Bump version

3 years agoMerge pull request #2537 from pepijndevos/spice
Claire Xen [Wed, 13 Jan 2021 18:08:25 +0000 (19:08 +0100)]
Merge pull request #2537 from pepijndevos/spice

Add buffer option to spice backend

3 years agoadd buffer option to spice backend
Pepijn de Vos [Wed, 13 Jan 2021 16:24:28 +0000 (17:24 +0100)]
add buffer option to spice backend

3 years agoFixed missing goto statement in passes/techmap/abc.cc
Tobias Faller [Tue, 12 Jan 2021 15:17:51 +0000 (16:17 +0100)]
Fixed missing goto statement in passes/techmap/abc.cc

3 years agoBump version
Yosys Bot [Tue, 5 Jan 2021 00:10:05 +0000 (00:10 +0000)]
Bump version

3 years agoMerge pull request #2522 from tomverbeure/simlib_typos2
whitequark [Mon, 4 Jan 2021 14:04:17 +0000 (14:04 +0000)]
Merge pull request #2522 from tomverbeure/simlib_typos2

Fix some trivial typos.

3 years agoFix some trivial typos.
Tom Verbeure [Mon, 4 Jan 2021 07:52:59 +0000 (23:52 -0800)]
Fix some trivial typos.

3 years agoBump version
Yosys Bot [Sat, 2 Jan 2021 00:10:04 +0000 (00:10 +0000)]
Bump version

3 years agoMerge pull request #2480 from YosysHQ/dave/nexus-lram
whitequark [Fri, 1 Jan 2021 09:49:00 +0000 (09:49 +0000)]
Merge pull request #2480 from YosysHQ/dave/nexus-lram

nexus: Add LRAM inference

3 years agoMerge pull request #2512 from umarcor/plugin-err
whitequark [Fri, 1 Jan 2021 09:39:17 +0000 (09:39 +0000)]
Merge pull request #2512 from umarcor/plugin-err

plugin: enhance no-plugin error

3 years agoMerge pull request #2515 from umarcor/fix/ghdl
whitequark [Fri, 1 Jan 2021 09:37:12 +0000 (09:37 +0000)]
Merge pull request #2515 from umarcor/fix/ghdl

makefile: fix GHDL vars, replace GHDL_DIR with GHDL_PREFIX

3 years agoMerge pull request #2518 from zachjs/recursion
whitequark [Fri, 1 Jan 2021 09:32:26 +0000 (09:32 +0000)]
Merge pull request #2518 from zachjs/recursion

verilog: improved support for recursive functions

3 years agoMerge pull request #2517 from zachjs/sv-tf-implied-direction
whitequark [Fri, 1 Jan 2021 09:31:49 +0000 (09:31 +0000)]
Merge pull request #2517 from zachjs/sv-tf-implied-direction

sv: complete support for implied task/function port directions

3 years agoverilog: improved support for recursive functions
Zachary Snow [Fri, 1 Jan 2021 00:23:36 +0000 (17:23 -0700)]
verilog: improved support for recursive functions

3 years agosv: complete support for implied task/function port directions
Zachary Snow [Thu, 31 Dec 2020 23:14:35 +0000 (16:14 -0700)]
sv: complete support for implied task/function port directions

3 years agomakefile: fix GHDL vars, replace GHDL_DIR with GHDL_PREFIX
umarcor [Wed, 30 Dec 2020 06:06:52 +0000 (07:06 +0100)]
makefile: fix GHDL vars, replace GHDL_DIR with GHDL_PREFIX

3 years agoBump version
Yosys Bot [Wed, 30 Dec 2020 00:10:06 +0000 (00:10 +0000)]
Bump version

3 years agoplugin: enhance no-plugin error
umarcor [Mon, 28 Dec 2020 03:30:57 +0000 (04:30 +0100)]
plugin: enhance no-plugin error

3 years agoMerge pull request #2509 from zachjs/issue-2427
whitequark [Tue, 29 Dec 2020 02:59:09 +0000 (02:59 +0000)]
Merge pull request #2509 from zachjs/issue-2427

Fix elaboration of whole memory words used as indices

3 years agoMerge pull request #2514 from umarcor/feat/ghdl
whitequark [Tue, 29 Dec 2020 02:58:41 +0000 (02:58 +0000)]
Merge pull request #2514 from umarcor/feat/ghdl

makefile: add support for built-in ghdl-yosys-plugin

3 years agoBump version
Yosys Bot [Tue, 29 Dec 2020 00:10:04 +0000 (00:10 +0000)]
Bump version

3 years agomakefile: add support for built-in ghdl-yosys-plugin
umarcor [Mon, 28 Dec 2020 01:24:41 +0000 (02:24 +0100)]
makefile: add support for built-in ghdl-yosys-plugin

Co-authored-by: Tristan Gingold <tgingold@free.fr>
Co-authored-by: whitequark <whitequark@whitequark.org>
3 years agoMerge pull request #2511 from umarcor/feat/msys2-32
whitequark [Mon, 28 Dec 2020 02:33:58 +0000 (02:33 +0000)]
Merge pull request #2511 from umarcor/feat/msys2-32

Update MSYS2 build system

3 years agoMerge pull request #2507 from umarcor/fix/msys2
whitequark [Mon, 28 Dec 2020 02:33:30 +0000 (02:33 +0000)]
Merge pull request #2507 from umarcor/fix/msys2

kernel/yosys.h: undef CONST on WIN32

3 years agomakefile: rename msys2 to msys2-32, config PREFIX
umarcor [Sun, 27 Dec 2020 04:37:46 +0000 (05:37 +0100)]
makefile: rename msys2 to msys2-32, config PREFIX

3 years agokernel/yosys.h: undef CONST on WIN32
umarcor [Sat, 26 Dec 2020 22:21:30 +0000 (23:21 +0100)]
kernel/yosys.h: undef CONST on WIN32

3 years agoBump version
Yosys Bot [Mon, 28 Dec 2020 00:10:04 +0000 (00:10 +0000)]
Bump version

3 years agoMerge pull request #2510 from YosysHQ/whitequark/CODEOWNERS-verilog-ast
Claire Xen [Sun, 27 Dec 2020 15:33:58 +0000 (16:33 +0100)]
Merge pull request #2510 from YosysHQ/whitequark/CODEOWNERS-verilog-ast

CODEOWNERS: add @zachjs as Verilog/AST frontend owner

3 years agoCODEOWNERS: add @zachjs as Verilog/AST frontend owner
whitequark [Sun, 27 Dec 2020 05:00:04 +0000 (05:00 +0000)]
CODEOWNERS: add @zachjs as Verilog/AST frontend owner

3 years agoFix elaboration of whole memory words used as indices
Zachary Snow [Sun, 27 Dec 2020 04:38:13 +0000 (21:38 -0700)]
Fix elaboration of whole memory words used as indices

3 years agoBump version
Yosys Bot [Sun, 27 Dec 2020 00:10:10 +0000 (00:10 +0000)]
Bump version

3 years agoMerge pull request #2506 from zachjs/const-arg-redeclare
Miodrag Milanović [Sat, 26 Dec 2020 17:59:06 +0000 (18:59 +0100)]
Merge pull request #2506 from zachjs/const-arg-redeclare

Fix constants bound to redeclared function args

3 years agoFix constants bound to redeclared function args
Zachary Snow [Sat, 26 Dec 2020 15:39:57 +0000 (08:39 -0700)]
Fix constants bound to redeclared function args

The changes in #2476 ensured that function inputs like `input x;`
retained their single-bit size when instantiated with a constant
argument and turned into a localparam. That change did not handle the
possibility for an input to be redeclared later on with an explicit
width, such as `integer x;`.

3 years agoBump version
Yosys Bot [Thu, 24 Dec 2020 00:10:08 +0000 (00:10 +0000)]
Bump version

3 years agoMerge pull request #2502 from ldoolitt/master
whitequark [Wed, 23 Dec 2020 23:36:13 +0000 (23:36 +0000)]
Merge pull request #2502 from ldoolitt/master

passes/pmgen/pmgen.py: trivial change to remove C++ compiler warnings