mesa.git
4 years agolima: always add texture bo to submit
Qiang Yu [Tue, 11 Feb 2020 02:32:38 +0000 (10:32 +0800)]
lima: always add texture bo to submit

No matter texture desc change, we need to add texture to submit.
Otherwise texture may be freed before submit finish.

Reviewed-by: Vasily Khoruzhick <anarsoul@gmail.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3755>

4 years agolima: use util_copy_framebuffer_state
Qiang Yu [Fri, 7 Feb 2020 03:12:09 +0000 (11:12 +0800)]
lima: use util_copy_framebuffer_state

Use this helper to replace self written code.

Reviewed-by: Vasily Khoruzhick <anarsoul@gmail.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3755>

4 years agolima: remove definition of lima_is_scanout
Qiang Yu [Thu, 6 Feb 2020 12:20:28 +0000 (20:20 +0800)]
lima: remove definition of lima_is_scanout

There is no implementation of this function.

Reviewed-by: Vasily Khoruzhick <anarsoul@gmail.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3755>

4 years agopan/decode: Remove extraneous newline
Alyssa Rosenzweig [Wed, 12 Feb 2020 02:50:04 +0000 (21:50 -0500)]
pan/decode: Remove extraneous newline

pandecode_log already does this.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3835>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3835>

4 years agopan/midgard: Use fprintf instead of printf for constants
Alyssa Rosenzweig [Thu, 13 Feb 2020 22:14:05 +0000 (17:14 -0500)]
pan/midgard: Use fprintf instead of printf for constants

I was wondering where those constants disappeared to :-)

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Fixes: 968f36d1fc0 ("pan/midgard: Support disassembling to a file")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3835>

4 years agopan/midgard: Don't crash with constants on unknown ops
Alyssa Rosenzweig [Thu, 13 Feb 2020 22:12:51 +0000 (17:12 -0500)]
pan/midgard: Don't crash with constants on unknown ops

Just use a dummy name instead.. we can't know a priori what type an
unknown op will consume, but we don't want to dereference a null
pointer.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Fixes: 24360966ab3 ("panfrost/midgard: Prettify embedded constant
prints")

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3835>

4 years agopan/midgard: Identify stack barrier flag
Alyssa Rosenzweig [Thu, 13 Feb 2020 12:41:38 +0000 (07:41 -0500)]
pan/midgard: Identify stack barrier flag

In case thread local storage is used.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3835>

4 years agopan/midgard: Set xyzx swizzle for load_compute_arg
Alyssa Rosenzweig [Wed, 12 Feb 2020 13:39:29 +0000 (08:39 -0500)]
pan/midgard: Set xyzx swizzle for load_compute_arg

Probably harmless but the w component doesn't appear valid so let's
match the blob... one less bit to be nervous about.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3835>

4 years agopan/midgard: Infer tags entirely
Alyssa Rosenzweig [Wed, 12 Feb 2020 02:43:43 +0000 (21:43 -0500)]
pan/midgard: Infer tags entirely

We're so close, again marking off a few edge cases is enough to allow us
to omit this data entirely. Woot!

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3835>

4 years agopan/midgard: Imply next tags
Alyssa Rosenzweig [Wed, 12 Feb 2020 02:37:18 +0000 (21:37 -0500)]
pan/midgard: Imply next tags

As long as we can disambiguate a few edge cases, we can imply next tags
entirely which cleans up the disassembly a fair bit (though not as much
as implying tags entirely would -- we'll get there!)

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3835>

4 years agopan/midgard: Overhaul tag handling
Alyssa Rosenzweig [Wed, 12 Feb 2020 02:20:30 +0000 (21:20 -0500)]
pan/midgard: Overhaul tag handling

We unify disparate metadata about tags into a single structure to ensure
information is not left out.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3835>

4 years agopan/midgard: Improve barrier disassembly
Alyssa Rosenzweig [Tue, 11 Feb 2020 20:58:18 +0000 (15:58 -0500)]
pan/midgard: Improve barrier disassembly

Just move some state from unknowns to actual keywords.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3835>

4 years agopan/midgard: Use dummy tag for empty shaders
Alyssa Rosenzweig [Tue, 4 Feb 2020 14:34:11 +0000 (09:34 -0500)]
pan/midgard: Use dummy tag for empty shaders

Fixes INSTR_INVALID_ENC in dEQP-GLES31.functional.compute.basic.empty

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3835>

4 years agopan/midgard: Fix 32/64 mixed swizzle packing
Alyssa Rosenzweig [Tue, 4 Feb 2020 14:29:59 +0000 (09:29 -0500)]
pan/midgard: Fix 32/64 mixed swizzle packing

Occurs in SSBO address computation.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3835>

4 years agopan/midgard: Allow jumping out of a shader
Alyssa Rosenzweig [Tue, 4 Feb 2020 14:28:06 +0000 (09:28 -0500)]
pan/midgard: Allow jumping out of a shader

This comes up as a `return;` instruction in a compute shader. We need to
use the special tag 1 to signify "break". Fixes numerous
INSTR_INVALID_ENC faults in dEQP-GLES31.functional.compute.basic.*

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3835>

4 years agopan/midgard: Implement barriers
Alyssa Rosenzweig [Tue, 4 Feb 2020 01:23:41 +0000 (20:23 -0500)]
pan/midgard: Implement barriers

Barriers execute on the texture pipeline on Midgard, so let's
tentatively handle barrier() as conservatively as possible (forcing
memory barriers of both buffers and shared memory). Implementation isn't
quite there yet -- it doesn't look at interactions of adjacent barriers
like it's supposed to -- but the core is there.

Fixes dEQP-GLES31.functional.compute.basic.ssbo_local_barrier_single_invocation

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3835>

4 years agopan/midgard: Fix swizzles harder
Alyssa Rosenzweig [Tue, 4 Feb 2020 00:21:59 +0000 (19:21 -0500)]
pan/midgard: Fix swizzles harder

Just for disassembly for now~

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3835>

4 years agopan/midgard: Fix missing prefixes
Alyssa Rosenzweig [Mon, 3 Feb 2020 20:12:24 +0000 (15:12 -0500)]
pan/midgard: Fix missing prefixes

I was wondering where those were going... :)

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Fixes: c1952779d68 ("pan/decode: Dump to a file")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3835>

4 years agopan/midgard: Track pressure when scheduling ld/st
Alyssa Rosenzweig [Mon, 3 Feb 2020 19:55:58 +0000 (14:55 -0500)]
pan/midgard: Track pressure when scheduling ld/st

Fixes RA failure in
dEQP-GLES31.functional.shaders.builtin_functions.common.modf.* (which
uses multiple indirect SSBO writes)

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3835>

4 years agopanfrost: Allocate RAM backing of shared memory
Alyssa Rosenzweig [Thu, 6 Feb 2020 19:29:42 +0000 (14:29 -0500)]
panfrost: Allocate RAM backing of shared memory

Unlike other GPUs, Mali does not have dedicated shared memory for
compute workloads. Instead, we allocate shared memory (backed to RAM),
and the general memory access functions have modes to access shared
memory (essentially, think of these modes as adding this allocates base
+ workgroupid * stride  in harder). So let's allocate enough memory
based on the shared_size parameter and supply it.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3835>

4 years agopanfrost: Rename unknown2_8 to padding
Alyssa Rosenzweig [Mon, 10 Feb 2020 13:56:33 +0000 (08:56 -0500)]
panfrost: Rename unknown2_8 to padding

It's zero everywhere.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3835>

4 years agopanfrost: Rename bifrost_framebuffer->mali_framebuffer
Alyssa Rosenzweig [Mon, 10 Feb 2020 13:51:37 +0000 (08:51 -0500)]
panfrost: Rename bifrost_framebuffer->mali_framebuffer

(And bifrost_fb_extra to mali_framebuffer_extra, bifrost_render_target
to mali_render_target)

These structures are the norm on midgard t760+, drop the bifrost names,
it's silly... unrelated to the rest of the series but while I'm messing
with pandecode and cleaning up bifrost abstractions, might as well.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3835>

4 years agopanfrost: Unify bifrost_scratchpad with mali_shared_memory
Alyssa Rosenzweig [Mon, 10 Feb 2020 13:47:09 +0000 (08:47 -0500)]
panfrost: Unify bifrost_scratchpad with mali_shared_memory

It looks like these are the same structure, so this allows us to reuse
mali_shared_memory across architectures, and dispels with the
Bifrost-specific mystery of the scratchpads... nothing so mysterious
after all, just stack.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3835>

4 years agopanfrost: Identify mali_shared_memory structure
Alyssa Rosenzweig [Wed, 5 Feb 2020 20:58:28 +0000 (15:58 -0500)]
panfrost: Identify mali_shared_memory structure

This small structure is used to configure shared memory and stack for
compute shaders, and is also present at the beginning of framebuffer
descriptors. Let's factor it out.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3835>

4 years agopanfrost: Ensure compute shader_meta is zeroed
Alyssa Rosenzweig [Tue, 4 Feb 2020 19:24:44 +0000 (14:24 -0500)]
panfrost: Ensure compute shader_meta is zeroed

In theory the hardware doesn't care but it'll make for easier traces.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3835>

4 years agopanfrost: Update comment about magic number relating to barriers
Alyssa Rosenzweig [Tue, 4 Feb 2020 19:15:27 +0000 (14:15 -0500)]
panfrost: Update comment about magic number relating to barriers

It's a complicated story. But from what I can tell, in GL compute
without barriers, the blob is able to redistribute the workgroups in
various ways (that are not yet understood), whereas with barriers it
cannot redistribute anything, which accounts for erratic workgroup
packing without barriers.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3835>

4 years agoci: bump debian image and change llvm deps to 8
Dave Airlie [Fri, 14 Feb 2020 05:47:20 +0000 (15:47 +1000)]
ci: bump debian image and change llvm deps to 8

v3: remove version in a few places (Michel)

Reviewed-by: Michel Dänzer <mdaenzer@redhat.com>
Reviewed-by: Adam Jackson <ajax@redhat.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3805>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3805>

4 years agogallivm/s390: fix pass init order on s390 with llvm 8 (v2)
Dave Airlie [Thu, 13 Feb 2020 00:35:51 +0000 (10:35 +1000)]
gallivm/s390: fix pass init order on s390 with llvm 8 (v2)

llvm 8 has some missing pass dependencies, fix the s390 case
as well.

v2: add ARM also (Michel)

Reviewed-by: Michel Dänzer <mdaenzer@redhat.com>
Reviewed-by: Adam Jackson <ajax@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3805>

4 years agoiris: Trim "../../src/gallium/drivers/iris/" out of debug dump filenames
Kenneth Graunke [Tue, 11 Feb 2020 19:36:09 +0000 (11:36 -0800)]
iris: Trim "../../src/gallium/drivers/iris/" out of debug dump filenames

Easier to read.

v2: Also trim "/iris/" (Jordan Justen)

Acked-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3830>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3830>

4 years agoiris: Dump frame markers with INTEL_DEBUG=submit
Kenneth Graunke [Tue, 11 Feb 2020 19:21:47 +0000 (11:21 -0800)]
iris: Dump frame markers with INTEL_DEBUG=submit

Now you can see which batches go with which frames.

Acked-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3830>

4 years agogallium/cso_hash: remove another layer of pointer indirection
Marek Olšák [Wed, 22 Jan 2020 03:53:13 +0000 (22:53 -0500)]
gallium/cso_hash: remove another layer of pointer indirection

Convert this:

    struct cso_hash {
       union {
          struct cso_hash_data *d;
          struct cso_node      *e;
       } data;
    };

to this:

    struct cso_hash {
       struct cso_hash_data data;
       struct cso_node      *end;
    };

1) data is not a pointer anymore.
2) "end" points to "data" and acts as the end of the linked list.
3) This code is still crazy.

Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3829>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3829>

4 years agogallium/cso_hash: cosmetic changes, no behavior changes
Marek Olšák [Wed, 22 Jan 2020 02:47:47 +0000 (21:47 -0500)]
gallium/cso_hash: cosmetic changes, no behavior changes

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3829>

4 years agogallium/cso_hash: remove always constant variable nodeSize
Marek Olšák [Wed, 22 Jan 2020 01:18:54 +0000 (20:18 -0500)]
gallium/cso_hash: remove always constant variable nodeSize

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3829>

4 years agogallium/cso_hash: make cso_hash declared within structures instead of alloc'd
Marek Olšák [Wed, 22 Jan 2020 01:10:43 +0000 (20:10 -0500)]
gallium/cso_hash: make cso_hash declared within structures instead of alloc'd

This removes one level of indirection.

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3829>

4 years agogallium/cso_hash: inline a bunch of functions
Marek Olšák [Wed, 22 Jan 2020 00:46:34 +0000 (19:46 -0500)]
gallium/cso_hash: inline a bunch of functions

I'm probably not getting anything out of this, but it's harmless.

Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3829>

4 years agogallium/u_vbuf: adjust the heuristic for unrolling indices
Marek Olšák [Tue, 21 Jan 2020 00:57:05 +0000 (19:57 -0500)]
gallium/u_vbuf: adjust the heuristic for unrolling indices

This improves performance in the first subtest of Viewperf11/Catia by 10%.

Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3829>

4 years agogallium/u_upload_mgr: don't do align twice in the u_upload_alloc fast path
Marek Olšák [Fri, 24 Jan 2020 01:40:35 +0000 (20:40 -0500)]
gallium/u_upload_mgr: don't do align twice in the u_upload_alloc fast path

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3829>

4 years agogallium/u_upload_mgr: reduce dereferences by adding buffer_size
Marek Olšák [Fri, 24 Jan 2020 01:35:48 +0000 (20:35 -0500)]
gallium/u_upload_mgr: reduce dereferences by adding buffer_size

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3829>

4 years agost/mesa: simplify releasing the current attrib buffer
Marek Olšák [Fri, 24 Jan 2020 02:13:44 +0000 (21:13 -0500)]
st/mesa: simplify releasing the current attrib buffer

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3829>

4 years agost/mesa: make st_setup_current static
Marek Olšák [Fri, 24 Jan 2020 02:10:06 +0000 (21:10 -0500)]
st/mesa: make st_setup_current static

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3829>

4 years agost/mesa: change some loops from while to do..while in st_atom_array.c
Marek Olšák [Fri, 24 Jan 2020 02:08:30 +0000 (21:08 -0500)]
st/mesa: change some loops from while to do..while in st_atom_array.c

Reviewed-by: Mathias Fröhlich <mathias.froehlich@web.de>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3829>

4 years agost/mesa: simplify determination whether a draw needs min/max index
Marek Olšák [Thu, 23 Jan 2020 03:38:09 +0000 (22:38 -0500)]
st/mesa: simplify determination whether a draw needs min/max index

Reviewed-by: Mathias Fröhlich <mathias.froehlich@web.de>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3829>

4 years agost/mesa: simplify determination whether a draw has user vertex buffers
Marek Olšák [Thu, 23 Jan 2020 03:23:09 +0000 (22:23 -0500)]
st/mesa: simplify determination whether a draw has user vertex buffers

Reviewed-by: Mathias Fröhlich <mathias.froehlich@web.de>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3829>

4 years agost/mesa: always inline the code setting non-64bit vertex elements
Marek Olšák [Tue, 21 Jan 2020 03:14:11 +0000 (22:14 -0500)]
st/mesa: always inline the code setting non-64bit vertex elements

Reviewed-by: Mathias Fröhlich <mathias.froehlich@web.de>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3829>

4 years agomesa: remove unused _mesa_draw_indirect
Marek Olšák [Tue, 4 Feb 2020 01:53:52 +0000 (20:53 -0500)]
mesa: remove unused _mesa_draw_indirect

All drivers that expose ARB_draw_indirect also set the driver callback.

Reviewed-by: Mathias Fröhlich <mathias.froehlich@web.de>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3829>

4 years agomesa: translate into gallium vertex formats in mesa/main
Marek Olšák [Tue, 21 Jan 2020 03:06:30 +0000 (22:06 -0500)]
mesa: translate into gallium vertex formats in mesa/main

Reviewed-by: Mathias Fröhlich <mathias.froehlich@web.de>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3829>

4 years agointel/fs/gen7+: Implement discard/demote for SIMD32 programs.
Francisco Jerez [Sun, 5 Jan 2020 00:16:24 +0000 (16:16 -0800)]
intel/fs/gen7+: Implement discard/demote for SIMD32 programs.

At this point this simply involves fixing the initialization of the
sample mask flag register to take the right dispatch mask from the
thread payload, and fixing sample_mask_reg() to return f1.1 for the
second half of a SIMD32 thread.  This improves Manhattan 3.1
performance by 2.4%±0.31% (N>40) on my ICL with SIMD32 enabled
relative to falling back to SIMD16 for the shaders that use discard.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
4 years agointel/fs: Return consistent UW types from sample_mask_reg() in fragment shaders.
Francisco Jerez [Sun, 5 Jan 2020 00:11:23 +0000 (16:11 -0800)]
intel/fs: Return consistent UW types from sample_mask_reg() in fragment shaders.

In SIMD32 programs that don't use discard, the upper 16 bits of the UD
result of sample_mask_reg() don't contain the sample mask of the upper
16 channels as one would expect.  Stop pretending we are returning a
valid 32-bit mask.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
4 years agointel/fs: Refactor predication on sample mask into helper function.
Francisco Jerez [Sun, 5 Jan 2020 00:08:16 +0000 (16:08 -0800)]
intel/fs: Refactor predication on sample mask into helper function.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
4 years agointel/fs/gen7+: Swap sample mask flag register and FIND_LIVE_CHANNEL temporary.
Francisco Jerez [Sat, 4 Jan 2020 23:48:07 +0000 (15:48 -0800)]
intel/fs/gen7+: Swap sample mask flag register and FIND_LIVE_CHANNEL temporary.

FIND_LIVE_CHANNEL was using f1.0-f1.1 as temporary flag register on
Gen7, instead use f0.0-f0.1.  In order to avoid collision with the
discard sample mask, move the latter to f1.0-f1.1.  This makes room
for keeping track of the sample mask of the second half of SIMD32
programs that use discard.

Note that some MOVs of the sample mask into f1.0 become redundant now
in lower_surface_logical_send() and lower_a64_logical_send().

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>x
4 years agointel/fs: Use helper for discard sample mask flag subregister number.
Francisco Jerez [Sat, 4 Jan 2020 22:32:09 +0000 (14:32 -0800)]
intel/fs: Use helper for discard sample mask flag subregister number.

Use it instead of hard-coding f0.1 for the sample mask of programs
that use discard.  This will make the task easier when we replace f0.1
with another flag register location in order to support discard with
SIMD32 shaders.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
4 years agointel/fs: Make sample_mask_reg() local to brw_fs.cpp and use it in more places.
Francisco Jerez [Thu, 23 Jan 2020 20:50:50 +0000 (12:50 -0800)]
intel/fs: Make sample_mask_reg() local to brw_fs.cpp and use it in more places.

It's only really useful there.  This will avoid confusion with another
helper with a similar purpose I'm about to introduce that will be
useful in multiple files from the FS back-end.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
4 years agointel/fs/gen11: Work around dual-source blending hangs in combination with SIMD32.
Francisco Jerez [Tue, 21 Jan 2020 21:55:36 +0000 (13:55 -0800)]
intel/fs/gen11: Work around dual-source blending hangs in combination with SIMD32.

The SIMD8 dual-source blending framebuffer write messages seem to have
trouble releasing the pixel scoreboard dependency in SIMD32 dispatch
mode, which leads to hangs.  I have a better workaround for this which
doesn't involve disabling SIMD32 when dual-source blending is enabled,
but I'm still investigating some issues with it.  Limit the dispatch
width to SIMD16 in such cases for the moment in order to make the CI
happy on ICL with SIMD32 fragment shaders enabled.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
4 years agointel/fs: Set src0 alpha present bit in header when provided in message payload.
Francisco Jerez [Fri, 27 Dec 2019 22:14:06 +0000 (14:14 -0800)]
intel/fs: Set src0 alpha present bit in header when provided in message payload.

Currently the "Source0 Alpha Present to RenderTarget" bit of the RT
write message header is derived from brw_wm_prog_data::replicate_alpha.
However the src0_alpha payload is provided anytime it's specified to
the logical message.  This could theoretically lead to an
inconsistency if somebody provided a src0_alpha value while
brw_wm_prog_data::replicate_alpha was false, as I'm planning to do in
a future commit in order to implement a hardware workaround.

Instead calculate the header bit based on whether a src0_alpha value
was provided to the logical message, which guarantees the same
behavior on pre-ICL and ICL+ (the latter used an extended descriptor
bit for this which didn't suffer from the same issue).  Remove the
brw_wm_prog_data::replicate_alpha flag.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
4 years agointel/fs/gen12: Workaround data coherency issues due to broken NoMask control flow.
Francisco Jerez [Fri, 24 Jan 2020 23:09:52 +0000 (15:09 -0800)]
intel/fs/gen12: Workaround data coherency issues due to broken NoMask control flow.

Together with the fixup_nomask_control_flow() pass introduced in a
previous patch, this implements a less invasive alternative to the
workaround documented in the hardware spec for GEN:BUG:1407528679,
which doesn't involve disabling structured control flow.

Under some conditions Gen12 hardware can end up executing a BB with
all channels disabled, which will lead to the execution of any NoMask
instructions in it, even though any execution-masked instructions will
be correctly shot down.  This could break assumptions of the SWSB pass
if the data computed by a NoMask instruction is synchronized against
by using an SWSB annotation baked into a regular execution-masked
instruction, since the first (NoMask) instruction may be executed
redundantly by the hardware, even though the second will correctly be
shot down, potentially leading to a RaW or WaW hazard if a third
instruction subsequently accesses the destination register of the
first instruction.

Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Cc: 20.0 <mesa-stable@lists.freedesktop.org>
4 years agointel/fs/gen12: Fixup/simplify SWSB annotations of SIMD32 scratch writes.
Francisco Jerez [Fri, 24 Jan 2020 06:27:21 +0000 (22:27 -0800)]
intel/fs/gen12: Fixup/simplify SWSB annotations of SIMD32 scratch writes.

Found by inspection.  Existing code was trying to avoid assuming that
an SBID had been assigned to the virtual instruction, but
synchronizing the header setup with respect to the previous SIMD16
SEND by using SYNC.ALLRD doesn't really seem possible unless the SEND
instruction had been assigned an SBID.  Assert-fail instead if no SBID
has been allocated.

Fixes: 15e3a0d9d264becc "intel/eu/gen12: Set SWSB annotations in hand-crafted assembly."
Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Cc: 20.0 <mesa-stable@lists.freedesktop.org>
4 years agointel/fs/gen12: Workaround unwanted SEND execution due to broken NoMask control flow.
Francisco Jerez [Fri, 24 Jan 2020 06:55:33 +0000 (22:55 -0800)]
intel/fs/gen12: Workaround unwanted SEND execution due to broken NoMask control flow.

This is a less invasive alternative to the workaround documented in
the hardware spec for GEN:BUG:1407528679, which doesn't involve
disabling structured control flow (it's unlikely that switching to
GOTO/JOIN would have actually fixed the problem anyway).

Under some conditions Gen12 hardware can end up executing a BB with
all channels disabled, which will lead to the execution of any NoMask
instructions in it, even though any execution-masked instructions will
be correctly shot down.  This may break assumptions of some NoMask
SEND messages whose descriptor depends on data generated by live
invocations of the shader.

This avoids the problem by predicating certain instructions on an ANY
horizontal predicate that makes sure that their execution is omitted
when all channels of the program are disabled.  The shader-db impact
of this patch seems to be minimal:

total instructions in shared programs: 17169833 -> 17169913 (0.00%)
instructions in affected programs: 30663 -> 30743 (0.26%)
helped: 0
HURT: 42

total cycles in shared programs: 336966176 -> 336968568 (0.00%)
cycles in affected programs: 2367290 -> 2369682 (0.10%)
helped: 0
HURT: 13

Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Cc: 20.0 <mesa-stable@lists.freedesktop.org>
4 years agointel/fs: Add virtual instruction to load mask of live channels into flag register.
Francisco Jerez [Fri, 24 Jan 2020 07:01:32 +0000 (23:01 -0800)]
intel/fs: Add virtual instruction to load mask of live channels into flag register.

Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Cc: 20.0 <mesa-stable@lists.freedesktop.org>
4 years agointel/fs/gen7: Fix fs_inst::flags_written() for SHADER_OPCODE_FIND_LIVE_CHANNEL.
Francisco Jerez [Fri, 24 Jan 2020 07:00:54 +0000 (23:00 -0800)]
intel/fs/gen7: Fix fs_inst::flags_written() for SHADER_OPCODE_FIND_LIVE_CHANNEL.

We need to pass a width of 32 since the opcode bashes the whole f1.0
register on IVB.  This is unlikely to have caused problems since f1.0
is largely unused currently.  That's likely to change soon though,
even on platforms other than Gen7.

Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Cc: 20.0 <mesa-stable@lists.freedesktop.org>
4 years agointel/fs/cse: Make HALT instruction act as CSE barrier.
Francisco Jerez [Fri, 24 Jan 2020 06:01:00 +0000 (22:01 -0800)]
intel/fs/cse: Make HALT instruction act as CSE barrier.

Found by inspection.  This seems particularly likely to cause problems
with instructions dependent on the current execution mask like
SHADER_OPCODE_FIND_LIVE_CHANNEL or the FS_OPCODE_LOAD_LIVE_CHANNELS
instruction I'm about to introduce, but one could imagine it leading
to data corruption if CSE ever managed to combine two instructions
before and after the FS_OPCODE_PLACEHOLDER_HALT, since the one before
may not be executed for some channels.

Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Cc: 20.0 <mesa-stable@lists.freedesktop.org>
4 years agolima/parser: Extend rsw parsing showing strings instead of numbers
Andreas Baierl [Thu, 30 Jan 2020 09:37:55 +0000 (10:37 +0100)]
lima/parser: Extend rsw parsing showing strings instead of numbers

Reviewed-by: Vasily Khoruzhick <anarsoul@gmail.com>
Signed-off-by: Andreas Baierl <ichgeh@imkreisrum.de>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3807>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3807>

4 years agoradeonsi: don't wait for shader compilation to finish when destroying a context
Marek Olšák [Wed, 12 Feb 2020 19:55:27 +0000 (14:55 -0500)]
radeonsi: don't wait for shader compilation to finish when destroying a context

This was a hack for glsl_types deinitialization and it predates the proper
fix, which was the addition of glsl_type_singleton_decref.

This fixes a crash when the context is destroyed via the atexit handler.

Cc: 19.3 20.0 <mesa-stable@lists.freedesktop.org>
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3800>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3800>

4 years agoegl: directly access static members instead of using _egl{Get,Set}ConfigKey()
Eric Engestrom [Thu, 13 Feb 2020 15:53:03 +0000 (15:53 +0000)]
egl: directly access static members instead of using _egl{Get,Set}ConfigKey()

This function is meant for when the attribute is unknown at compile-time
(eg. user-specified), but in all these cases it is much simpler to just
read/write the member directly.

Suggested-by: Emil Velikov <emil.velikov@collabora.com>
Signed-off-by: Eric Engestrom <eric@engestrom.ch>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3816>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3816>

4 years agofreedreno/a6xx: document some unknown bits
Jonathan Marek [Wed, 12 Feb 2020 02:08:58 +0000 (21:08 -0500)]
freedreno/a6xx: document some unknown bits

Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Reviewed-by: Rob Clark <robdclark@gmail.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3814>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3814>

4 years agofreedreno: name sysmem color/depth flush events
Jonathan Marek [Mon, 10 Feb 2020 18:51:36 +0000 (13:51 -0500)]
freedreno: name sysmem color/depth flush events

Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Reviewed-by: Connor Abbott <cwabbott0@gmail.com>
Reviewed-by: Rob Clark <robdclark@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3814>

4 years agopanfrost: Simplify swizzle translation
Alyssa Rosenzweig [Fri, 14 Feb 2020 12:49:25 +0000 (07:49 -0500)]
panfrost: Simplify swizzle translation

It lines up anyway, and Gallium shouldn't change this. (And if it does,
we'll deal with that then since CI would start failing.)

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3824>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3824>

4 years agopanfrost: Inline panfrost_get_default_swizzle
Icecream95 [Fri, 14 Feb 2020 07:22:38 +0000 (20:22 +1300)]
panfrost: Inline panfrost_get_default_swizzle

This commit replaces panfrost_get_default_swizzle with an inlined
implementation where the returned values can be determined at compile
time.

According to perf, this previously used about 2% CPU for Openarena.

Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3824>

4 years agospirv2nir: Add kernel spirv support
Elie Tournier [Mon, 3 Feb 2020 13:44:59 +0000 (13:44 +0000)]
spirv2nir: Add kernel spirv support

Signed-off-by: Elie Tournier <elie.tournier@collabora.com>
Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3678>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3678>

4 years agospirv2nir: print nir shader if translation succed
Elie Tournier [Mon, 3 Feb 2020 15:33:34 +0000 (15:33 +0000)]
spirv2nir: print nir shader if translation succed

Signed-off-by: Elie Tournier <elie.tournier@collabora.com>
Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3678>

4 years agozink: do not use SpvDimRect
Erik Faye-Lund [Tue, 4 Feb 2020 11:20:36 +0000 (12:20 +0100)]
zink: do not use SpvDimRect

Vulkan doesn't support SpvDimRect. But we don't need to pass this at
all, as we already mark the sampler as un-normalized.

Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3764>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3764>

4 years agolima: handle early-z and pixel kill better
Vasily Khoruzhick [Sat, 8 Feb 2020 10:05:24 +0000 (02:05 -0800)]
lima: handle early-z and pixel kill better

[1] calls bit 12 of aux0 'pixel kill' which is likely forward pixel
kill described in [2]. Blob sets this bit if early-z is enabled and
blending is disabled and colormask is RGBA.

Bit 8 seems to be always enabled with bit 9 (early-z).

Let's mimic blob behavior.

[1] https://web.archive.org/web/20171026123213/http://limadriver.org/Render_State/
[2] https://community.arm.com/developer/tools-software/graphics/b/blog/posts/killing-pixels---a-new-optimization-for-shading-on-arm-mali-gpus

Reviewed-by: Andreas Baierl <ichgeh@imkreisrum.de>
Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3754>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3754>

4 years agogitlab-ci: Add three more dEQP-GLES31 tests to softpipe skips
Michel Dänzer [Thu, 13 Feb 2020 10:43:03 +0000 (11:43 +0100)]
gitlab-ci: Add three more dEQP-GLES31 tests to softpipe skips

These have randomly flipped lately, see e.g.
https://gitlab.freedesktop.org/mesa/mesa/-/jobs/1620056
https://gitlab.freedesktop.org/daenzer/mesa/-/jobs/1621374
https://gitlab.freedesktop.org/daenzer/mesa/-/jobs/1622156

Reviewed-by: Eric Anholt <eric@anholt.net>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3811>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3811>

4 years agogitlab-ci: Sort random failure softpipe skips
Michel Dänzer [Thu, 13 Feb 2020 10:44:24 +0000 (11:44 +0100)]
gitlab-ci: Sort random failure softpipe skips

Reviewed-by: Eric Anholt <eric@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3811>

4 years agodocs/new_features: empty the feature list for the 20.1 cycle
Samuel Pitoiset [Wed, 12 Feb 2020 16:12:20 +0000 (17:12 +0100)]
docs/new_features: empty the feature list for the 20.1 cycle

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Dylan Baker <dylan@pnwbakers.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3793>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3793>

4 years agoradv: remove unnecessary RADV_DEBUG=nobatchchain option
Samuel Pitoiset [Wed, 12 Feb 2020 15:49:45 +0000 (16:49 +0100)]
radv: remove unnecessary RADV_DEBUG=nobatchchain option

It was used in the past but nowadays chained submissions work fine.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3791>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3791>

4 years agoglsl: fix gl_nir_set_uniform_initializers() for image arrays
Timothy Arceri [Mon, 10 Feb 2020 00:22:32 +0000 (11:22 +1100)]
glsl: fix gl_nir_set_uniform_initializers() for image arrays

The if was incorrectly checking for an image type on what could
be an array of images. Here we change it to use the type stored
in uniform storage which has already been stripped of arrays,
this is what the above code for samplers does also.

Fixes: 2bf91733fcb5 ("nir/linker: Set the uniform initial values")
Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3757>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3757>

4 years agointel/tools: Update aubinator_error_decode.
Rafael Antognolli [Wed, 12 Feb 2020 23:18:15 +0000 (15:18 -0800)]
intel/tools: Update aubinator_error_decode.

"ringbuffer" is now called only "ring" in the error state.

v2: Keep compatible with old error state (Lionel).
v3: Also update "gtt_offset" -> "batch".

Closes: https://gitlab.freedesktop.org/drm/intel/issues/1206
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
4 years agofreedreno: allow INVALID modifier
Rob Clark [Thu, 13 Feb 2020 18:26:08 +0000 (10:26 -0800)]
freedreno: allow INVALID modifier

Re-allow INVALID modifier in import path.  The legacy import path
(createImageFromFds()), which is used by android, uses the INVALID
modifier.  Previously we would ignore this and just setup the imported
buffer as linear.  Restore this behavior to unbreak the legacy import
path.

Fixes: 9891062642a freedreno/a6xx: Implement layout for DRM_FORMAT_MOD_QCOM_COMPRESSED
Signed-off-by: Rob Clark <robdclark@chromium.org>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3817>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3817>

4 years agointel/isl: Switch to R8_UNORM format for compatiblity
Sagar Ghuge [Tue, 4 Feb 2020 05:58:50 +0000 (21:58 -0800)]
intel/isl: Switch to R8_UNORM format for compatiblity

Gen12 added CCS_E support for A8_UNORM. Intercept A8_UNORM format and
switch to R8_UNORM, as both share the same aux map format encoding so
they are compatible.

Fixes Piglit's ext_framebuffer_multisample-formats all_samples, which
was hitting an assert about A8_UNORM and R8_UINT not being CCS_E
compatible formats.

v2: Add gen check (Kenneth Graunke)

v3: Intercept A8_UNORM and set format to R8_UNORM (Jason Ekstrand)

v4:
- Remove gen check and move block little bit down (Jason Ekstrand)

Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3719>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3719>

4 years agointel/isl: Move get_format_encoding function to isl
Sagar Ghuge [Tue, 4 Feb 2020 05:57:38 +0000 (21:57 -0800)]
intel/isl: Move get_format_encoding function to isl

Move get_format_encoding function to isl and rename to
isl_get_aux_map_format_encoding.

v2:
- Rename isl_get_aux_map_format_encoding to
  isl_format_get_aux_map_encoding (Jason Ekstrand)

Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
Suggested-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3719>

4 years agoRevert "gitlab-ci: disable a630 tests as mesa-cheza is down (again)"
Fritz Koenig [Wed, 12 Feb 2020 19:31:24 +0000 (19:31 +0000)]
Revert "gitlab-ci: disable a630 tests as mesa-cheza is down (again)"

This reverts commit 18657c0c0a9074d3dfc0763b396929bcf34f71b4

Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3804>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3804>

4 years agofreedreno/a6xx: fix Z24_UNORM_S8_UINT_AS_R8G8B8A8
Jonathan Marek [Wed, 12 Feb 2020 23:40:57 +0000 (18:40 -0500)]
freedreno/a6xx: fix Z24_UNORM_S8_UINT_AS_R8G8B8A8

CI didn't run so missed this.

Note previously had :
   texfmt = TFMT6_Z24_UNORM_S8_UINT
   rbfmt = RB6_Z24_UNORM_S8_UINT_AS_R8G8B8A8

which are both now FMT6_Z24_UNORM_S8_UINT_AS_R8G8B8A8

Fixes: 18786cc7d55 ("freedreno/a6xx: use single format enum")
Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3804>

4 years agoiris: add support INTEL_blackhole_render
Lionel Landwerlin [Thu, 5 Dec 2019 12:49:12 +0000 (14:49 +0200)]
iris: add support INTEL_blackhole_render

v2: Use a software mechanism to manage blackhole state

v3: s/iris_batchbuffer/iris_batch/ (Ken)

v4: Fixup state transition mistake (Ken/Lionel)

v5: Cleanup iris_batch_flush (Ken)

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/2964>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/2964>

4 years agost: add support for INTEL_blackhole_render
Lionel Landwerlin [Thu, 5 Dec 2019 12:46:51 +0000 (14:46 +0200)]
st: add support for INTEL_blackhole_render

Adding a new CSO proved to be fairly difficult especially because this
extension affect draw/dispatch/blit alike.

Instead this change passes the state of the noop into the entry points
emitting the operations affected.

v2: Fix assert in default pipe caps

v3: Drop whitespace changes (Ken)

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/2964>

4 years agoi965: enable INTEL_blackhole_render
Lionel Landwerlin [Fri, 2 Mar 2018 14:46:26 +0000 (14:46 +0000)]
i965: enable INTEL_blackhole_render

v2: condition the extension on context isolation support from the
    kernel (Chris)

v3: (Lionel)

    The initial version of this change used a feature of the Gen7+
    command parser to turn the primitive instructions into no-ops.
    Unfortunately this doesn't play well with how we're using the
    hardware outside of the user submitted commands. For example
    resolves are implicit operations which should not be turned into
    no-ops as part of the previously submitted commands (before
    blackhole_render is enabled) might not be disabled. For example
    this sequence :

       glClear();
       glEnable(GL_BLACKHOLE_RENDER_INTEL);
       glDrawArrays(...);
       glReadPixels(...);
       glDisable(GL_BLACKHOLE_RENDER_INTEL);

    While clear has been emitted outside the blackhole render, it
    should still be resolved properly in the read pixels. Hence we
    need to be more selective and only disable user submitted
    commands.

    This v3 manually turns primitives into MI_NOOP if blackhole render
    is enabled. This lets us enable this feature on any platform.

v4: Limit support to gen7.5+ (Lionel)

v5: Enable Gen7.5 support again, requires a kernel update of the
    command parser (Lionel)

v6: Disable Gen7.5 again... Kernel devs want these patches landed
    before they accept the kernel patches to whitelist INSTPM (Lionel)

v7: Simplify change by never holding noop (there was a shortcoming in the test not considering fast clears)
    Only program register using MI_LRI (Lionel)

v8: Switch to software managed blackhole (BDW hangs on compute batches...)

v9: Simplify the noop state tracking (Lionel)

v10: Don't modify flush function (Ken)

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> (v8)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/2964>

4 years agomesa: add INTEL_blackhole_render
Lionel Landwerlin [Fri, 2 Mar 2018 14:45:56 +0000 (14:45 +0000)]
mesa: add INTEL_blackhole_render

v2: Implement missing Enable/Disable (Emil)

v3: Drop unused NewIntelBlackholeRender (Ken)

v4: Bring back NewIntelBlackholeRender as i965 implementation uses it
    again (Lionel)

v5: Drop atom (Ken)

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/2964>

4 years agoRevert "st/va: Convert interlaced NV12 to progressive"
Thong Thai [Thu, 13 Feb 2020 16:03:12 +0000 (11:03 -0500)]
Revert "st/va: Convert interlaced NV12 to progressive"

This reverts commit 2add63060b51ea2ae432d10e1bd52d6cc0a4dcbb.

Closes: https://gitlab.freedesktop.org/mesa/mesa/issues/2454
Fixes: 2add63060b51 "st/va: Convert interlaced NV12 to progressive"
Signed-off-by: Thong Thai <thong.thai@amd.com>
Acked-by: Leo Liu <leo.liu@amd.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3815>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3815>

4 years agoanv: Reject modifiers on depth/stencil formats
Jason Ekstrand [Wed, 12 Feb 2020 16:22:39 +0000 (10:22 -0600)]
anv: Reject modifiers on depth/stencil formats

6790397346cc added code which attempts to reject modifiers on
depth/stencil formats but it was placed after the early return for depth
and stencil aspects.  This commit moves it up so it actually works.

Of course, this doesn't actually matter because the only user of any of
the modifiers stuff is the WSI code and it will never do anything with
depth/stencil.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3794>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3794>

4 years agogallium/swr: fix rdtsc debug statistics mechanism
Krzysztof Raszkowski [Thu, 13 Feb 2020 13:41:41 +0000 (14:41 +0100)]
gallium/swr: fix rdtsc debug statistics mechanism

Reviewed-by: Jan Zielinski <jan.zielinski@intel.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3812>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3812>

4 years agogitlab-ci: remove load_store_vectorizer from expected s390x test failures
Rhys Perry [Wed, 5 Feb 2020 15:14:02 +0000 (15:14 +0000)]
gitlab-ci: remove load_store_vectorizer from expected s390x test failures

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3690>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3690>

4 years agonir: fix nir_const_value_as_uint bit size in load/store vectorizer tests
Rhys Perry [Tue, 4 Feb 2020 11:42:17 +0000 (11:42 +0000)]
nir: fix nir_const_value_as_uint bit size in load/store vectorizer tests

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3690>

4 years agoRevert "nir: Add a couple trivial abs optimizations"
Erik Faye-Lund [Wed, 12 Feb 2020 11:48:37 +0000 (12:48 +0100)]
Revert "nir: Add a couple trivial abs optimizations"

These were already added in 9fdaeb7776c ("nir: add min/max optimisation"),
and there's no point in doing them twice.

This reverts commit e4d346c86db0ae332fcdf55eac0e075cfb99a7eb.

Fixes: e4d346c86db ("nir: Add a couple trivial abs optimizations")
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3786>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3786>

4 years agoiris: fix aux buf map failure in 32bits app on Android
Tapani Pälli [Wed, 12 Feb 2020 06:45:47 +0000 (08:45 +0200)]
iris: fix aux buf map failure in 32bits app on Android

Cc: mesa-stable@lists.freedesktop.org
Reported-by: Zhifang Long <zhifang.long@intel.com>
Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3784>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3784>

4 years agoradv: remove unused RADV_HASH_SHADER_IS_GEOM_COPY_SHADER
Samuel Pitoiset [Wed, 12 Feb 2020 14:36:51 +0000 (15:36 +0100)]
radv: remove unused RADV_HASH_SHADER_IS_GEOM_COPY_SHADER

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3789>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3789>

4 years agoradv: remove RADV_DEBUG=nosisched and RADV_PERFTEST=sisched
Samuel Pitoiset [Wed, 12 Feb 2020 14:35:49 +0000 (15:35 +0100)]
radv: remove RADV_DEBUG=nosisched and RADV_PERFTEST=sisched

They are no longer useful.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3789>

4 years agoradv: remove LLVM sicheduler enable for The Talos Principle
Samuel Pitoiset [Wed, 12 Feb 2020 14:25:52 +0000 (15:25 +0100)]
radv: remove LLVM sicheduler enable for The Talos Principle

sisched is completely unmaintained, it used to give few more FPS
in the past but with ACO, it's now obsolete. It seems even faster
without sisched now.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3789>

4 years agoglsl: fix a memory leak with resource_set
Tapani Pälli [Mon, 27 Jan 2020 08:05:20 +0000 (10:05 +0200)]
glsl: fix a memory leak with resource_set

   ==7265== 248 (120 direct, 128 indirect) bytes in 1 blocks are definitely lost in loss record 1,438 of 1,465
   ==7265==    at 0x483980B: malloc (vg_replace_malloc.c:309)
   ==7265==    by 0x598A2AB: ralloc_size (ralloc.c:119)
   ==7265==    by 0x598F861: _mesa_set_create (set.c:127)
   ==7265==    by 0x599079D: _mesa_pointer_set_create (set.c:570)
   ==7265==    by 0x58BD7D1: build_program_resource_list(gl_context*, gl_shader_program*, bool) (linker.cpp:4026)
   ==7265==    by 0x548231B: st_link_shader (st_glsl_to_ir.cpp:170)
   ==7265==    by 0x54DA269: _mesa_glsl_link_shader (ir_to_mesa.cpp:3119)

Fixes: a6aedc66 ("st/glsl_to_nir: use nir based program resource list builder")
Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3574>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3574>

4 years agoradv: implement VK_EXT_line_rasterization
Samuel Pitoiset [Fri, 13 Sep 2019 11:40:44 +0000 (13:40 +0200)]
radv: implement VK_EXT_line_rasterization

Only Bresenham lines are supported. GFX9 is currently disabled
because there is some CTS failures for some weird reasons.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/2982>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/2982>

4 years agoradv: fix line width range and granularity
Samuel Pitoiset [Thu, 5 Dec 2019 16:28:47 +0000 (17:28 +0100)]
radv: fix line width range and granularity

The hardware supports wide lines and the granularity is way larger.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/2982>

4 years agotu: Force sysmem with mipmapped non-aligned linear stores
Connor Abbott [Fri, 31 Jan 2020 16:47:48 +0000 (17:47 +0100)]
tu: Force sysmem with mipmapped non-aligned linear stores

Fixes hangs with
dEQP-VK.api.image_clearing.core.clear_color_image.1d.linear.single_layer.r8g8b8a8_unorm
and many others on a640, and presumably silent corruption with a630.

Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3713>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3713>