litex.git
5 years agosoc_core: add check_regions_overlap method, add linker_region support (overlap is...
Florent Kermarrec [Mon, 28 Oct 2019 17:32:28 +0000 (18:32 +0100)]
soc_core: add check_regions_overlap method, add linker_region support (overlap is not checked on linker_regions)

5 years agosoc_core/add_memory_region: fix memory overlap detection
Florent Kermarrec [Mon, 28 Oct 2019 16:07:37 +0000 (17:07 +0100)]
soc_core/add_memory_region: fix memory overlap detection

5 years agotest/test_targets: skip Minerva test on Travis-CI, remove commented tests
Florent Kermarrec [Mon, 28 Oct 2019 09:59:43 +0000 (10:59 +0100)]
test/test_targets: skip Minerva test on Travis-CI, remove commented tests

5 years agocpu/minerva: elaborate from nmigen sources during build, enable hardware multiplier
Florent Kermarrec [Mon, 28 Oct 2019 09:22:17 +0000 (10:22 +0100)]
cpu/minerva: elaborate from nmigen sources during build, enable hardware multiplier

5 years agoMerge pull request #286 from gsomlo/gls-timingstrict
enjoy-digital [Fri, 25 Oct 2019 10:28:29 +0000 (12:28 +0200)]
Merge pull request #286 from gsomlo/gls-timingstrict

build/lattice/trellis: optionally allow failure if p&r timing not met

5 years agobuild/lattice/trellis: optionally allow failure if p&r timing not met
Gabriel Somlo [Thu, 24 Oct 2019 17:56:20 +0000 (13:56 -0400)]
build/lattice/trellis: optionally allow failure if p&r timing not met

When timing requirements are strict, allow the build process to fail upon
failure to meet timing. This facilitates running the build process from a
loop, repeatedly, until a "lucky" p&r solution is found, e.g.:

  while true; do
    litex/boards/targets/versa_ecp5.py --gateware-toolchain trellis \
      --sys-clk-freq=60e06 --cpu-type rocket --cpu-variant linux \
      --with-ethernet --yosys-nowidelut \
      --nextpnr-timingstrict
    if [ "$?" == "0" ]; then
      echo "Success" | mail -s "Build Succeeded" your@email.here
      break
    fi
  done

This augments commit #683e0668, which unconditionally forced p&r to
succeed, regardless of whether timing was met, via '--timing-allow-fail'.

Signed-off-by: Gabriel Somlo <gsomlo@gmail.com>
5 years agoMerge pull request #283 from kbeckmann/kbeckmann/bios_increment_address
enjoy-digital [Sun, 20 Oct 2019 13:30:22 +0000 (15:30 +0200)]
Merge pull request #283 from kbeckmann/kbeckmann/bios_increment_address

bios: Increment address when writing to flash

5 years agobios: Increment address when writing to flash
Konrad Beckmann [Sat, 19 Oct 2019 20:58:24 +0000 (22:58 +0200)]
bios: Increment address when writing to flash

5 years agobuild/lattice/trellis: use --timing-allow-fail to allow generating bistream when...
Florent Kermarrec [Fri, 18 Oct 2019 12:12:01 +0000 (14:12 +0200)]
build/lattice/trellis: use --timing-allow-fail to allow generating bistream when timings are not met

This is the default behaviour of the others tools and allow testing designs on hardware with small violations.

5 years agosoc/cores/icap/ICAPBitstream: always keep fifo.source.ready to 1
Florent Kermarrec [Fri, 18 Oct 2019 08:26:47 +0000 (10:26 +0200)]
soc/cores/icap/ICAPBitstream: always keep fifo.source.ready to 1

5 years agoMerge pull request #282 from antmicro/icapbitstream_fixes
enjoy-digital [Fri, 18 Oct 2019 08:24:20 +0000 (10:24 +0200)]
Merge pull request #282 from antmicro/icapbitstream_fixes

Fix ICAPBitstream

5 years agocores/icap/ICAPBitstream: add source ready signal.
Jan Kowalewski [Fri, 18 Oct 2019 07:33:31 +0000 (09:33 +0200)]
cores/icap/ICAPBitstream: add source ready signal.

5 years agosoc/integration/__init__: remove imports (not used and causing issues
Florent Kermarrec [Thu, 17 Oct 2019 10:44:16 +0000 (12:44 +0200)]
soc/integration/__init__: remove imports (not used and causing issues

5 years agobuild: always use platform.add_source and avoid manipulate platform.sources directly
Florent Kermarrec [Thu, 17 Oct 2019 10:13:06 +0000 (12:13 +0200)]
build: always use platform.add_source and avoid manipulate platform.sources directly

5 years agobuild/generic_platform: replace set with list for sources/verilog_include_paths
Florent Kermarrec [Thu, 17 Oct 2019 07:52:31 +0000 (09:52 +0200)]
build/generic_platform: replace set with list for sources/verilog_include_paths

Python does not have native OrderedSet and we need to be able to preserve the order of the sources
for some backends (Verilator for instance), so use list instead of set.

5 years agocores/icap/ICAPBitstream: simplify, add icap_clk_div parameter, describe how to use it.
Florent Kermarrec [Wed, 16 Oct 2019 12:56:17 +0000 (14:56 +0200)]
cores/icap/ICAPBitstream: simplify, add icap_clk_div parameter, describe how to use it.

5 years agobuild/generic_platform: keep language to None if None after tools.language_by_filename
Florent Kermarrec [Tue, 15 Oct 2019 10:13:42 +0000 (12:13 +0200)]
build/generic_platform: keep language to None if None after tools.language_by_filename

5 years agosoc_core: fix default --uart_name
Florent Kermarrec [Mon, 14 Oct 2019 20:15:02 +0000 (22:15 +0200)]
soc_core: fix default --uart_name

5 years agointegration/soc_core: expose more SoC parameters
Florent Kermarrec [Mon, 14 Oct 2019 07:12:25 +0000 (09:12 +0200)]
integration/soc_core: expose more SoC parameters

5 years agoMerge pull request #280 from kbeckmann/picorv32_typo
Tim Ansell [Sun, 13 Oct 2019 18:29:46 +0000 (11:29 -0700)]
Merge pull request #280 from kbeckmann/picorv32_typo

picorv32: Fix minimal variant params

5 years agopicorv32: Fix minimal variant params
Konrad Beckmann [Sun, 13 Oct 2019 10:56:55 +0000 (12:56 +0200)]
picorv32: Fix minimal variant params

The param p_ENABLE_COUNTERS was misspelled.

5 years agosoc_core: fix soc_core_argdict
Florent Kermarrec [Sat, 12 Oct 2019 21:05:53 +0000 (23:05 +0200)]
soc_core: fix soc_core_argdict

5 years agocpu/lm32: add missing buses
Florent Kermarrec [Sat, 12 Oct 2019 17:20:50 +0000 (19:20 +0200)]
cpu/lm32: add missing buses

5 years agosoc_core/soc_core_argdict: use inspect to get all parameters and simplify
Florent Kermarrec [Sat, 12 Oct 2019 17:18:57 +0000 (19:18 +0200)]
soc_core/soc_core_argdict: use inspect to get all parameters and simplify

5 years agointegration: simplify cpu buses auto-conversion (always use Converter, thanks gsomlo)
Florent Kermarrec [Fri, 11 Oct 2019 19:55:26 +0000 (21:55 +0200)]
integration: simplify cpu buses auto-conversion (always use Converter, thanks gsomlo)

5 years agointerconnect/wishbone: fix Converter case when buses are identical
Florent Kermarrec [Fri, 11 Oct 2019 19:49:11 +0000 (21:49 +0200)]
interconnect/wishbone: fix Converter case when buses are identical

5 years agoplatforms/versa_ecp5: add serdes refclk/sma
Florent Kermarrec [Fri, 11 Oct 2019 12:28:29 +0000 (14:28 +0200)]
platforms/versa_ecp5: add serdes refclk/sma

5 years agocpu/rocket: expose 64-bit buses (use automatic down-conversion of SoCCore)
Florent Kermarrec [Fri, 11 Oct 2019 07:01:50 +0000 (09:01 +0200)]
cpu/rocket: expose 64-bit buses (use automatic down-conversion of SoCCore)

5 years agosoc_core: add automatic down-conversion of CPU buses to 32-bit (if needed)
Florent Kermarrec [Fri, 11 Oct 2019 06:59:25 +0000 (08:59 +0200)]
soc_core: add automatic down-conversion of CPU buses to 32-bit (if needed)

5 years agosoc/interconnect/axi: re-align to improve readability
Florent Kermarrec [Fri, 11 Oct 2019 06:41:05 +0000 (08:41 +0200)]
soc/interconnect/axi: re-align to improve readability

5 years agosoftware/bios: simplify banners
Florent Kermarrec [Fri, 11 Oct 2019 06:38:12 +0000 (08:38 +0200)]
software/bios: simplify banners

5 years agocpu/picorv32: remove obsolete comment
Florent Kermarrec [Thu, 10 Oct 2019 20:29:54 +0000 (22:29 +0200)]
cpu/picorv32: remove obsolete comment

5 years agocpu/picorv32: use a single idbus
Florent Kermarrec [Thu, 10 Oct 2019 20:02:04 +0000 (22:02 +0200)]
cpu/picorv32: use a single idbus

5 years agocpu: cleanup/re-align
Florent Kermarrec [Thu, 10 Oct 2019 19:52:09 +0000 (21:52 +0200)]
cpu: cleanup/re-align

5 years agocpu/rocket: rename ibus/dbus to mem_wb/mmio_wb and add size suffix
Florent Kermarrec [Thu, 10 Oct 2019 19:40:29 +0000 (21:40 +0200)]
cpu/rocket: rename ibus/dbus to mem_wb/mmio_wb and add size suffix

5 years agocpu: add buses list and use it in soc_core to add bus masters
Florent Kermarrec [Thu, 10 Oct 2019 19:35:06 +0000 (21:35 +0200)]
cpu: add buses list and use it in soc_core to add bus masters

5 years agointegration: move soc constants to soc.h of csr.h
Florent Kermarrec [Thu, 10 Oct 2019 19:15:49 +0000 (21:15 +0200)]
integration: move soc constants to soc.h of csr.h

software retro-compat with soc.h included in csr.h

5 years agobuild/generic_platform: only add sources if language is not None
Florent Kermarrec [Thu, 10 Oct 2019 17:39:33 +0000 (19:39 +0200)]
build/generic_platform: only add sources if language is not None

5 years agoxilinx/vivado: replace "xy" == language with language == "xy"
Florent Kermarrec [Thu, 10 Oct 2019 17:36:17 +0000 (19:36 +0200)]
xilinx/vivado: replace "xy" == language with language == "xy"

5 years agoMerge pull request #277 from railnova/feature/vivado_sysverilog_support
enjoy-digital [Thu, 10 Oct 2019 17:31:09 +0000 (19:31 +0200)]
Merge pull request #277 from railnova/feature/vivado_sysverilog_support

[feature] Add SystemVerilog support for the Vivado builder

5 years agointegration/soc_zynq: shadow_base no longer recommended (replace with io_regions)
Florent Kermarrec [Thu, 10 Oct 2019 17:23:01 +0000 (19:23 +0200)]
integration/soc_zynq: shadow_base no longer recommended (replace with io_regions)

5 years agobios/main: use same banner than README (MiSoC cited in README/LICENSE)
Florent Kermarrec [Thu, 10 Oct 2019 17:21:32 +0000 (19:21 +0200)]
bios/main: use same banner than README (MiSoC cited in README/LICENSE)

5 years agosoftware/bios: don't show peripherals init banner if nothing to init, add Ethernet...
Florent Kermarrec [Thu, 10 Oct 2019 17:18:28 +0000 (19:18 +0200)]
software/bios: don't show peripherals init banner if nothing to init, add Ethernet init printf

5 years agoAdd system Verilog support for the Vivado builder
Martin Cornil [Thu, 10 Oct 2019 12:06:37 +0000 (14:06 +0200)]
Add system Verilog support for the Vivado builder

5 years agoMerge pull request #276 from gsomlo/gls-rocket-map
enjoy-digital [Wed, 9 Oct 2019 19:25:57 +0000 (21:25 +0200)]
Merge pull request #276 from gsomlo/gls-rocket-map

cpu/rocket: swap main_mem and io regions

5 years agocpu/rocket: swap main_mem and io regions
Gabriel Somlo [Wed, 9 Oct 2019 18:25:41 +0000 (14:25 -0400)]
cpu/rocket: swap main_mem and io regions

The total size of RAM (main_mem) can be expected to vary significantly,
and often exceed the size needed for MMIO allocations by a large margin.

As such, place Rocket's MMIO (io regions) below 0x8000_0000, and start
the RAM (main_mem) at 0x8000_0000, with nothing above it to limit its
future growth.

Also, bump the pre-built Rocket verilog submodule to an updated version,
which also comes with matching changes to the way MMIO and RAM accesses
are mapped and routed to their respective AXI interfaces.

Signed-off-by: Gabriel Somlo <gsomlo@gmail.com>
5 years agocpu: add default io_regions to CPUNone (all address range can be used as IO)
Florent Kermarrec [Wed, 9 Oct 2019 10:05:10 +0000 (12:05 +0200)]
cpu: add default io_regions to CPUNone (all address range can be used as IO)

5 years agoMerge pull request #275 from pcotret/patch-1
enjoy-digital [Wed, 9 Oct 2019 09:20:50 +0000 (11:20 +0200)]
Merge pull request #275 from pcotret/patch-1

Update README (related to issue #273)

5 years agosoc_core: improve check_io_region error message
Florent Kermarrec [Wed, 9 Oct 2019 08:47:19 +0000 (10:47 +0200)]
soc_core: improve check_io_region error message

5 years agotargets/sim: switch from shadow_base to io_regions
Florent Kermarrec [Wed, 9 Oct 2019 08:38:22 +0000 (10:38 +0200)]
targets/sim: switch from shadow_base to io_regions

5 years agocpu/rocket: move csr to IO region
Florent Kermarrec [Wed, 9 Oct 2019 08:24:01 +0000 (10:24 +0200)]
cpu/rocket: move csr to IO region

5 years agobuild/xilinx/vivado: fix default synth-mode
Florent Kermarrec [Wed, 9 Oct 2019 08:19:18 +0000 (10:19 +0200)]
build/xilinx/vivado: fix default synth-mode

5 years agosoc_core/cpu: add io_regions and deprecate shadow_base (with API retro-compat)
Florent Kermarrec [Wed, 9 Oct 2019 08:14:14 +0000 (10:14 +0200)]
soc_core/cpu: add io_regions and deprecate shadow_base (with API retro-compat)

The shadow_base parameter has always been difficult to apprehend, replace it with
io_regions (uncached regions) defined user or the CPU.

The equivalent of a shadow_base parameter of 0x80000000 in the old API is:
io_regions = {0x80000000: 0x80000000} # origin, length

It's still possible to use shadow_base with retro-compat, but user is encouraged
to update and features will be removed in the future.

5 years agoUpdate README (related to issue #273)
Pascal Cotret [Wed, 9 Oct 2019 07:48:32 +0000 (09:48 +0200)]
Update README (related to issue #273)

Following my problems with the quick start guide (issue #273), I suggest a few modifications to have a "real" quick start guide.

5 years agoMerge pull request #274 from gsomlo/gls-shadow-base
enjoy-digital [Tue, 8 Oct 2019 19:15:54 +0000 (21:15 +0200)]
Merge pull request #274 from gsomlo/gls-shadow-base

builder: use the SoC's existing shadow base with get_csr_header()

5 years agobuilder: use the SoC's existing shadow base with get_csr_header()
Gabriel Somlo [Tue, 8 Oct 2019 18:28:50 +0000 (14:28 -0400)]
builder: use the SoC's existing shadow base with get_csr_header()

Both the SoC and get_csr_header() have independently set defaults
for the value of 'shadow_base'. If the SoC's value was modified,
ensure that get_csr_header() uses the modified value instead of
its own default.

Signed-off-by: Gabriel Somlo <somlo@cmu.edu>
5 years agotargets/arty: allow setting synth-mode to yosys with command line: --synth-mode=yosys
Florent Kermarrec [Mon, 7 Oct 2019 08:38:26 +0000 (10:38 +0200)]
targets/arty: allow setting synth-mode to yosys with command line: --synth-mode=yosys

5 years agobuild/xilinx/vivado: add vivado_build_args/vivado_build_argdict for yosys synthesis...
Florent Kermarrec [Mon, 7 Oct 2019 08:37:16 +0000 (10:37 +0200)]
build/xilinx/vivado: add vivado_build_args/vivado_build_argdict for yosys synthesis mode

5 years agoxilinx/common: be sure language is not vhdl when yosys synthesis is used
Florent Kermarrec [Mon, 7 Oct 2019 08:36:32 +0000 (10:36 +0200)]
xilinx/common: be sure language is not vhdl when yosys synthesis is used

5 years agocpu/vexriscv: use specific mem_map for linux variant
Florent Kermarrec [Mon, 7 Oct 2019 06:49:32 +0000 (08:49 +0200)]
cpu/vexriscv: use specific mem_map for linux variant

5 years agoMerge pull request #271 from gsomlo/gls-yosys-nowidelut
enjoy-digital [Sun, 6 Oct 2019 12:55:44 +0000 (14:55 +0200)]
Merge pull request #271 from gsomlo/gls-yosys-nowidelut

RFC: optional '-nowidelut' flag for yosys synth_ecp5

5 years agotrellis, versa_ecp5: optional '-nowidelut' flag for yosys synth_ecp5
Gabriel L. Somlo [Thu, 8 Aug 2019 22:55:14 +0000 (18:55 -0400)]
trellis, versa_ecp5: optional '-nowidelut' flag for yosys synth_ecp5

Passing '-nowidelut' to yosys' synth_ecp5 command improves area utilization
to the point where a (linux variant) rocket-chip based design will fit on a
versa_ecp5 board. Usually '-nowidelut' incurs a timing penalty, but that is
then mitigated by using DSP inference (enabled by default from yosys commit
8474c5b3).

Off by default, this flag can be enabled by adding '--yosys-nowidelut=True'
to the litex/boards/targets/versa_ecp5.py command line.

Signed-off-by: Gabriel Somlo <gsomlo@gmail.com>
5 years agoMerge pull request #272 from sergachev/fix-comments
enjoy-digital [Sun, 6 Oct 2019 10:10:19 +0000 (12:10 +0200)]
Merge pull request #272 from sergachev/fix-comments

fix comments in icap.py

5 years agofix comments
Ilia Sergachev [Sun, 6 Oct 2019 08:47:28 +0000 (10:47 +0200)]
fix comments

5 years agolitex_setup: add litejesd204b
Florent Kermarrec [Fri, 4 Oct 2019 08:00:45 +0000 (10:00 +0200)]
litex_setup: add litejesd204b

5 years agoMerge pull request #270 from gsomlo/gls-csr-upper
enjoy-digital [Tue, 1 Oct 2019 19:40:56 +0000 (21:40 +0200)]
Merge pull request #270 from gsomlo/gls-csr-upper

soc/integration: ensure CSR constants are in uppercase

5 years agosoc/cores/icap: simplify ICAPBitstream (untested)
Florent Kermarrec [Tue, 1 Oct 2019 19:30:14 +0000 (21:30 +0200)]
soc/cores/icap: simplify ICAPBitstream (untested)

5 years agosoc/cores/icap: rename ICAP to ICAPBistream and revert old ICAP
Florent Kermarrec [Tue, 1 Oct 2019 19:04:49 +0000 (21:04 +0200)]
soc/cores/icap: rename ICAP to ICAPBistream and revert old ICAP

5 years agoMerge pull request #269 from antmicro/rework_icap
enjoy-digital [Tue, 1 Oct 2019 18:55:28 +0000 (20:55 +0200)]
Merge pull request #269 from antmicro/rework_icap

soc: cores: support sending custom bitstream to ICAP

5 years agosoc/integration: ensure CSR constants are in uppercase
Gabriel Somlo [Tue, 1 Oct 2019 16:14:33 +0000 (12:14 -0400)]
soc/integration: ensure CSR constants are in uppercase

Fixup over commit 8be5824e.

Signed-off-by: Gabriel Somlo <gsomlo@gmail.com>
5 years agosoc: cores: support sending custom bitstream to ICAP
Jan Kowalewski [Tue, 17 Sep 2019 19:35:53 +0000 (21:35 +0200)]
soc: cores: support sending custom bitstream to ICAP

This adds FIFO that can be used to send any
sequence of commands to the ICAP controller.

5 years agosoc/interconnect: rename stream_packet to packet & cleanup (with retro-compat)
Florent Kermarrec [Mon, 30 Sep 2019 21:31:34 +0000 (23:31 +0200)]
soc/interconnect: rename stream_packet to packet & cleanup (with retro-compat)

5 years agosoc/interconnect/stream: add separators, mode Actor modules just after Endpoint
Florent Kermarrec [Mon, 30 Sep 2019 21:18:39 +0000 (23:18 +0200)]
soc/interconnect/stream: add separators, mode Actor modules just after Endpoint

5 years agosoc_zynq: update get_csr_header
Florent Kermarrec [Mon, 30 Sep 2019 14:00:11 +0000 (16:00 +0200)]
soc_zynq: update get_csr_header

5 years agosoc/integration: move cpu_interface retro-compatibility to litex/__init__
Florent Kermarrec [Mon, 30 Sep 2019 09:32:07 +0000 (11:32 +0200)]
soc/integration: move cpu_interface retro-compatibility to litex/__init__

5 years agosoc/integration: use dicts for constants/mem_regions/csr_regions to cleanup/simplify...
Florent Kermarrec [Mon, 30 Sep 2019 08:59:36 +0000 (10:59 +0200)]
soc/integration: use dicts for constants/mem_regions/csr_regions to cleanup/simplify iterations on theses

5 years agocpu: remove initial SERV support (we'll work in a branch to experiment with it)
Florent Kermarrec [Mon, 30 Sep 2019 06:30:45 +0000 (08:30 +0200)]
cpu: remove initial SERV support (we'll work in a branch to experiment with it)

5 years agosoc_core: fix cpu_type=None case and add test for it
Florent Kermarrec [Mon, 30 Sep 2019 06:26:38 +0000 (08:26 +0200)]
soc_core: fix cpu_type=None case and add test for it

5 years agosoc_sdram: remove axi usecase, this was only useful to do some preliminary axi tests.
Florent Kermarrec [Sun, 29 Sep 2019 15:33:16 +0000 (17:33 +0200)]
soc_sdram: remove axi usecase, this was only useful to do some preliminary axi tests.

Proper AXI support will be added in the future for SoCs.

5 years agosoc_core: cleanup/re-align
Florent Kermarrec [Sun, 29 Sep 2019 15:31:37 +0000 (17:31 +0200)]
soc_core: cleanup/re-align

5 years agosoc/integration: rename cpu_interface to export (with retro-compat), re-arrange a...
Florent Kermarrec [Sun, 29 Sep 2019 15:23:01 +0000 (17:23 +0200)]
soc/integration: rename cpu_interface to export (with retro-compat), re-arrange a bit, add separators

5 years agotest/test_targets: update cpu-type to mor1kx
Florent Kermarrec [Sun, 29 Sep 2019 15:12:15 +0000 (17:12 +0200)]
test/test_targets: update cpu-type to mor1kx

5 years agosoc/cores: uniformize (continue)
Florent Kermarrec [Sun, 29 Sep 2019 15:04:21 +0000 (17:04 +0200)]
soc/cores: uniformize (continue)

5 years agosoc/cores/gpio: uniformize with others cores
Florent Kermarrec [Sun, 29 Sep 2019 14:10:44 +0000 (16:10 +0200)]
soc/cores/gpio: uniformize with others cores

5 years agosoc/cores: rename frequency_meter to freqmeter and uniformize with others cores
Florent Kermarrec [Sun, 29 Sep 2019 14:08:39 +0000 (16:08 +0200)]
soc/cores: rename frequency_meter to freqmeter and uniformize with others cores

5 years agosoc/cores/ecc: improve readibility, uniformize with others cores
Florent Kermarrec [Sun, 29 Sep 2019 14:02:04 +0000 (16:02 +0200)]
soc/cores/ecc: improve readibility, uniformize with others cores

5 years agosoc/cores/clocks: improve readibility
Florent Kermarrec [Sun, 29 Sep 2019 13:58:22 +0000 (15:58 +0200)]
soc/cores/clocks: improve readibility

5 years agosoc_core: use cpu.data_width to compute csr_alignment (and remove Rocket workaround)
Florent Kermarrec [Sun, 29 Sep 2019 13:47:10 +0000 (15:47 +0200)]
soc_core: use cpu.data_width to compute csr_alignment (and remove Rocket workaround)

5 years agosoc/cores/cpus: improve ident/align, uniformize between cpus
Florent Kermarrec [Sun, 29 Sep 2019 13:41:18 +0000 (15:41 +0200)]
soc/cores/cpus: improve ident/align, uniformize between cpus

5 years agosoc/cores/cpu: add CPU class and make all CPU inheritate from it
Florent Kermarrec [Sun, 29 Sep 2019 13:05:29 +0000 (15:05 +0200)]
soc/cores/cpu: add CPU class and make all CPU inheritate from it

Also rename reserved_interrupts to interrupts (empty dict is no reserved interrupts)

5 years agosoc_sdram: move ControllerInjector to LiteDRAM (LiteDRAMCore)
Florent Kermarrec [Sun, 29 Sep 2019 12:38:07 +0000 (14:38 +0200)]
soc_sdram: move ControllerInjector to LiteDRAM (LiteDRAMCore)

5 years agosoc/integration: add common.py and move helpers from soc_core to it
Florent Kermarrec [Sun, 29 Sep 2019 12:22:26 +0000 (14:22 +0200)]
soc/integration: add common.py and move helpers from soc_core to it

5 years agosoc_core: avoid manual listing of support CPUs, just use CPU.keys()
Florent Kermarrec [Sat, 28 Sep 2019 17:04:38 +0000 (19:04 +0200)]
soc_core: avoid manual listing of support CPUs, just use CPU.keys()

5 years agosoc_core: remove add_cpu_or_bridge retro-compatibility (most of the designs have...
Florent Kermarrec [Sat, 28 Sep 2019 17:01:41 +0000 (19:01 +0200)]
soc_core: remove add_cpu_or_bridge retro-compatibility (most of the designs have been updated since the change)

5 years agointegration/soc_core: remove csr_map_update (no longer used)
Florent Kermarrec [Sat, 28 Sep 2019 16:59:30 +0000 (18:59 +0200)]
integration/soc_core: remove csr_map_update (no longer used)

5 years agosoc_core/cpu: move memory map override to CPUs, select reset_address after eventual...
Florent Kermarrec [Sat, 28 Sep 2019 12:13:39 +0000 (14:13 +0200)]
soc_core/cpu: move memory map override to CPUs, select reset_address after eventual memory map has override been done

5 years agosoc/cores/cpu: add set_reset_address method and use it instead of passing reset_addre...
Florent Kermarrec [Sat, 28 Sep 2019 10:35:41 +0000 (12:35 +0200)]
soc/cores/cpu: add set_reset_address method and use it instead of passing reset_address as a parameter

5 years agosoc/cores/cpu: do instance in do_finalize for all cpus (allow updating parameters...
Florent Kermarrec [Sat, 28 Sep 2019 10:09:55 +0000 (12:09 +0200)]
soc/cores/cpu: do instance in do_finalize for all cpus (allow updating parameters until the design is generated)

5 years agocores/cpu: define CPUS and simplify instance
Florent Kermarrec [Fri, 27 Sep 2019 22:55:08 +0000 (00:55 +0200)]
cores/cpu: define CPUS and simplify instance

5 years agosoc_core/serv: use UART_POLLING (no interrupt support)
Florent Kermarrec [Fri, 27 Sep 2019 22:42:00 +0000 (00:42 +0200)]
soc_core/serv: use UART_POLLING (no interrupt support)