Eddie Hung [Wed, 25 Sep 2019 23:43:24 +0000 (16:43 -0700)]
Merge pull request #1401 from SergeyDegtyar/SergeyDegtyar/ice40
ICE40 tests. adffs test update (equiv_opt -multiclock).
SergeyDegtyar [Wed, 25 Sep 2019 11:43:26 +0000 (14:43 +0300)]
Change sync controls to async.
Clifford Wolf [Wed, 25 Sep 2019 07:20:54 +0000 (09:20 +0200)]
Merge pull request #1402 from YosysHQ/clifford/portlist
Add "portlist" command
Clifford Wolf [Wed, 25 Sep 2019 07:20:38 +0000 (09:20 +0200)]
Improve "portlist" command
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Clifford Wolf [Tue, 24 Sep 2019 16:08:59 +0000 (18:08 +0200)]
Add "portlist" command
Signed-off-by: Clifford Wolf <clifford@clifford.at>
SergeyDegtyar [Tue, 24 Sep 2019 11:55:32 +0000 (14:55 +0300)]
adffs test update (equiv_opt -multiclock).
Miodrag Milanović [Mon, 23 Sep 2019 18:06:40 +0000 (20:06 +0200)]
Merge pull request #1399 from nakengelhardt/fix-show-macos
fix show command for macos
N. Engelhardt [Mon, 23 Sep 2019 16:25:04 +0000 (18:25 +0200)]
add xdot dependency to Brewfile
N. Engelhardt [Mon, 23 Sep 2019 15:25:30 +0000 (17:25 +0200)]
fix show command for macos
Clifford Wolf [Sat, 21 Sep 2019 09:25:36 +0000 (11:25 +0200)]
Merge pull request #1392 from YosysHQ/eddie/fix1391
(* techmap_autopurge *) fixes when ports aren't consistently-sized
Eddie Hung [Sat, 21 Sep 2019 00:58:51 +0000 (17:58 -0700)]
Hell let's add the original #1381 testcase too
Eddie Hung [Sat, 21 Sep 2019 00:52:23 +0000 (17:52 -0700)]
Revert abc9.cc
Eddie Hung [Sat, 21 Sep 2019 00:49:26 +0000 (17:49 -0700)]
Add testcase
Eddie Hung [Sat, 21 Sep 2019 00:48:37 +0000 (17:48 -0700)]
Trim mismatched connection to be same (smallest) size
Eddie Hung [Sat, 21 Sep 2019 00:42:36 +0000 (17:42 -0700)]
Fix first testcase in #1391
Clifford Wolf [Fri, 20 Sep 2019 11:30:28 +0000 (13:30 +0200)]
Merge pull request #1386 from YosysHQ/clifford/fix1360
Fix handling of read_verilog config in AstModule::reprocess_module()
Clifford Wolf [Fri, 20 Sep 2019 10:16:20 +0000 (12:16 +0200)]
Fix handling of read_verilog config in AstModule::reprocess_module(), fixes #1360
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Clifford Wolf [Fri, 20 Sep 2019 08:28:20 +0000 (10:28 +0200)]
Update CHANGELOG
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Clifford Wolf [Fri, 20 Sep 2019 08:27:17 +0000 (10:27 +0200)]
Add "add -mod"
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Clifford Wolf [Fri, 20 Sep 2019 07:58:42 +0000 (09:58 +0200)]
Merge pull request #1384 from YosysHQ/clifford/fix1381
Add techmap_autopurge attribute
Clifford Wolf [Thu, 19 Sep 2019 17:26:09 +0000 (19:26 +0200)]
Add techmap_autopurge attribute, fixes #1381
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Marcin Kościelnicki [Wed, 28 Aug 2019 15:28:01 +0000 (15:28 +0000)]
Use extractinv for synth_xilinx -ise
Marcin Kościelnicki [Wed, 28 Aug 2019 14:58:14 +0000 (14:58 +0000)]
Added extractinv pass
Eddie Hung [Fri, 6 Sep 2019 20:28:15 +0000 (13:28 -0700)]
Document (* gentb_skip *) attr for test_autotb
Eddie Hung [Wed, 18 Sep 2019 19:40:08 +0000 (12:40 -0700)]
Merge pull request #1355 from YosysHQ/eddie/peepopt_dffmuxext
peepopt_dffmux -- bit optimisations for word level $dff + (enable/reset) $mux cells
Eddie Hung [Wed, 18 Sep 2019 17:04:27 +0000 (10:04 -0700)]
Merge pull request #1379 from mmicko/sim_models
Added simulation models for Efinix and Anlogic
Miodrag Milanovic [Wed, 18 Sep 2019 15:48:16 +0000 (17:48 +0200)]
make note that it is for latch mode
Miodrag Milanovic [Wed, 18 Sep 2019 15:45:19 +0000 (17:45 +0200)]
better lut handling
Miodrag Milanovic [Wed, 18 Sep 2019 15:45:07 +0000 (17:45 +0200)]
better handling of lut and begin/end add
Clifford Wolf [Wed, 18 Sep 2019 11:33:02 +0000 (13:33 +0200)]
Add "write_aiger -L"
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Clifford Wolf [Wed, 18 Sep 2019 09:56:14 +0000 (11:56 +0200)]
Fix stupid bug in btor back-end
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Clifford Wolf [Mon, 16 Sep 2019 11:05:41 +0000 (13:05 +0200)]
Bump version
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Clifford Wolf [Mon, 16 Sep 2019 11:05:02 +0000 (13:05 +0200)]
Merge pull request #1380 from YosysHQ/clifford/fix1372
Fix handling of range selects on loop variables
Clifford Wolf [Mon, 16 Sep 2019 09:25:16 +0000 (11:25 +0200)]
Fix handling of range selects on loop variables, fixes #1372
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Eddie Hung [Sun, 15 Sep 2019 20:56:07 +0000 (13:56 -0700)]
Merge pull request #1374 from YosysHQ/eddie/fix1371
Fix two non-deterministic behaviours that cause divergence between compilers
Marcin Kościelnicki [Sun, 15 Sep 2019 00:49:53 +0000 (00:49 +0000)]
xilinx: Make blackbox library family-dependent.
Fixes #1246.
Clifford Wolf [Sun, 15 Sep 2019 09:04:31 +0000 (11:04 +0200)]
Merge pull request #1377 from YosysHQ/clifford/fixzdigit
Fix handling of z_digit "?" and fix optimization of cmp with "z"
Miodrag Milanovic [Sun, 15 Sep 2019 07:37:16 +0000 (09:37 +0200)]
Added simulation models for Efinix and Anlogic
Eddie Hung [Sat, 14 Sep 2019 01:19:07 +0000 (18:19 -0700)]
Oops
Eddie Hung [Fri, 13 Sep 2019 23:41:10 +0000 (16:41 -0700)]
Add counter-example from @cliffordwolf
Eddie Hung [Fri, 13 Sep 2019 23:33:18 +0000 (16:33 -0700)]
Revert "Make one check $shift(x)? only; change testcase to be 8b"
This reverts commit
e2c2d784c8217e4bcf29fb6b156b6a8285036b80.
Eddie Hung [Fri, 13 Sep 2019 23:30:44 +0000 (16:30 -0700)]
Spacing
Eddie Hung [Fri, 13 Sep 2019 23:18:05 +0000 (16:18 -0700)]
Explicitly order function arguments
Eddie Hung [Fri, 13 Sep 2019 18:13:57 +0000 (11:13 -0700)]
Use template specialisation
Eddie Hung [Fri, 13 Sep 2019 16:49:15 +0000 (09:49 -0700)]
Revert "SigSet<Cell*> to use stable compare class"
This reverts commit
4ea34aaacdf6f76e11a83d5eb2a53ba7e75f7c11.
Clifford Wolf [Fri, 13 Sep 2019 11:39:39 +0000 (13:39 +0200)]
Fix handling of z_digit "?" and fix optimization of cmp with "z"
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Clifford Wolf [Fri, 13 Sep 2019 08:22:34 +0000 (10:22 +0200)]
Merge pull request #1373 from YosysHQ/clifford/fix1364
Fix lexing of integer literals
Clifford Wolf [Fri, 13 Sep 2019 08:19:58 +0000 (10:19 +0200)]
Fix lexing of integer literals without radix
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Eddie Hung [Thu, 12 Sep 2019 19:00:34 +0000 (12:00 -0700)]
Grammar
Eddie Hung [Thu, 12 Sep 2019 18:45:17 +0000 (11:45 -0700)]
static_assert to enforce this going forward
Eddie Hung [Thu, 12 Sep 2019 18:45:02 +0000 (11:45 -0700)]
SigSet<Cell*> to use stable compare class
David Shah [Thu, 12 Sep 2019 11:26:28 +0000 (12:26 +0100)]
Merge pull request #1370 from YosysHQ/dave/equiv_opt_multiclock
Add equiv_opt -multiclock
Clifford Wolf [Thu, 12 Sep 2019 07:43:19 +0000 (09:43 +0200)]
Fix lexing of integer literals, fixes #1364
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Eddie Hung [Wed, 11 Sep 2019 21:20:49 +0000 (14:20 -0700)]
Tidy up
Eddie Hung [Wed, 11 Sep 2019 21:17:45 +0000 (14:17 -0700)]
Fix UB
Eddie Hung [Wed, 11 Sep 2019 20:36:37 +0000 (13:36 -0700)]
Cope with presence of reset muxes too
Eddie Hung [Wed, 11 Sep 2019 20:22:52 +0000 (13:22 -0700)]
Cleanup
Eddie Hung [Wed, 11 Sep 2019 20:22:41 +0000 (13:22 -0700)]
Add more tests
Eddie Hung [Wed, 11 Sep 2019 19:29:26 +0000 (12:29 -0700)]
Only display log message if did_something
Marcin Kościelnicki [Tue, 10 Sep 2019 16:31:50 +0000 (16:31 +0000)]
Add -match-init option to dff2dffs.
David Shah [Wed, 11 Sep 2019 12:55:16 +0000 (13:55 +0100)]
Add equiv_opt -multiclock
Signed-off-by: David Shah <dave@ds0.me>
David Shah [Wed, 11 Sep 2019 08:57:30 +0000 (09:57 +0100)]
Merge pull request #1362 from xobs/smtbmc-msvc2-build-fixes
MSVC2 fixes
Eddie Hung [Wed, 11 Sep 2019 07:56:38 +0000 (00:56 -0700)]
Rename dffmuxext -> dffmux, also remove constants in dff+mux
Eddie Hung [Wed, 11 Sep 2019 07:14:06 +0000 (00:14 -0700)]
proc instead of prep
Eddie Hung [Wed, 11 Sep 2019 07:07:17 +0000 (00:07 -0700)]
Add unsigned case
Clifford Wolf [Tue, 10 Sep 2019 16:42:45 +0000 (18:42 +0200)]
Bump version
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Sean Cross [Tue, 10 Sep 2019 00:47:16 +0000 (08:47 +0800)]
tests: ice40: fix div_mod SB_LUT4 count
This test is failing due to one of the changes present in this patchset.
Adjust the test to match the newly-observed values.
https://github.com/xobs/yosys/compare/smtbmc-msvc2-build-fixes...YosysHQ:xobs/pr1362
Signed-off-by: Sean Cross <sean@xobs.io>
Eddie Hung [Mon, 9 Sep 2019 23:46:33 +0000 (16:46 -0700)]
Fix misspelling
Sean Cross [Mon, 9 Sep 2019 04:40:01 +0000 (12:40 +0800)]
passes: opt_share: don't statically initialize mergeable_type_map
In
3d3779b0376b8204ed7637053176a07b7271ac1d this got turned from a
`std::map<std::string, std::string>` to `std::map<IdString, IdString>`.
Consequently, this exposed some initialization sequencing issues (#1361).
Only initialize the map when it's first used, to avoid these static issues.
This fixes #1361.
Signed-off-by: Sean Cross <sean@xobs.io>
Sean Cross [Sun, 8 Sep 2019 07:50:24 +0000 (15:50 +0800)]
msys2: launcher: fix warnings and errors under g++
When building under G++, certain C-isms no longer work. For example,
we must now cast the return from `calloc()`.
Fix `launcher.c` so that it builds under whatever $CXX is set to,
which is usually a C++ compiler.
Signed-off-by: Sean Cross <sean@xobs.io>
Sean Cross [Sun, 8 Sep 2019 07:47:09 +0000 (15:47 +0800)]
backends: smt2: use $(CXX) variable for compiler
The Makefile assumes the compiler is called `gcc`, which isn't always
true. In fact, if we're building on msys2 or msys2-64, the compiler
is called `i686-w64-mingw32-g++` or `x86_64-w64-mingw32-g++`.
Use the variable instead of hardcoding the name, to fix building on
these systems.
Signed-off-by: Sean Cross <sean@xobs.io>
Marcin Kościelnicki [Fri, 16 Aug 2019 03:14:30 +0000 (03:14 +0000)]
synth_xilinx: Support init values on Spartan 6 flip-flops properly.
Marcin Kościelnicki [Fri, 16 Aug 2019 03:14:03 +0000 (03:14 +0000)]
techmap: Add support for extracting init values of ports
Eddie Hung [Sat, 7 Sep 2019 05:52:00 +0000 (22:52 -0700)]
Merge branch 'master' of github.com:YosysHQ/yosys
Eddie Hung [Sat, 7 Sep 2019 05:51:44 +0000 (22:51 -0700)]
Add missing -assert to equiv_opt
Eddie Hung [Sat, 7 Sep 2019 05:50:03 +0000 (22:50 -0700)]
Missing equiv_opt -assert
Eddie Hung [Sat, 7 Sep 2019 05:48:23 +0000 (22:48 -0700)]
Make one check $shift(x)? only; change testcase to be 8b
Eddie Hung [Sat, 7 Sep 2019 05:48:04 +0000 (22:48 -0700)]
Usee equiv_opt -assert
Eddie Hung [Thu, 5 Sep 2019 19:00:23 +0000 (12:00 -0700)]
Merge pull request #1312 from YosysHQ/xaig_arrival
Allow arrival times of sequential outputs to be specified to abc9
Clifford Wolf [Thu, 5 Sep 2019 17:05:13 +0000 (19:05 +0200)]
Bump version
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Clifford Wolf [Thu, 5 Sep 2019 16:14:28 +0000 (18:14 +0200)]
Merge pull request #1350 from YosysHQ/clifford/fixsby59
Properly construct $live and $fair cells from "if (...) assume/assert (s_eventually ...)"
Clifford Wolf [Thu, 5 Sep 2019 16:10:40 +0000 (18:10 +0200)]
Merge pull request #1330 from YosysHQ/clifford/fix1145
Add flatten handling of pre-existing wires as created by interfaces
Eddie Hung [Thu, 5 Sep 2019 15:43:22 +0000 (08:43 -0700)]
simple/peepopt.v tests to various/peepopt.ys with equiv_opt & select
Eddie Hung [Thu, 5 Sep 2019 15:25:09 +0000 (08:25 -0700)]
Revert "abc9 followed by clean otherwise netlist could be invalid for sim"
This reverts commit
6fe1ca633d90fb238d2671dba3d7f772c263a497.
Clifford Wolf [Thu, 5 Sep 2019 15:20:29 +0000 (17:20 +0200)]
Update README.md
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Clifford Wolf [Thu, 5 Sep 2019 11:51:53 +0000 (13:51 +0200)]
Rename conflicting wires on flatten/techmap, add "hierconn" attribute, fixes #1220
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Clifford Wolf [Mon, 26 Aug 2019 22:55:43 +0000 (00:55 +0200)]
Add flatten handling of pre-existing wires as created by interfaces, fixes #1145
Signed-off-by: Clifford Wolf <clifford@clifford.at>
whitequark [Thu, 5 Sep 2019 00:20:47 +0000 (00:20 +0000)]
Merge pull request #1356 from emilazy/fix-makefile-shell
Use $(shell :; ...) in Makefile to force shell
Emily [Wed, 4 Sep 2019 23:30:29 +0000 (00:30 +0100)]
Use $(shell :; ...) in Makefile to force shell
Did you think that `$(shell command -v ...)` would actually get run by
the shell? Foolish mortal; GNU Make is obviously far more wise than
thee, as it optimizes it to a direct -- and hence broken (since
`command` is a shell builtin) -- exec. This horrifying contortion
ensures that an actual shell runs the command and fixes the behaviour.
@Shizmob found the source of this misbehaviour; turns out gmake has a
hard-coded, incomplete list of shell builtins:
https://github.com/mirror/make/blob/
715c787dc69bac37827a7d6ea6d40a86c55b5583/src/job.c#L2691
This contains `command`, but the whole function is full of horrible
heuristic garbage so who knows. I'm so sorry.
Eddie Hung [Wed, 4 Sep 2019 22:47:36 +0000 (15:47 -0700)]
Resolve TODO with pin assignments for SRL*
Eddie Hung [Wed, 4 Sep 2019 22:36:07 +0000 (15:36 -0700)]
Merge remote-tracking branch 'origin/master' into xaig_arrival
Eddie Hung [Wed, 4 Sep 2019 22:21:39 +0000 (15:21 -0700)]
Revert "parse_xaiger() to do "clean -purge""
This reverts commit
5d16bf831688ff665b0ec2abd6835b71320b2db5.
Eddie Hung [Wed, 4 Sep 2019 22:20:04 +0000 (15:20 -0700)]
abc9 followed by clean otherwise netlist could be invalid for sim
Eddie Hung [Wed, 4 Sep 2019 20:42:44 +0000 (13:42 -0700)]
Remove log_cell() calls
Eddie Hung [Wed, 4 Sep 2019 19:35:15 +0000 (12:35 -0700)]
Add peepopt_dffmuxext
Eddie Hung [Wed, 4 Sep 2019 19:34:44 +0000 (12:34 -0700)]
Add peepopt_dffmuxext tests
whitequark [Wed, 4 Sep 2019 18:55:17 +0000 (18:55 +0000)]
Merge pull request #1354 from emilazy/remove-which-use
Replace `which` with `command -v` in Makefile too
Emily [Wed, 4 Sep 2019 18:01:00 +0000 (19:01 +0100)]
Replace `which` with `command -v` in Makefile too
Eddie Hung [Wed, 4 Sep 2019 17:55:41 +0000 (10:55 -0700)]
Merge pull request #1338 from YosysHQ/eddie/deferred_top
hierarchy -auto-top to work with (* top *) modules from read/read_verilog -defer
Eddie Hung [Tue, 3 Sep 2019 19:18:50 +0000 (12:18 -0700)]
Adopt @cliffordwolf's suggestion