Clifford Wolf [Thu, 22 Dec 2016 22:41:44 +0000 (23:41 +0100)]
Added "yosys -W regex"
Clifford Wolf [Wed, 21 Dec 2016 09:16:47 +0000 (10:16 +0100)]
Added AIGER back-end to automatic back-end detection
Clifford Wolf [Wed, 21 Dec 2016 09:16:10 +0000 (10:16 +0100)]
Updated ABC to hg rev
a4872e22c646
Clifford Wolf [Wed, 21 Dec 2016 08:13:20 +0000 (09:13 +0100)]
Updated ABC to hg rev
8bab2eedbba4
Clifford Wolf [Thu, 15 Dec 2016 16:49:11 +0000 (17:49 +0100)]
Added "verilog_defines" command
Clifford Wolf [Tue, 13 Dec 2016 12:48:09 +0000 (13:48 +0100)]
Bugfix in comment handling
Clifford Wolf [Sun, 11 Dec 2016 12:48:18 +0000 (13:48 +0100)]
Added $anyconst support to AIGER back-end
Clifford Wolf [Sun, 11 Dec 2016 10:03:25 +0000 (11:03 +0100)]
Merge branch 'LSS-USP-unit-test-structure'
Clifford Wolf [Sun, 11 Dec 2016 10:02:56 +0000 (11:02 +0100)]
Some minor CodingReadme changes in unit test section
Clifford Wolf [Sun, 11 Dec 2016 09:58:49 +0000 (10:58 +0100)]
Build hotfix in tests/unit/Makefile
rodrigosiqueira [Sat, 10 Dec 2016 20:21:56 +0000 (18:21 -0200)]
Improved unit test structure
Signed-off-by: rodrigosiqueira <rodrigosiqueiramelo@gmail.com>
Signed-off-by: chaws <18oliveira.charles@gmail.com>
* Merged run-all-unitest inside unit-test target
* Fixed Makefile dependencies
* Updated documentation about unit test
rodrigosiqueira [Sun, 4 Dec 2016 13:35:13 +0000 (11:35 -0200)]
Added explanation about configure and create test
Added explanation about configure unit test environment and how to add new unit tests
rodrigosiqueira [Sun, 4 Dec 2016 13:28:25 +0000 (11:28 -0200)]
Added required structure to implement unit tests
Added modifications inside the main Makefile to refers the unit test Makefile.
Added separated Makefile only for compiling unit tests.
Added simple example of unit test.
Signed-off-by: Charles Oliveira <18oliveira.charles@gmail.com>
Signed-off-by: Pablo Alejandro <pabloabur@usp.br>
Signed-off-by: Rodrigo Siqueira <siqueira@ime.usp.br>
Clifford Wolf [Sat, 3 Dec 2016 12:20:29 +0000 (13:20 +0100)]
Added $assert/$assume support to AIGER back-end
Clifford Wolf [Sat, 3 Dec 2016 11:37:20 +0000 (12:37 +0100)]
Improved yosys-smtbmc default -t/--assume-skipped for --cex and --aig
Clifford Wolf [Thu, 1 Dec 2016 16:45:40 +0000 (17:45 +0100)]
Updated ABV to hg rev
8b555d9e67cf
Clifford Wolf [Thu, 1 Dec 2016 12:42:17 +0000 (13:42 +0100)]
Added examples/aiger/
Clifford Wolf [Thu, 1 Dec 2016 11:57:26 +0000 (12:57 +0100)]
Added "yosys-smtbmc --aig"
Clifford Wolf [Thu, 1 Dec 2016 11:00:00 +0000 (12:00 +0100)]
Added support for partially initialized regs to smt2 back-end
Clifford Wolf [Thu, 1 Dec 2016 10:04:36 +0000 (11:04 +0100)]
Added "write_aiger -zinit -symbols -vmap"
Clifford Wolf [Wed, 30 Nov 2016 20:30:24 +0000 (21:30 +0100)]
Added "write_aiger" command
Clifford Wolf [Wed, 30 Nov 2016 10:25:55 +0000 (11:25 +0100)]
Added "design -reset-vlog"
Clifford Wolf [Tue, 29 Nov 2016 12:30:35 +0000 (13:30 +0100)]
Improved equiv_purge log output
Clifford Wolf [Mon, 28 Nov 2016 14:15:09 +0000 (15:15 +0100)]
Bugfix in smt2 back-end for pure checker modules
Clifford Wolf [Mon, 28 Nov 2016 13:50:17 +0000 (14:50 +0100)]
Added support for macros as include file names
Clifford Wolf [Mon, 28 Nov 2016 13:45:05 +0000 (14:45 +0100)]
Bugfix in "read_verilog -D NAME=VAL" handling
Clifford Wolf [Sun, 27 Nov 2016 11:11:04 +0000 (12:11 +0100)]
Removed shebang line from smtio.py, fixes #279
Clifford Wolf [Wed, 23 Nov 2016 12:49:25 +0000 (13:49 +0100)]
Added wire start_offset and upto handling BLIF back-end
Clifford Wolf [Wed, 23 Nov 2016 12:46:03 +0000 (13:46 +0100)]
Added wire start_offset and upto handling to splitnets cmd
Clifford Wolf [Tue, 22 Nov 2016 20:24:45 +0000 (21:24 +0100)]
Merge pull request #274 from oldtopman/lcurses
Added optional flag for linking curses with readline.
Clifford Wolf [Tue, 22 Nov 2016 20:21:13 +0000 (21:21 +0100)]
Added "yosys-smtbmc --append"
oldtopman [Tue, 22 Nov 2016 06:11:58 +0000 (23:11 -0700)]
Added optional flag for linking curses with readline.
Clifford Wolf [Sat, 19 Nov 2016 22:25:58 +0000 (23:25 +0100)]
Merge pull request #272 from AlexDaniel/master
Markdownify README (№2)
Aleks-Daniel Jakimenko-Aleksejev [Sat, 19 Nov 2016 18:51:50 +0000 (20:51 +0200)]
Keep lines under 80 characters
Recent README changes added some characters to existing lines, which
made them longer than 80 characters. This commit fixes that.
Clifford Wolf [Sat, 19 Nov 2016 17:20:54 +0000 (18:20 +0100)]
Improved ABC default scripts
Aleks-Daniel Jakimenko-Aleksejev [Sat, 19 Nov 2016 16:34:13 +0000 (18:34 +0200)]
Markdownify README even further
Clifford Wolf [Sat, 19 Nov 2016 16:36:07 +0000 (17:36 +0100)]
Merge pull request #271 from azidar/bugfix-assign-wmask
Bugfix: include assign to write-mask
Adam Izraelevitz [Fri, 18 Nov 2016 19:49:26 +0000 (11:49 -0800)]
Bugfix: include assign to write-mask
Clifford Wolf [Fri, 18 Nov 2016 01:41:29 +0000 (02:41 +0100)]
More progress in FIRRTL back-end
Clifford Wolf [Thu, 17 Nov 2016 23:32:35 +0000 (00:32 +0100)]
Progress in FIRRTL back-end
Clifford Wolf [Thu, 17 Nov 2016 22:36:47 +0000 (23:36 +0100)]
Added first draft of FIRRTL back-end
Clifford Wolf [Wed, 16 Nov 2016 11:00:39 +0000 (12:00 +0100)]
Cleanups and fixed in write_verilog regarding reg init
Clifford Wolf [Tue, 15 Nov 2016 12:35:19 +0000 (13:35 +0100)]
Added support for hierarchical defparams
Clifford Wolf [Tue, 15 Nov 2016 11:42:43 +0000 (12:42 +0100)]
Remember global declarations and defines accross read_verilog calls
Clifford Wolf [Sun, 13 Nov 2016 20:47:51 +0000 (21:47 +0100)]
Merge pull request #268 from AlexDaniel/master
Markdownify README
Aleks-Daniel Jakimenko-Aleksejev [Sat, 12 Nov 2016 21:33:28 +0000 (23:33 +0200)]
Markdownify README
This is the first commit in series. There are many other things that
could be improved, this is just the first renderable version.
Clifford Wolf [Wed, 9 Nov 2016 12:13:26 +0000 (13:13 +0100)]
Minor bugfix in submod
Clifford Wolf [Tue, 8 Nov 2016 18:07:22 +0000 (19:07 +0100)]
Progress in examples/gowin/
Clifford Wolf [Tue, 8 Nov 2016 17:54:00 +0000 (18:54 +0100)]
Indenting fixes in gowin sim cell lib
Clifford Wolf [Tue, 8 Nov 2016 17:53:36 +0000 (18:53 +0100)]
Bugfix in "setundef" pass
Clifford Wolf [Mon, 7 Nov 2016 11:55:56 +0000 (12:55 +0100)]
Added examples/gowin/
Clifford Wolf [Sat, 5 Nov 2016 23:04:10 +0000 (00:04 +0100)]
Implemented "scc -set_attr"
Clifford Wolf [Sat, 5 Nov 2016 23:03:35 +0000 (00:03 +0100)]
Bugfix in "scc" command
Clifford Wolf [Fri, 4 Nov 2016 06:46:30 +0000 (07:46 +0100)]
Fixed anonymous genblock object names
Clifford Wolf [Thu, 3 Nov 2016 11:13:23 +0000 (12:13 +0100)]
Added hex constant support to write_verilog
Clifford Wolf [Thu, 3 Nov 2016 09:31:51 +0000 (10:31 +0100)]
We are now in 0.7+ development
Clifford Wolf [Thu, 3 Nov 2016 08:08:43 +0000 (09:08 +0100)]
Yosys 0.7
Clifford Wolf [Wed, 2 Nov 2016 19:09:57 +0000 (20:09 +0100)]
Bugfix in "hierarchy -check"
Clifford Wolf [Wed, 2 Nov 2016 18:25:28 +0000 (19:25 +0100)]
Updated command reference in manual
Clifford Wolf [Wed, 2 Nov 2016 17:53:30 +0000 (18:53 +0100)]
Changelog for Yosys 0.7
Clifford Wolf [Wed, 2 Nov 2016 12:15:49 +0000 (13:15 +0100)]
Added support for fsm_encoding="user"
Clifford Wolf [Wed, 2 Nov 2016 08:31:39 +0000 (09:31 +0100)]
Added "fsm_expand -full"
Clifford Wolf [Tue, 1 Nov 2016 22:17:43 +0000 (23:17 +0100)]
Some fixes in handling of signed arrays
Clifford Wolf [Tue, 1 Nov 2016 10:32:02 +0000 (11:32 +0100)]
iCE40 flow is not experimental anymore
Clifford Wolf [Tue, 1 Nov 2016 10:31:13 +0000 (11:31 +0100)]
Added initial version of "synth_gowin"
Clifford Wolf [Tue, 1 Nov 2016 10:30:27 +0000 (11:30 +0100)]
Adde "write_verilog -renameprefix -v"
Clifford Wolf [Tue, 1 Nov 2016 09:03:13 +0000 (10:03 +0100)]
Added support for (single-clock) transparent memories to bram tests
Clifford Wolf [Tue, 25 Oct 2016 21:21:37 +0000 (23:21 +0200)]
Bugfix in fsm_map for FSMs without reset state
Clifford Wolf [Sat, 22 Oct 2016 09:05:49 +0000 (11:05 +0200)]
Added avail params to ilang format, check module params in 'hierarchy -check'
Clifford Wolf [Wed, 19 Oct 2016 11:54:04 +0000 (13:54 +0200)]
Added "setparam -type"
Clifford Wolf [Wed, 19 Oct 2016 10:44:58 +0000 (12:44 +0200)]
No limit for length of lines in BLIF front-end
Clifford Wolf [Wed, 19 Oct 2016 09:37:04 +0000 (11:37 +0200)]
Merge pull request #250 from azonenberg/master
Add support for more GreenPak cells (edge detector, delay, pattern generator)
Andrew Zonenberg [Wed, 19 Oct 2016 03:46:49 +0000 (20:46 -0700)]
Fixed typo in last commit
Andrew Zonenberg [Wed, 19 Oct 2016 03:42:44 +0000 (20:42 -0700)]
greenpak4: Added GP_PGEN cell definition
Andrew Zonenberg [Wed, 19 Oct 2016 02:53:19 +0000 (19:53 -0700)]
Added GLITCH_FILTER parameter to GP_DELAY
Andrew Zonenberg [Wed, 19 Oct 2016 02:33:26 +0000 (19:33 -0700)]
greenpak4: added model for GP_EDGEDET block
Andrew Zonenberg [Wed, 19 Oct 2016 02:29:25 +0000 (19:29 -0700)]
Merge https://github.com/cliffordwolf/yosys
Clifford Wolf [Tue, 18 Oct 2016 08:54:53 +0000 (10:54 +0200)]
Ignore L_pi nets in "yosys-smtbmc --cex"
Clifford Wolf [Tue, 18 Oct 2016 08:54:04 +0000 (10:54 +0200)]
Use init value "2" for all uninitialized FFs in BLIF back-end
Clifford Wolf [Mon, 17 Oct 2016 12:57:28 +0000 (14:57 +0200)]
Added "yosys-smtbmc --cex <filename>"
Clifford Wolf [Mon, 17 Oct 2016 12:56:58 +0000 (14:56 +0200)]
Bugfix in "miter -assert" handling of assumptions
Clifford Wolf [Mon, 17 Oct 2016 11:28:55 +0000 (13:28 +0200)]
Added clk2fflogic support for $dffsr and $dlatch
Andrew Zonenberg [Mon, 17 Oct 2016 05:53:43 +0000 (22:53 -0700)]
greenpak4: Changed parameters for GP_SYSRESET
Clifford Wolf [Sun, 16 Oct 2016 21:03:29 +0000 (23:03 +0200)]
Improvements and bugfixes in clk2fflogic
Clifford Wolf [Sun, 16 Oct 2016 21:02:51 +0000 (23:02 +0200)]
cleanup in write_smt2 log messages (-bv and -mem are now default)
Clifford Wolf [Sun, 16 Oct 2016 18:37:02 +0000 (20:37 +0200)]
Build fixes for VS 2015
Clifford Wolf [Fri, 14 Oct 2016 16:34:44 +0000 (18:34 +0200)]
Some minor build fixes for Visual C
Clifford Wolf [Fri, 14 Oct 2016 16:20:36 +0000 (18:20 +0200)]
Avoid using strcasecmp()
Clifford Wolf [Fri, 14 Oct 2016 15:18:18 +0000 (17:18 +0200)]
Fixed version string for out-of-tree builds
Clifford Wolf [Fri, 14 Oct 2016 13:39:33 +0000 (15:39 +0200)]
Added notes about some formal features to README
Clifford Wolf [Fri, 14 Oct 2016 13:24:03 +0000 (15:24 +0200)]
Added $anyseq cell type
Clifford Wolf [Fri, 14 Oct 2016 12:55:07 +0000 (14:55 +0200)]
Added clk2fflogic
Clifford Wolf [Fri, 14 Oct 2016 11:02:36 +0000 (13:02 +0200)]
Added opt_rmdff support for $ff cells
Clifford Wolf [Fri, 14 Oct 2016 10:33:56 +0000 (12:33 +0200)]
Added $global_clock verilog syntax support for creating $ff cells
Clifford Wolf [Fri, 14 Oct 2016 08:36:37 +0000 (10:36 +0200)]
Added MEMID handling to "flatten" pass
Clifford Wolf [Fri, 14 Oct 2016 07:36:40 +0000 (09:36 +0200)]
Merge branch 'master' of github.com:cliffordwolf/yosys
Clifford Wolf [Fri, 14 Oct 2016 07:36:31 +0000 (09:36 +0200)]
Merge pull request #246 from set-soft/abc_external_ovr
Allow to overwrite ABCEXTERNAL from the environment.
Clifford Wolf [Fri, 14 Oct 2016 07:35:18 +0000 (09:35 +0200)]
Added YOSYS_VER_STR make variable
Salvador E. Tropea [Thu, 13 Oct 2016 20:57:09 +0000 (17:57 -0300)]
Ugh! extra patches got here, reverting
Salvador E. Tropea [Thu, 13 Oct 2016 20:51:14 +0000 (17:51 -0300)]
Allow to overwrite ABCEXTERNAL from the environment.
In this way Debian scripts can define it as berkeley-abc from the shell.