Marcelina Kościelnicka [Wed, 15 Jul 2020 00:37:43 +0000 (02:37 +0200)]
peepopt: Remove now-redundant dffmux pattern.
Marcelina Kościelnicka [Wed, 15 Jul 2020 00:54:40 +0000 (02:54 +0200)]
Remove now-redundant opt_rmdff pass.
Marcelina Kościelnicka [Mon, 20 Jul 2020 21:19:51 +0000 (23:19 +0200)]
Replace opt_rmdff with opt_dff.
Claire Wolf [Fri, 31 Jul 2020 18:57:41 +0000 (20:57 +0200)]
Bump YOSYS_VER
Signed-off-by: Claire Wolf <claire@symbioticeda.com>
Marcelina Kościelnicka [Mon, 27 Jul 2020 13:24:57 +0000 (15:24 +0200)]
Add dffunmap pass.
To be used with backends that cannot deal with fancy FF types (like blif
or smt).
Marcelina Kościelnicka [Fri, 24 Jul 2020 11:08:54 +0000 (13:08 +0200)]
opt_expr: Remove -clkinv option, make it the default.
Adds -noclkinv option just in case the old behavior was actually useful
to someone.
Marcelina Kościelnicka [Wed, 22 Jul 2020 11:34:11 +0000 (13:34 +0200)]
synth_ice40: Use opt_dff.
The main part is converting ice40_dsp to recognize the new FF types
created in opt_dff instead of trying to recognize the mux patterns on
its own.
The fsm call has been moved upwards because the passes cannot deal with
$dffe/$sdff*, and other optimizations don't help it much anyway.
Marcelina Kościelnicka [Wed, 22 Jul 2020 10:27:15 +0000 (12:27 +0200)]
synth_xilinx: Use opt_dff.
The main part is converting xilinx_dsp to recognize the new FF types
created in opt_dff instead of trying to recognize the patterns on its
own.
The fsm call has been moved upwards because the passes cannot deal with
$dffe/$sdff*, and other optimizations don't help it much anyway.
Marcelina Kościelnicka [Fri, 24 Jul 2020 15:01:26 +0000 (17:01 +0200)]
async2sync: Support all FF types.
Marcelina Kościelnicka [Tue, 14 Jul 2020 22:58:07 +0000 (00:58 +0200)]
Add opt_dff pass.
Marcelina Kościelnicka [Tue, 23 Jun 2020 21:46:00 +0000 (23:46 +0200)]
verilog_backend: Add handling for all FF types.
Miodrag Milanović [Wed, 29 Jul 2020 13:41:26 +0000 (15:41 +0200)]
Merge pull request #2314 from YosysHQ/verifix_errorfix
Verific - prevent exit yosys due to stored error
Miodrag Milanovic [Wed, 29 Jul 2020 13:28:33 +0000 (15:28 +0200)]
Clear last error message
Marcelina Kościelnicka [Wed, 29 Jul 2020 08:00:01 +0000 (10:00 +0200)]
opt_expr: Fix handling of $_XNOR_ cells with A = B.
Fixes #2311.
Marcelina Kościelnicka [Tue, 28 Jul 2020 00:11:29 +0000 (02:11 +0200)]
ffinit: Fortify the code a bit.
This fixes handling of messy cases involving repeatedly setting and
removing the same init bit.
clairexen [Tue, 28 Jul 2020 12:07:26 +0000 (14:07 +0200)]
Merge pull request #2301 from zachjs/for-loop-errors
Clearer for loop error messages
clairexen [Tue, 28 Jul 2020 10:56:22 +0000 (12:56 +0200)]
Merge pull request #2306 from YosysHQ/mwk/equiv_induct-undef
equiv_induct: Fix up assumption for $equiv cells in -undef mode.
Marcelina Kościelnicka [Mon, 27 Jul 2020 16:28:01 +0000 (18:28 +0200)]
equiv_induct: Fix up assumption for $equiv cells in -undef mode.
Before this fix, equiv_induct only assumed that one of the following is
true:
- defined value of A is equal to defined value of B
- A is undefined
This lets through valuations where A is defined, B is undefined, and
the defined (meaningless) value of B happens to match the defined value
of A. Instead, tighten this up to OR of the following:
- defined value of A is equal to defined value of B, and B is not
undefined
- A is undefined
Dan Ravensloft [Sun, 26 Jul 2020 18:28:10 +0000 (19:28 +0100)]
intel_alm: direct M10K instantiation
This reverts commit
a3a90f6377f251d3b6c5898eb1543f8832493bb8.
Dan Ravensloft [Sun, 26 Jul 2020 18:11:55 +0000 (19:11 +0100)]
intel_alm: increase abc9 -W
clairexen [Sun, 26 Jul 2020 19:34:55 +0000 (21:34 +0200)]
Merge pull request #2299 from zachjs/arg-loop
Avoid generating wires for function args which are constant
Zachary Snow [Sat, 25 Jul 2020 16:35:03 +0000 (10:35 -0600)]
Clearer for loop error messages
Zachary Snow [Sat, 25 Jul 2020 03:18:24 +0000 (21:18 -0600)]
Avoid generating wires for function args which are constant
Marcelina Kościelnicka [Sun, 19 Jul 2020 01:25:30 +0000 (03:25 +0200)]
async2sync: Refactor to use FfInitVals.
Marcelina Kościelnicka [Sun, 19 Jul 2020 00:28:55 +0000 (02:28 +0200)]
memory_dff: Refactor to use FfInitVals.
Marcelina Kościelnicka [Sun, 19 Jul 2020 00:25:32 +0000 (02:25 +0200)]
proc_dlatch: Refactor to use FfInitVals.
Marcelina Kościelnicka [Sun, 19 Jul 2020 00:19:38 +0000 (02:19 +0200)]
pmux2shift: Refactor to use FfInitVals.
Marcelina Kościelnicka [Sun, 19 Jul 2020 00:19:23 +0000 (02:19 +0200)]
wreduce: Refactor to use FfInitVals.
Marcelina Kościelnicka [Sun, 19 Jul 2020 00:17:31 +0000 (02:17 +0200)]
techmap: Refactor to use FfInitVals.
Marcelina Kościelnicka [Sun, 19 Jul 2020 00:14:15 +0000 (02:14 +0200)]
shregmap: Refactor to use FfInitVals.
Marcelina Kościelnicka [Sun, 19 Jul 2020 00:07:24 +0000 (02:07 +0200)]
abc: Refactor to use FfInitVals.
Marcelina Kościelnicka [Sun, 19 Jul 2020 00:06:25 +0000 (02:06 +0200)]
dffinit: Refactor to use FfInitVals.
Marcelina Kościelnicka [Sun, 19 Jul 2020 00:05:32 +0000 (02:05 +0200)]
zinit: Refactor to use FfInitVals.
Marcelina Kościelnicka [Sun, 19 Jul 2020 00:04:38 +0000 (02:04 +0200)]
dfflegalize: Refactor to use FfInitVals.
Marcelina Kościelnicka [Sun, 19 Jul 2020 01:25:41 +0000 (03:25 +0200)]
clk2fflogic: Support all FF types.
Marcelina Kościelnicka [Mon, 20 Jul 2020 20:49:30 +0000 (22:49 +0200)]
satgen: Add support for dffe, sdff, sdffe, sdffce cells.
Marcelina Kościelnicka [Sun, 19 Jul 2020 01:51:05 +0000 (03:51 +0200)]
Add utility module for representing flip-flops.
Marcelina Kościelnicka [Mon, 20 Jul 2020 21:58:00 +0000 (23:58 +0200)]
memory_dff: recognize more dff cells
Marcelina Kościelnicka [Sat, 18 Jul 2020 23:59:47 +0000 (01:59 +0200)]
Add utility module for dealing with init attributes.
clairexen [Thu, 23 Jul 2020 16:39:42 +0000 (18:39 +0200)]
Merge pull request #2285 from YosysHQ/mwk/techmap-cellname
techmap: Add _TECHMAP_CELLNAME_ special parameter.
clairexen [Thu, 23 Jul 2020 16:21:20 +0000 (18:21 +0200)]
Merge pull request #2294 from Ravenslofty/intel_alm_timings
intel_alm: add additional ABC9 timings
Dan Ravensloft [Tue, 21 Jul 2020 12:58:38 +0000 (13:58 +0100)]
intel_alm: add additional ABC9 timings
Keith Rothman [Mon, 19 Aug 2019 15:42:09 +0000 (08:42 -0700)]
Remove EXPLICIT_CARRY logic.
The symbiflow-arch-defs tool chain no longer needs the EXPLICIT_CARRY
within yosys itself.
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
Marcelina Kościelnicka [Tue, 21 Jul 2020 13:00:54 +0000 (15:00 +0200)]
techmap: Add _TECHMAP_CELLNAME_ special parameter.
This parameter will resolve to the name of the cell being mapped. The
first user of this parameter will be synth_intel_alm's Quartus output,
which requires a unique (and preferably descriptive) name passed as
a cell parameter for the memory cells.
clairexen [Tue, 21 Jul 2020 12:43:33 +0000 (14:43 +0200)]
Merge pull request #2215 from boqwxp/qbfsat-solver-options
qbfsat, smt2, smtio: Add `-solver-option` to allow specifying SMT-LIBv2 `(set-option ...)` commands
Alberto Gonzalez [Mon, 20 Jul 2020 22:09:44 +0000 (22:09 +0000)]
smtio: Emit `mode: start` options before `set-logic` command and any other options after it.
Refer to the SMT-LIB specification, section 4.1.7. According to the spec, some options can only be specified in `start` mode. Once the solver sees `set-logic`, it moves to `assert` mode.
Alberto Gonzalez [Wed, 1 Jul 2020 20:04:56 +0000 (20:04 +0000)]
smtio: Add support for parsing `yosys-smt2-solver-option` info statements.
Alberto Gonzalez [Mon, 29 Jun 2020 04:41:18 +0000 (04:41 +0000)]
qbfsat: Add `-solver-option` option.
Alberto Gonzalez [Wed, 1 Jul 2020 20:51:14 +0000 (20:51 +0000)]
smt2: Add `-solver-option` option.
clairexen [Mon, 20 Jul 2020 21:06:36 +0000 (23:06 +0200)]
Merge pull request #2282 from YosysHQ/claire/satunsat
Only allow "sat" and "unsat" smt solver responses in yosys-smtbmc
Marcelina Kościelnicka [Mon, 20 Jul 2020 19:43:05 +0000 (21:43 +0200)]
celltypes: Fix EN port name for some FF types.
Claire Wolf [Mon, 20 Jul 2020 17:35:32 +0000 (19:35 +0200)]
Only allow "sat" and "unsat" smt solver responses in yosys-smtbmc
Signed-off-by: Claire Wolf <claire@symbioticeda.com>
clairexen [Mon, 20 Jul 2020 13:23:14 +0000 (15:23 +0200)]
Merge pull request #2276 from YosysHQ/mwk/satgen-cc
satgen: Move importCell out of the header.
Marcelina Kościelnicka [Sat, 18 Jul 2020 22:17:02 +0000 (00:17 +0200)]
satgen: Move importCell out of the header.
This function has no hope of ever getting inlined anyway, and it speeds
up yosys compile time by 7%.
Miodrag Milanović [Fri, 17 Jul 2020 13:05:46 +0000 (15:05 +0200)]
Merge pull request #2275 from YosysHQ/mwk/sf2-clkint-fix
sf2: Emit CLKINT even if -clkbuf not passed
Marcelina Kościelnicka [Fri, 17 Jul 2020 13:01:45 +0000 (15:01 +0200)]
sf2: Emit CLKINT even if -clkbuf not passed
This restores pre #2229 behavior.
Miodrag Milanović [Fri, 17 Jul 2020 12:39:31 +0000 (14:39 +0200)]
Merge pull request #2274 from YosysHQ/mwk/anlogic-ff-fix
anlogic: Fix FF mapping.
Marcelina Kościelnicka [Fri, 17 Jul 2020 12:03:21 +0000 (14:03 +0200)]
anlogic: Fix FF mapping.
clairexen [Thu, 16 Jul 2020 16:33:56 +0000 (18:33 +0200)]
Merge pull request #2229 from Ravenslofty/sf2_remove_sf2_iobs
sf2: replace sf2_iobs with {clkbuf,iopad}map
clairexen [Thu, 16 Jul 2020 16:30:50 +0000 (18:30 +0200)]
Merge pull request #2273 from whitequark/write-verilog-always-star-initial
verilog_backend: in non-SV mode, add a trigger for `always @*`
clairexen [Thu, 16 Jul 2020 16:28:24 +0000 (18:28 +0200)]
Merge pull request #2272 from whitequark/write-verilog-sv
verilog_backend: add `-sv` option, make `-o <filename>.sv` work
Miodrag Milanović [Thu, 16 Jul 2020 16:07:58 +0000 (18:07 +0200)]
Merge pull request #2238 from YosysHQ/mwk/dfflegalize-anlogic
anlogic: Use dfflegalize.
Miodrag Milanović [Thu, 16 Jul 2020 16:07:41 +0000 (18:07 +0200)]
Merge pull request #2226 from YosysHQ/mwk/nuke-efinix-gbuf
efinix: Nuke efinix_gbuf in favor of clkbufmap.
whitequark [Thu, 16 Jul 2020 11:26:31 +0000 (11:26 +0000)]
verilog_backend: in non-SV mode, add a trigger for `always @*`.
This commit only affects translation of RTLIL processes (for which
there is limited support).
Due to the event-driven nature of Verilog, processes like
reg x;
always @*
x <= 1;
may never execute. This can be fixed in SystemVerilog code by using
`always_comb` instead of `always @*`, but in Verilog-2001 the options
are limited. This commit implements the following workaround:
reg init = 0;
reg x;
always @* begin
if (init) begin end
x <= 1;
end
Fixes #2271.
whitequark [Thu, 16 Jul 2020 10:34:21 +0000 (10:34 +0000)]
verilog_backend: add `-sv` option, make `-o <filename>.sv` work.
See #2271.
whitequark [Thu, 16 Jul 2020 09:48:10 +0000 (09:48 +0000)]
Merge pull request #2270 from whitequark/cxxrtl-fix-typo
cxxrtl: fix typo
whitequark [Wed, 15 Jul 2020 19:20:33 +0000 (19:20 +0000)]
Merge pull request #2269 from YosysHQ/claire/bisonwall
Use "bison -Wall -Werror" for verilog front-end
Claire Wolf [Wed, 15 Jul 2020 09:57:31 +0000 (11:57 +0200)]
Treat all bison warnings as errors in verilog front-end
Signed-off-by: Claire Wolf <claire@symbioticeda.com>
Claire Wolf [Wed, 15 Jul 2020 09:54:28 +0000 (11:54 +0200)]
Use %precedence in verilog_parser.y
Signed-off-by: Claire Wolf <claire@symbioticeda.com>
Claire Wolf [Tue, 14 Jul 2020 22:04:23 +0000 (00:04 +0200)]
Fix bison warnings for missing %empty
Signed-off-by: Claire Wolf <claire@symbioticeda.com>
Claire Wolf [Tue, 14 Jul 2020 22:04:04 +0000 (00:04 +0200)]
Run bison with -Wall for verilog front-end
Signed-off-by: Claire Wolf <claire@symbioticeda.com>
clairexen [Wed, 15 Jul 2020 09:49:09 +0000 (11:49 +0200)]
Merge pull request #2257 from antmicro/fix-conflicts
Restore #2203 and #2244 and fix parser conflicts
Kamil Rakoczy [Wed, 15 Jul 2020 08:15:13 +0000 (10:15 +0200)]
Add missing semicolons
Signed-off-by: Kamil Rakoczy <krakoczy@antmicro.com>
Marcelina Kościelnicka [Wed, 15 Jul 2020 00:30:25 +0000 (02:30 +0200)]
opt_merge: Dedup one more use of FF cell type list.
Marcelina Kościelnicka [Thu, 2 Jul 2020 22:22:28 +0000 (00:22 +0200)]
achronix: Use dfflegalize.
whitequark [Tue, 14 Jul 2020 16:10:30 +0000 (16:10 +0000)]
cxxrtl: fix typo. NFC.
Marcelina Kościelnicka [Thu, 2 Jul 2020 22:22:44 +0000 (00:22 +0200)]
anlogic: Use dfflegalize.
Marcelina Kościelnicka [Sun, 5 Jul 2020 02:02:42 +0000 (04:02 +0200)]
intel: Use dfflegalize.
Lofty [Mon, 13 Jul 2020 13:08:52 +0000 (14:08 +0100)]
Revert "intel_alm: direct M10K instantiation"
This reverts commit
09ecb9b2cf3ab76841d30712bf70dafc6d47ef67.
whitequark [Mon, 13 Jul 2020 02:44:36 +0000 (02:44 +0000)]
Merge pull request #2263 from whitequark/cxxrtl-capi-eval-commit
cxxrtl: expose eval() and commit() via the C API
whitequark [Sun, 12 Jul 2020 23:34:18 +0000 (23:34 +0000)]
cxxrtl: expose eval() and commit() via the C API.
Marcelina Kościelnicka [Sun, 12 Jul 2020 15:54:07 +0000 (17:54 +0200)]
xilinx: Fix srl regression.
Of standard yosys cells, xilinx_srl only works on $_DFF_?_ and
$_DFFE_?P_, which get upgraded to $_SDFFE_?P?P_ by dfflegalize at the
point where xilinx_srl is called for non-abc9. Fix this by running
ff_map.v first, resulting in FDRE cells, which are handled correctly.
Marcelina Kościelnicka [Sun, 12 Jul 2020 13:38:51 +0000 (15:38 +0200)]
proc_dlatch: Remove init values for combinatorial processes.
Fixes #2258.
Marcelina Kościelnicka [Sun, 12 Jul 2020 13:39:40 +0000 (15:39 +0200)]
dfflegalize: Gather init values from all wires.
Skipping non-selected wires is unsound in an obvious way.
clairexen [Fri, 10 Jul 2020 17:07:50 +0000 (19:07 +0200)]
Merge pull request #2256 from YosysHQ/claire/fix2241
Add AST_EDGE support to AstNode::detect_latch()
Claire Wolf [Fri, 10 Jul 2020 16:41:13 +0000 (18:41 +0200)]
Add AST_EDGE support to AstNode::detect_latch(), fixes #2241
Signed-off-by: Claire Wolf <claire@symbioticeda.com>
Kamil Rakoczy [Fri, 10 Jul 2020 12:56:14 +0000 (14:56 +0200)]
Fix S/R conflicts
This commit fixes S/R conflicts introduced by commit
6f9be93.
Signed-off-by: Kamil Rakoczy <krakoczy@antmicro.com>
Kamil Rakoczy [Fri, 10 Jul 2020 08:14:31 +0000 (10:14 +0200)]
Fix R/R conflicts
This commit fixes R/R conflicts introduced by commit
7e83a51.
Parameter logic is already defined as part of `param_range_type` rule.
Signed-off-by: Kamil Rakoczy <krakoczy@antmicro.com>
Kamil Rakoczy [Fri, 10 Jul 2020 07:59:48 +0000 (09:59 +0200)]
Revert "Revert PRs #2203 and #2244."
This reverts commit
9c120b89ace6c111aa4677616947d18d980b9c1a.
Dan Ravensloft [Sat, 4 Jul 2020 20:20:26 +0000 (21:20 +0100)]
sf2: replace sf2_iobs with {clkbuf,iopad}map
whitequark [Thu, 9 Jul 2020 20:17:19 +0000 (20:17 +0000)]
Merge pull request #2255 from whitequark/bison-Werror-conflicts
verilog_parser: turn S/R and R/R conflicts into hard errors
whitequark [Thu, 9 Jul 2020 20:17:12 +0000 (20:17 +0000)]
Merge pull request #2254 from whitequark/cxxrtl-extern-c
cxxrtl: add missing extern "C"
Marcelina Kościelnicka [Thu, 2 Jul 2020 16:22:29 +0000 (18:22 +0200)]
sf2: Use dfflegalize.
whitequark [Thu, 9 Jul 2020 19:36:39 +0000 (19:36 +0000)]
verilog_parser: turn S/R and R/R conflicts into hard errors.
Fixes #2253.
whitequark [Thu, 9 Jul 2020 18:13:04 +0000 (18:13 +0000)]
whitequark [Thu, 9 Jul 2020 17:52:52 +0000 (17:52 +0000)]
cxxrtl: add missing extern "C".
This bug was hidden if a header was generated.
Marcelina Kościelnicka [Tue, 23 Jun 2020 16:51:51 +0000 (18:51 +0200)]
xilinx: Use dfflegalize.
Marcelina Kościelnicka [Thu, 2 Jul 2020 16:22:43 +0000 (18:22 +0200)]
dfflibmap: Refactor to use dfflegalize internally.
Lucas Castro [Thu, 9 Jul 2020 16:50:26 +0000 (13:50 -0300)]
Fix issue #2251 (#2252)
* Fix #2251 - YosysJS ReferenceError: _memset is not defined.
Add '_memset' in emcc EXPORTED_FUNCTIONS in Makefile.
Marcelina Kościelnicka [Sat, 4 Jul 2020 21:09:00 +0000 (23:09 +0200)]
clkbufmap: improve input pad handling.
- allow inserting only the input pad cell
- do not insert the usual buffer if the input pad already acts as a
buffer