Jean THOMAS [Mon, 6 Jul 2020 11:12:13 +0000 (13:12 +0200)]
Make RefreshTimer fully synchronous (#24)
Jean THOMAS [Mon, 6 Jul 2020 10:51:24 +0000 (12:51 +0200)]
Add write transactions in the simulation testbench
Jean THOMAS [Mon, 6 Jul 2020 10:49:37 +0000 (12:49 +0200)]
Reduce amount of combinatorial statements to improve frequency (#24)
Jean THOMAS [Mon, 6 Jul 2020 10:45:53 +0000 (12:45 +0200)]
Fix formal support in FHDLTestCase
Jean THOMAS [Fri, 3 Jul 2020 17:47:47 +0000 (19:47 +0200)]
Remove Diamond install script
Jean THOMAS [Fri, 3 Jul 2020 17:46:01 +0000 (19:46 +0200)]
Add SourceHut badge
Jean THOMAS [Fri, 3 Jul 2020 17:44:04 +0000 (19:44 +0200)]
Add .gitattributes file
Jean THOMAS [Fri, 3 Jul 2020 17:40:09 +0000 (19:40 +0200)]
Remove Diamond install as it only comes with models if activated
Jean THOMAS [Fri, 3 Jul 2020 16:27:16 +0000 (18:27 +0200)]
Use CRG parameters that actually work on hardware
Jean THOMAS [Fri, 3 Jul 2020 16:21:00 +0000 (18:21 +0200)]
Update CRG with parameters that work IRL
Jean THOMAS [Fri, 3 Jul 2020 16:19:25 +0000 (18:19 +0200)]
Invert condition in runsimcrg.sh
Jean THOMAS [Fri, 3 Jul 2020 15:52:38 +0000 (17:52 +0200)]
Remove remainings from TRELLIS_IO
Jean THOMAS [Fri, 3 Jul 2020 15:27:41 +0000 (17:27 +0200)]
Check if YOSYS env var is set and use it as YOSYS executable
Jean THOMAS [Fri, 3 Jul 2020 15:05:20 +0000 (17:05 +0200)]
Use Yosys from YoWASP
Jean THOMAS [Fri, 3 Jul 2020 14:50:51 +0000 (16:50 +0200)]
Fix permissions for simulation script
Jean THOMAS [Fri, 3 Jul 2020 14:38:50 +0000 (16:38 +0200)]
Add simulation script into SourceHut builds
Jean THOMAS [Fri, 3 Jul 2020 14:37:47 +0000 (16:37 +0200)]
Exclude DDRDLLA from tree
Jean THOMAS [Fri, 3 Jul 2020 14:36:22 +0000 (16:36 +0200)]
Ensure dramsync runs at 100Mhz, sync2x at 200Mhz
Jean THOMAS [Fri, 3 Jul 2020 13:22:13 +0000 (15:22 +0200)]
Remove DDRDLLA
Jean THOMAS [Fri, 3 Jul 2020 12:56:28 +0000 (14:56 +0200)]
Add build script for SourceHut
Jean THOMAS [Fri, 3 Jul 2020 12:55:20 +0000 (14:55 +0200)]
Add tests in DFI Injector for odt and reset signals
Jean THOMAS [Fri, 3 Jul 2020 12:51:10 +0000 (14:51 +0200)]
Check for additional signals in phase injector at t=0
Jean THOMAS [Fri, 3 Jul 2020 12:50:43 +0000 (14:50 +0200)]
Add DFI injector test case
Jean THOMAS [Fri, 3 Jul 2020 12:32:41 +0000 (14:32 +0200)]
Update simulation gitignore
Jean THOMAS [Fri, 3 Jul 2020 12:32:10 +0000 (14:32 +0200)]
Update gram simulation documentation
Jean THOMAS [Fri, 3 Jul 2020 12:30:18 +0000 (14:30 +0200)]
Add cleaning pass
Jean THOMAS [Fri, 3 Jul 2020 12:29:32 +0000 (14:29 +0200)]
Fix autopep8 madness
Jean THOMAS [Fri, 3 Jul 2020 12:25:45 +0000 (14:25 +0200)]
Rework CRG simulation
Jean THOMAS [Fri, 3 Jul 2020 12:24:37 +0000 (14:24 +0200)]
Externalize CRG into its own file
Jean THOMAS [Fri, 3 Jul 2020 11:40:43 +0000 (13:40 +0200)]
Add devel doc
Jean THOMAS [Fri, 3 Jul 2020 11:29:11 +0000 (13:29 +0200)]
Add test for Refresher
Jean THOMAS [Fri, 3 Jul 2020 11:23:46 +0000 (13:23 +0200)]
Refactor generic_test execution
Jean THOMAS [Fri, 3 Jul 2020 11:15:05 +0000 (13:15 +0200)]
Use spaces for indentation
Jean THOMAS [Fri, 3 Jul 2020 11:08:07 +0000 (13:08 +0200)]
Add tests for core/refresher.py
Jean THOMAS [Fri, 3 Jul 2020 11:07:46 +0000 (13:07 +0200)]
Removing reset=0 attribute as it is already the default choice in nMigen
Jean THOMAS [Thu, 2 Jul 2020 13:34:12 +0000 (15:34 +0200)]
Use reset signal from dramsync instead of sync
Jean THOMAS [Thu, 2 Jul 2020 12:17:44 +0000 (14:17 +0200)]
Make RefreshPostponer more similar to LiteDRAM's
Jean THOMAS [Thu, 2 Jul 2020 12:07:32 +0000 (14:07 +0200)]
Fix RefreshPostponer output stuck to 1
Jean THOMAS [Thu, 2 Jul 2020 11:22:32 +0000 (13:22 +0200)]
Flatten specific parts of the designs
Jean THOMAS [Thu, 2 Jul 2020 11:18:11 +0000 (13:18 +0200)]
Add missing command issue strobe for ZQ calibration
Jean THOMAS [Thu, 2 Jul 2020 09:27:13 +0000 (11:27 +0200)]
Remove PyYAML dependency
Jean THOMAS [Thu, 2 Jul 2020 09:02:54 +0000 (11:02 +0200)]
Fix register addresses, add missing command_issue strobe
Jean THOMAS [Thu, 2 Jul 2020 09:02:08 +0000 (11:02 +0200)]
Set names to prevent CSR/DomainRenamer incompatibility
Jean THOMAS [Thu, 2 Jul 2020 08:59:38 +0000 (10:59 +0200)]
Add DDRDLLA patch
Jean THOMAS [Wed, 1 Jul 2020 18:09:56 +0000 (20:09 +0200)]
Fix merge
Jean THOMAS [Wed, 1 Jul 2020 18:06:38 +0000 (20:06 +0200)]
Rework indentation and add Wishbone tests
Jean THOMAS [Wed, 1 Jul 2020 17:00:15 +0000 (19:00 +0200)]
Add Wishbone interaction code
Jean THOMAS [Wed, 1 Jul 2020 17:00:15 +0000 (19:00 +0200)]
Add Wishbone interaction code
Jean THOMAS [Wed, 1 Jul 2020 16:57:52 +0000 (18:57 +0200)]
Fix Iverilog simulation
Jean THOMAS [Wed, 1 Jul 2020 11:38:41 +0000 (13:38 +0200)]
Generate ilang file
Jean THOMAS [Tue, 30 Jun 2020 17:28:34 +0000 (19:28 +0200)]
Build nMigen gateware in a specific folder
Jean THOMAS [Tue, 30 Jun 2020 17:27:18 +0000 (19:27 +0200)]
Remove LED code in CRG
Jean THOMAS [Tue, 30 Jun 2020 17:26:58 +0000 (19:26 +0200)]
Remove Minerva dependency
Jean THOMAS [Tue, 30 Jun 2020 09:33:03 +0000 (11:33 +0200)]
Applying #
9044c10 changes in LiteDRAM (phy/ecp5ddrphy: use sys_rst instead of sys2x_rst as reset on primitives and do sys2x reset externally.)
Jean THOMAS [Mon, 29 Jun 2020 14:22:09 +0000 (16:22 +0200)]
Define simulation time as a parameter
Jean THOMAS [Mon, 29 Jun 2020 12:46:59 +0000 (14:46 +0200)]
Define PLL's PHASELOADREG input
Jean THOMAS [Mon, 29 Jun 2020 12:40:55 +0000 (14:40 +0200)]
Use -n option in vvp to enable CTRL+C
Jean THOMAS [Mon, 29 Jun 2020 12:37:02 +0000 (14:37 +0200)]
Fix PLL instanciation code for CRG simulation
Jean THOMAS [Mon, 29 Jun 2020 12:36:39 +0000 (14:36 +0200)]
Dump whole module
Jean THOMAS [Mon, 29 Jun 2020 12:35:45 +0000 (14:35 +0200)]
Fix DQSBUFM floating DYNDELAY
Jean THOMAS [Mon, 29 Jun 2020 12:29:51 +0000 (14:29 +0200)]
Set DRAM's CK_N to low
Jean THOMAS [Mon, 29 Jun 2020 12:27:52 +0000 (14:27 +0200)]
Fix autopep8 madness
Jean THOMAS [Mon, 29 Jun 2020 12:26:51 +0000 (14:26 +0200)]
Use BB instead of TRELLIS_IO
Jean THOMAS [Mon, 29 Jun 2020 12:25:45 +0000 (14:25 +0200)]
Fix CRG, revert to resetful sync domain
Jean THOMAS [Mon, 29 Jun 2020 12:25:19 +0000 (14:25 +0200)]
Set UART RX to 1'b1
Jean THOMAS [Mon, 29 Jun 2020 12:24:33 +0000 (14:24 +0200)]
Add -Wall to simulations
Jean THOMAS [Fri, 26 Jun 2020 14:41:55 +0000 (16:41 +0200)]
Add testbench for SoC simulation
Jean THOMAS [Fri, 26 Jun 2020 14:41:31 +0000 (16:41 +0200)]
Use FST instead of VCD
Jean THOMAS [Fri, 26 Jun 2020 14:41:17 +0000 (16:41 +0200)]
Exclude .fst files
Jean THOMAS [Fri, 26 Jun 2020 13:20:34 +0000 (15:20 +0200)]
Add DDRSoC simulation
Jean THOMAS [Fri, 26 Jun 2020 13:19:52 +0000 (15:19 +0200)]
Add gitignore for simulation folder
Jean THOMAS [Fri, 26 Jun 2020 13:19:06 +0000 (15:19 +0200)]
Fix PLL code
Jean THOMAS [Fri, 26 Jun 2020 10:00:36 +0000 (12:00 +0200)]
Add DRAM model
Jean THOMAS [Thu, 25 Jun 2020 20:29:41 +0000 (22:29 +0200)]
Fix typo
Jean THOMAS [Thu, 25 Jun 2020 19:00:20 +0000 (21:00 +0200)]
Add simulation code
Jean THOMAS [Thu, 25 Jun 2020 13:10:50 +0000 (15:10 +0200)]
Add README.md for gram tests
Jean THOMAS [Thu, 25 Jun 2020 11:47:43 +0000 (13:47 +0200)]
Add rddata_en, wrdata_mask tests
Jean THOMAS [Thu, 25 Jun 2020 11:40:04 +0000 (13:40 +0200)]
Add wrdata, wrdata_en tests to Phase Injector unit tests
Jean THOMAS [Thu, 25 Jun 2020 10:50:45 +0000 (12:50 +0200)]
Fix R/W permissions to the bare minimum
Jean THOMAS [Thu, 25 Jun 2020 10:35:36 +0000 (12:35 +0200)]
Set UART bridge SEL signals to 0xF
Jean THOMAS [Thu, 25 Jun 2020 10:32:49 +0000 (12:32 +0200)]
Add Wishbone read/write helpers
Jean THOMAS [Thu, 25 Jun 2020 10:32:36 +0000 (12:32 +0200)]
Use constants for CSR addresses
Jean THOMAS [Thu, 25 Jun 2020 10:28:48 +0000 (12:28 +0200)]
Add bank address test
Jean THOMAS [Thu, 25 Jun 2020 10:26:25 +0000 (12:26 +0200)]
Fix DFII testing, test address set
Jean THOMAS [Wed, 24 Jun 2020 16:53:01 +0000 (18:53 +0200)]
Add buggy test for DFII
Jean THOMAS [Wed, 24 Jun 2020 15:59:50 +0000 (17:59 +0200)]
Fix CSR issue in PhaseInjector (r_data used for reading host data)
Jean THOMAS [Wed, 24 Jun 2020 15:56:31 +0000 (17:56 +0200)]
Fix CSR issue in DFII (r_data used for reading host data)
Jean THOMAS [Wed, 24 Jun 2020 08:56:21 +0000 (10:56 +0200)]
Simply arbiter when there is only 1 request to arbitrate
Jean THOMAS [Wed, 24 Jun 2020 08:34:39 +0000 (10:34 +0200)]
Ensure we have at least one master
Jean THOMAS [Tue, 23 Jun 2020 19:50:44 +0000 (21:50 +0200)]
Only declare wants_zqcs signal if needed
Jean THOMAS [Tue, 23 Jun 2020 19:16:12 +0000 (21:16 +0200)]
Simplify connections from refreshers to IOs (not FSM state dependent anymore)
Jean THOMAS [Tue, 23 Jun 2020 15:37:26 +0000 (17:37 +0200)]
Refactor test code
Jean THOMAS [Tue, 23 Jun 2020 14:10:12 +0000 (16:10 +0200)]
Fix DFII bitfield constants
Jean THOMAS [Tue, 23 Jun 2020 14:09:17 +0000 (16:09 +0200)]
Fix public libgram header
Jean THOMAS [Tue, 23 Jun 2020 14:09:04 +0000 (16:09 +0200)]
Compile libgram as C99 code
Jean THOMAS [Tue, 23 Jun 2020 12:44:05 +0000 (14:44 +0200)]
Fix typo in GramWidth enum declaration
Jean THOMAS [Tue, 23 Jun 2020 11:56:31 +0000 (13:56 +0200)]
Fix ZQCSExecuter (set a signal to the proper size), and fix ba in both ZQCSExecuter, RefreshSequencer and RefreshExecuter
Jean THOMAS [Tue, 23 Jun 2020 11:48:44 +0000 (13:48 +0200)]
Refresher: fix a address size (fixes #14)
Jean THOMAS [Mon, 22 Jun 2020 16:02:42 +0000 (18:02 +0200)]
Remove shadowing statement
Jean THOMAS [Mon, 22 Jun 2020 15:54:05 +0000 (17:54 +0200)]
Replace bits_for with range