mesa: remove INV_SQRTF() macro

Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>

mesa: remove ceilf, floorf macros

Reviewed-by: Matt Turner <mattst88@gmail.com>

mesa: remove expf macro

Reviewed-by: Matt Turner <mattst88@gmail.com>

mesa: remove logf macro

Reviewed-by: Matt Turner <mattst88@gmail.com>

mesa: remove powf macro

Use the wrapper in c99_math.h if needed.

Reviewed-by: Matt Turner <mattst88@gmail.com>

mesa: remove unused exp2f, log2f, truncf wrappers

Reviewed-by: Matt Turner <mattst88@gmail.com>

mesa: remove unused acosf, asinf, atan2f, etc. macros

Not used anywhere.  If any of these are needed, they should be added
to c99_math.h

Reviewed-by: Matt Turner <mattst88@gmail.com>

mesa: replace FABSF with fabsf

Reviewed-by: Matt Turner <mattst88@gmail.com>

mesa: replace FLOORF with floorf

Reviewed-by: Matt Turner <mattst88@gmail.com>

mesa: remove unused CEILF macro

Reviewed-by: Matt Turner <mattst88@gmail.com>

mesa: replace LOGF, EXPF with logf, expf

Reviewed-by: Matt Turner <mattst88@gmail.com>

mesa: replace FREXPF, LDEXPF with frexpf, ldexpf

Start getting rid of some imports.h macros.  Use the c99 functions instead.

Reviewed-by: Matt Turner <mattst88@gmail.com>

targets/libgl-xlib: add src/ include dir to fix build

swrast: fix a few release build warnings

r600g,radeonsi: fix streamout after pipeline stats have been used

EVENT_TYPE_PIPELINESTAT_STOP disables streamout queries too.

Luckily, pipeline stats are enabled by default, so we don't even have to
emit EVENT_TYPE_PIPELINESTAT_START.

Tested on Hawaii, Bonaire, Redwood, RV730.

Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>

radeonsi: small cleanup around current_rast_prim

- remove the last parameter of si_emit_rasterizer_prim_state
- remove the last unused parameter of si_emit_draw_registers
- use current_rast_prim in si_emit_draw_registers

Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>

radeonsi: set current_rast_prim in the right place

Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>

radeonsi: simplify obtaining a shader property in si_emit_clip_regs

Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>

radeonsi: only preload VertexID for the GS copy shader

The copy shader doesn't use any other preloaded VGPRs.

Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>

radeonsi: dump the shader key when dumping shaders

Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>

r600g,radeonsi: cleanup of hex literals

0x3F800000 -> fui(1.0)
0x00000000 -> 0

Reviewed-by: Dave Airlie <airlied@redhat.com>
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>

radeonsi: set PA_SU_HARDWARE_SCREEN_OFFSET to 0

It was probably 0 already, but it doesn't hurt to set it.

Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>

st/mesa: cleanup st_translate_geometry_program

Mostly dead code or code that didn't do anything.

Computing gs_num_outputs at the end was also useless. It's already set
correctly.

Reviewed-by: Dave Airlie <airlied@redhat.com>

st/mesa: inline st_free_tokens

Reviewed-by: Dave Airlie <airlied@redhat.com>

st/mesa: cleanup st_geometry_program structure

It's full of unused variables and variables only used
in st_translate_geometry_program.

Reviewed-by: Dave Airlie <airlied@redhat.com>

mesa: add a missing GS support check in GetActiveUniformBlockiv

Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>

r600g: Implement GL_ARB_draw_indirect for EG/CM

Requires Evergreen/Cayman and radeon kernel module
2.41.0 or newer.

Expected piglit fails due to hardware limitations:
* arb_draw_indirect-draw-arrays-prim-restart
  Restarts not applied for DrawArrays commands
* arb_draw_indirect-vertexid
  Base vertex offset is not included in vertex id

Marek: bump vgt_state num_dw by 3 (= space needed for one register write)

Signed-off-by: Glenn Kennard <glenn.kennard@gmail.com>
Signed-off-by: Marek Olšák <marek.olsak@amd.com>

freedreno/a4xx: aniso filtering

Signed-off-by: Rob Clark <robclark@freedesktop.org>

freedreno: update generated headers

Signed-off-by: Rob Clark <robclark@freedesktop.org>

freedreno/a4xx: add ARB_instanced_arrays support

Signed-off-by: Rob Clark <robclark@freedesktop.org>

freedreno/a4xx: handle index_bias (i.e. base_vertex)

Signed-off-by: Rob Clark <robclark@freedesktop.org>

freedreno/a4xx: add support for vertexid and instanceid sysvals

ir3 bits of it already in place from a3xx patch..

Signed-off-by: Rob Clark <robclark@freedesktop.org>

freedreno/a4xx: pass number of instances to draw

a4xx has it's own draw packet, so needs equivalent update to what a3xx
already got.

Signed-off-by: Rob Clark <robclark@freedesktop.org>

docs: add news item and link release notes for mesa 10.4.5

Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>

docs: Add sha256 sums for the 10.4.5 release

Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>
(cherry picked from commit 41bdeda10210b8f1d358c04b25af2fbfe3335531)

Add release notes for the 10.4.5 release

Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>
(cherry picked from commit a5c608e951c7d41be99a1f84450a1d5aaf6ccadd)

st/omx/dec/h264: fix picture out-of-order with poc type 0 v2

poc counter should be reset with IDR frame,
otherwise there would be a re-order issue with
frames before and after IDR

v2: add commit message

Signed-off-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Cc: "10.4 10.5" <mesa-stable@lists.freedesktop.org>

install-lib-links: remove the .install-lib-links file

With earlier commit (install-lib-links: don't depend on .libs directory)
we moved the location of the file from .libs/ to the current dir.
Although we did not attribute that in the former case autotools was
doing us a favour and removing the file. Explicitly remove the file at
clean-local time, otherwise we'll end up with dangling files.

Cc: "10.3 10.4 10.5" <mesa-stable@lists.freedesktop.org>
Cc: Matt Turner <mattst88@gmail.com>
Cc: Lucas Stach <l.stach@pengutronix.de>
Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>

clover: Set appropriate flag defaults on memory object creation.

According to the spec when no device access mode is specified
clCreateBuffer and clCreateImage* should default to read/write, and
clCreateSubBuffer should default to the parent's device access flags.

clCreateSubBuffer is also required to inherit the host access and
host pointer flags from the parent.

Reviewed-and-tested-by: EdB <edb+mesa@sigluy.net>

clover: Add CL_MEM_HOST_* flag checks.

Those flags have been introduced in OpenCL 1.2.

[ Francisco Jerez: Rebase.  Throw CL_INVALID_VALUE from
  clCreateSubBuffer if the subbuffer drops access flags from its
  parent.  Use single function taking the set of allowed host access
  flags to validate memory transfer operands. ]

Reviewed-by: Francisco Jerez <currojerez@riseup.net>

clover: Factor out memory object flags validation to a helper function.

And define constants for commonly used subsets of flags to save some
typing.

Reviewed-and-tested-by: EdB <edb+mesa@sigluy.net>

vc4: Update to current kernel sources.

New BO create and mmap ioctls are added.  The submit ABI gains a flags
argument, and the pointers are fixed at 64-bit.  Shaders are now fixed at
the start of their BOs.

r600: Fix build after 984f3069370cd4a347cb38269d430b428385affd

Same as for the CLAMP macro, undef it before including a header file that
tries to make fields with that name.

st/nine: Mark end of non-void function unreachable

Signed-off-by: Tobias Klausmann <tobias.johannes.klausmann@mni.thm.de>
Reviewed-by: Eric Anholt <eric@anholt.net>

gallium: include util/macros.h

The most common macros are defined there, no use to duplicate these
Clean up the already redefinded macros

Signed-off-by: Tobias Klausmann <tobias.johannes.klausmann@mni.thm.de>
Reviewed-by: Eric Anholt <eric@anholt.net>

driconf: Update Catalan translation

Signed-off-by: Alex Henrie <alexhenrie24@gmail.com>

driconf: Update Spanish translation

Signed-off-by: Alex Henrie <alexhenrie24@gmail.com>

mesa: Add missing error checks to GetProgramInfoLog, GetShaderInfoLog and GetProgramiv

Fixes 3 dEQP tests:
* dEQP-GLES3.functional.negative_api.state.get_program_info_log
* dEQP-GLES3.functional.negative_api.state.get_shader_info_log
* dEQP-GLES3.functional.negative_api.state.get_programiv

Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>

i965: Fix non-AA wide line rendering with fractional line widths

"(...)Let w be the width rounded to the nearest integer (...). If the
line segment has endpoints given by (x0,y0) and (x1,y1) in window
coordinates, the segment with endpoints (x0,y0-(w-1)/2) and
(x1,y1-(w-1/2)) is rasterized, (...)"

The hardware it not rounding the line width, so we should do it.

Also, we should be careful not to go beyond the hardware limits
for the line width after it gets rounded. Gen6-7 define a maximum line
width slightly below 8.0, so we should advertise a maximum line
width lower than 7.5 to make sure that 7.0 is the maximum integer
line width that we can select. Since the line width granularity in these
platforms is 0.125, we choose 7.375. Other platforms advertise rounded
maximum line widths, so those are fine.

Fixes the following 3 dEQP tests:
dEQP-GLES3.functional.rasterization.primitives.lines_wide
dEQP-GLES3.functional.rasterization.fbo.texture_2d.primitives.lines_wide
dEQP-GLES3.functional.rasterization.fbo.rbo_singlesample.primitives.lines_wide

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

mesa: Fix ctx->Texture.CubeMapSeamless

The intel driver code, and apparently all other Mesa drivers, call
_mesa_initialize_context early in the CreateContext hook. That
function will end up calling _mesa_init_texture which will do:

ctx->Texture.CubeMapSeamless = _mesa_is_gles3(ctx);

But this won't work at this point, since _mesa_is_gles3 requires
ctx->Version to be set and that will not happen until late
in the CreateContext hook, when _mesa_compute_version is called.

We can't just move the call to _mesa_compute_version before
_mesa_initialize_context since it needs that available extensions
have been computed, which again requires other things to be
initialized, etc. Instead, we enable seamless cube maps since
GLES2, which should work for most implementations, and expect
drivers that don't support this to disable it manually as part
of their context initialization setup.

Fixes the following 192 dEQP tests:
dEQP-GLES3.functional.texture.filtering.cube.formats.*
dEQP-GLES3.functional.texture.filtering.cube.sizes.*
dEQP-GLES3.functional.texture.filtering.cube.combinations.*
dEQP-GLES3.functional.texture.mipmap.cube.*
dEQP-GLES3.functional.texture.vertex.cube.filtering.*
dEQP-GLES3.functional.texture.vertex.cube.wrap.*
dEQP-GLES3.functional.shaders.texture_functions.texturelod.samplercube_fixed_*

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>

mesa: Return error if BeginQuery is called with an existing object of different type

Section 2.14 Asynchronous Queries, page 84 of the OpenGL ES 3.0.4
spec states:

  "BeginQuery generates an INVALID_OPERATION error if any of the
   following conditions hold: [...] id is the name of an
   existing query object whose type does not match target; [...]

Similar wording exists in the OpenGL 4.5 spec, section 4.2. QUERY
OBJECTS AND ASYNCHRONOUS QUERIES, page 43.

Fixes 1 dEQP test:
* dEQP-GLES3.functional.negative_api.fragment.begin_query

Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>

mesa: Return INVALID_OPERATION when querying a never bound Query obj

Section 2.14 Asynchronous Queries, page 84 of the OpenGL ES 3.0.4 states:

"The command void GenQueries( sizei n, uint *ids ); returns n previously unused
query object names in ids. These names are marked as used, for the purposes of
GenQueries only, but no object is associated with them until the first time they
are used by BeginQuery."

This means that any attempt to use or query a Query object id before it has ever
been bound by calling glBeginQuery, should be assume to be an invalid object.

Fixes 1 dEQP test:
* dEQP-GLES3.functional.negative_api.state.get_query_objectuiv

Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>

mesa: Add _mesa_is_array_texture helper

Reviewed-by: Brian Paul <brianp@vmware.com>

mesa: Fix error validating args for TexSubImage3D

The zoffset and depth values were not being considered when calling
error_check_subtexture_dimensions().

Fixes 2 dEQP tests:
* dEQP-GLES3.functional.negative_api.texture.texsubimage3d_neg_offset
* dEQP-GLES3.functional.negative_api.texture.texsubimage3d_invalid_offset

Reviewed-by: Brian Paul <brianp@vmware.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Cc: "10.4 10.5" <mesa-stable@lists.freedestkop.org>

i965/blorp: round to nearest when converting float into integer

Fixes:

dEQP-GLES3.functional.fbo.blit.rect.out_of_bounds_nearest
dEQP-GLES3.functional.fbo.blit.rect.out_of_bounds_linear
dEQP-GLES3.functional.fbo.blit.rect.out_of_bounds_reverse_src_y_nearest
dEQP-GLES3.functional.fbo.blit.rect.out_of_bounds_reverse_src_y_linear
dEQP-GLES3.functional.fbo.blit.rect.out_of_bounds_reverse_dst_y_nearest
dEQP-GLES3.functional.fbo.blit.rect.out_of_bounds_reverse_dst_y_linear
dEQP-GLES3.functional.fbo.blit.rect.out_of_bounds_reverse_src_dst_x_nearest
dEQP-GLES3.functional.fbo.blit.rect.out_of_bounds_reverse_src_dst_x_linear
dEQP-GLES3.functional.fbo.blit.rect.out_of_bounds_reverse_src_dst_y_nearest
dEQP-GLES3.functional.fbo.blit.rect.out_of_bounds_reverse_src_dst_y_linear

No piglit regressions.

Signed-off-by: Samuel Iglesias Gonsalvez <siglesias@igalia.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>

i965: Perform program state upload outside of atom handling

Across the board of the various generations, the intial few atoms in
all of the atom lists are basically the same, (performing uploads for
the various programs). The only difference is that prior to gen6
there's an ff_gs upload in place of the later gs upload.

In this commit, instead of using the atom lists for this program state
upload, we add a new function brw_upload_programs that calls into the
per-stage upload functions which in turn check dirty bits and return
immediately if nothing needs to be done.

This commit is intended to have no functional change. The motivation
is that future code, (such as the shader cache), wants to have a
single function within which to perform various operations before and
after program upload, (with some local variables holding state across
the upload).

It may be worth looking at whether some of the other functionality
currently handled via atoms might also be more cleanly handled in a
similar fashion.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

egl, wayland: RGB565 format support on Back-buffer

In current code, color format is always hardcoded to
__DRI_IMAGE_FORMAT_ARGB8888 when buffer or DRI image is
allocated in function calls, get_back_bo and dri2_get_buffers,
regardless of current target's color format. This problem
may leads to incorrect render pitch calculation, which
eventually ends up with wrong offset of pixels in
the frame buffer when the image is in different color format
from dri surf's, especially with different bpp. (e.g. RGB565-16bpp)

Attached code patch simply adds RGB565 and XRGB8888 cases to two
functions noted above to resolve the issue.

v2: added a case of XRGB8888, format and bpp selection is done
    via switch-case (not "if-else" anymore)

Signed-off-by: Vivek Kasireddy <vivek.kasireddy@intel.com>
Signed-off-by: Dongwon Kim <dongwon.kim@intel.com>
Reviewed-by: Kristian Høgsberg <krh@bitplanet.net>
Cc: "10.5" <mesa-stable@lists.freedesktop.org>

mesa: move math-related function into new c99_math.h file

The alternative would be to include math.h in c99_compat.h but that
seems heavy-handed.

This patch also replaces INLINE with inline in the c99 math function
wrappers.

Fixes MSVC build.

Acked-by: Matt Turner <mattst88@gmail.com>

nir/gcm: Add some missing break statements

Reviewed-by: Connor Abbott <cwabbott0@gmail.com>

nir: Copy-propagate vecN operations that are actually moves

We were already do this for ALU operations but we haven't for non-ALU
operations.  This changes that.

total NIR instructions in shared programs: 2039883 -> 2022338 (-0.86%)
NIR instructions in affected programs:     1768850 -> 1751305 (-0.99%)
helped:                                    14244
HURT:                                      124

total FS instructions in shared programs: 4083960 -> 4084036 (0.00%)
FS instructions in affected programs:     7302 -> 7378 (1.04%)
helped:                                   12
HURT:                                     51

Signed-off-by: Jason Ekstrand <jason.ekstrand@intel.com>
Reviewed-by: Connor Abbott <cwabbott0@gmail.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

ra: Disable round-robin strategy for optimistically colorable nodes.

The round-robin allocation strategy is expected to decrease the amount
of false dependencies created by the register allocator and give the
post-RA scheduling pass more freedom to move instructions around.  On
the other hand it has the disadvantage of increasing fragmentation and
decreasing the number of equally-colored nearby nodes, what increases
the likelihood of failure in presence of optimistically colorable
nodes.

This patch disables the round-robin strategy for optimistically
colorable nodes.  These typically arise in situations of high register
pressure or for registers with large live intervals, in both cases the
task of the instruction scheduler shouldn't be constrained excessively
by the dense packing of those nodes, and a spill (or on Intel hardware
a fall-back to SIMD8 mode) is invariably worse than a slightly less
optimal scheduling.

Shader-db results on the i965 driver:

total instructions in shared programs: 5488539 -> 5488489 (-0.00%)
instructions in affected programs:     1121 -> 1071 (-4.46%)
helped:                                1
HURT:                                  0
GAINED:                                49
LOST:                                  5

v2: Re-enable round-robin already for the lowest one of the nodes
    pushed optimistically onto the sack (Connor).
v3: Use UINT_MAX instead of ~0, open-code MIN2 (Jason, Connor).

Reviewed-by: Connor Abbott <cwabbott0@gmail.com>

i965/fs: Fix lower_load_payload() not to use an incorrect half for immediates and uniforms.

Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>

i965/fs: Fix lower_load_payload() to take into account non-zero reg_offset.

Fixes metadata guess when instructions in the program specify a
destination register with non-zero reg_offset and when the payload of
a LOAD_PAYLOAD spans several registers.

Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>

i965/fs: Remove logic to keep track of MRF metadata in lower_load_payload().

MRFs cannot be read from anyway so they cannot possibly be a valid
source of LOAD_PAYLOAD.

Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>

i965/fs: Less broken handling of force_writemask_all in lower_load_payload().

It's perfectly fine to read the second half of a register written with
force_writemask_all from a first half MOV instruction or vice versa, and
lower_load_payload shouldn't mark the whole MOV as belonging to the second
half in that case.  Replicate the same metadata to both halves of the
destination when writemasking is disabled.

Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>

mesa/vbo: Use unreachable to silence uninitialized var warning.

Reviewed-by: Eric Anholt <eric@anholt.net>

mesa: Move START/END_FAST_MATH macros to their only use.

Reviewed-by: Eric Anholt <eric@anholt.net>

mesa: Remove definition of NULL.

If your stdlib.h doesn't define this you should fix your stdlib.h.

Reviewed-by: Eric Anholt <eric@anholt.net>

mesa: Use assert() instead of ASSERT wrapper.

Acked-by: Eric Anholt <eric@anholt.net>

mesa: Remove CHECK macro.

There's some commentary about how it's defined by other "modules", and
maybe that was true in 2000 when the code was added.

Reviewed-by: Eric Anholt <eric@anholt.net>

mesa: Remove dead CAPI define.

Reviewed-by: Eric Anholt <eric@anholt.net>

gallium: Use util_cpu_to_le{16,32} in many more places.

... and util_le{16,32}_to_cpu. I think I've used the right ones for
describing the actual operation performed (even though they're both just
"byte-swap this if I'm on big-endian").

The Linux Kernel has typedefs __le32/__be32 and friends that static
analysis tools can use to check that byte-orderings are correct. It
might be interesting to apply that here as well.

Reviewed-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Jose Fonseca <jfonseca@vmware.com>

gallium/util: Use HAVE___BUILTIN_* macros.

Reviewed-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Jose Fonseca <jfonseca@vmware.com>

mesa: Move C99 MSVC compatibility code from u_math.h to c99_compat.h.

Reviewed-by: Jose Fonseca <jfonseca@vmware.com>

i965: Link test programs with gtest before pthreads.

Cc: "10.5" <mesa-stable@lists.freedesktop.org>
Bugzilla: https://bugs.gentoo.org/show_bug.cgi?id=540962

osmesa: add gallium include dirs to Makefile.am

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=89260
Reviewed-by: Jose Fonseca <jfonseca@vmware.com>

util: move pipe_prim_names array into u_prim_name()

Also, wrapping the array in #ifdef DEBUG / #endif doesn't seem necessary.

Reviewed-by: Jose Fonseca <jfonseca@vmware.com>

util: rewrite debug_print_transfer_flags() using debug_dump_flags()

Add add missing PIPE_TRANSFER_PERSISTENT, PIPE_TRANSFER_COHERENT flags.

Reviewed-by: Jose Fonseca <jfonseca@vmware.com>

mesa: Adds missing error condition in _mesa_check_sample_count()

This corrects a trivial error introduced in commit
19252fee46b835cb4f6b1cce18d7737d62b64a2e. That patch was merged recently
and omits one condition (that 'samples' is greater than zero) in one of
the error checks. That error will definitely cause regressions.

Also corrects the reference to the specification above the error check,
which was wrongly quoting OpenGL instead of OpenGL-ES.

Reviewed-by: Martin Peres <martin.peres@linux.intel.com>

radeonsi: fix a warning caused by previous commit

Cc: 10.5 10.4 <mesa-stable@lists.freedesktop.org>

radeonsi: fix point sprites

Broken by a27b74819ad375e8c0bc88e13f42c951d2b5cd6a.

This fix is critical and should be ported to stable ASAP.

Cc: 10.5 10.4 <mesa-stable@lists.freedesktop.org>

i965/skl: Use 1 register for uniform pull constant payload

When under dispatch_width=16 the previous code would allocate 2 registers for
the payload when only one is needed. This manifested itself through bugs on SKL
which needs to mess with this instruction.

Ken though this might impact shader-db, but apparently it doesn't

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=89118
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=88999
Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Tested-by: Timo Aaltonen <timo.aaltonen@canonical.com>

nir: Generalize the optimization of subs of subs from 0.

I initially wrote this based on the "(('fneg', ('fneg', a)), a)" above,
but we can generalize it and make it more potentially useful.  In the
specific original case of a 0 for our new 'a' argument, it'll get further
algebraic optimization once the 0 is an argument to the new add.

No shader-db effects.

Reviewed-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Connor Abbott <cwabbott0@gmail.com>

nir: Collapse repeated bcsels on the same argument.

vc4 results:
total instructions in shared programs: 39881 -> 39794 (-0.22%)
instructions in affected programs:     6302 -> 6215 (-1.38%)

Reviewed-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Connor Abbott <cwabbott0@gmail.com>

nir: When faced with a csel on !condition, just flip the arguments.

total NIR instructions in shared programs: 39426 -> 39411 (-0.04%)
NIR instructions in affected programs:     3748 -> 3733 (-0.40%)

Reviewed-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Connor Abbott <cwabbott0@gmail.com>

nir: Allow nir_opt_algebraic to see booleanness through &&, ||, ^, !.

We have some useful optimizations to drop things like 'ine a, 0' on a
boolean argument, but if 'a' came from logical operations on bools, it
couldn't tell.  These kinds of constructs appear as a result of TGSI->NIR
quite frequently (at least with if flattening), so being a little more
aggressive in detecting booleans can pay off.

v2: Add ixor as a booleanness-preserving op (Suggestion by Connor).

vc4 results:
total instructions in shared programs: 40207 -> 39881 (-0.81%)
instructions in affected programs:     6677 -> 6351 (-4.88%)

Reviewed-by: Matt Turner <mattst88@gmail.com> (v1)
Reviewed-by: Connor Abbott <cwabbott0@gmail.com>

nir: Add a couple of simplifications of csel operations.

vc4 was already cleaning these up, but it does shave 4 NIR instructions in
shader-db.

Reviewed-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Connor Abbott <cwabbott0@gmail.com>

glsl: ensure that enter/leave record get a record type

May make life easier for tools like Coverity.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Matt Turner <mattst88@gmail.com>

tgsi: avoid returning pointer to local var, make it static

Spotted by Coverity.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>

freedreno/a4xx: set PC_PRIM_VTX_CNTL.VAROUT properly

Fixes xonotic, some webgl stuff, and really pretty much anything with
more than 4 varyings.

Signed-off-by: Rob Clark <robclark@freedesktop.org>

freedreno: update generated headers

Signed-off-by: Rob Clark <robclark@freedesktop.org>

freedreno/a4xx: bit of cleanup

Signed-off-by: Rob Clark <robclark@freedesktop.org>

loader: not having a pci-id should not be a warn

If there is no pci-id, which is valid for vc4 and freedreno, just emit
an info msg.  Keep malformed but existing pci-id's as a warning.

Mostly just to clean up a warning that confuses users for the non-pci
devices.

Signed-off-by: Rob Clark <robclark@freedesktop.org>

freedreno: implement fence

I never actually implemented the stubbed out fence stuff back in the
early days.  Fix that.

We'll need a few libdrm_freedreno changes to handle timeout properly,
so ignore that for now to avoid a libdrm_freedreno dependency bump.

Signed-off-by: Rob Clark <robclark@freedesktop.org>

freedreno/a2xx: fix increment in assert

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=88883
Signed-off-by: Rob Clark <robclark@freedesktop.org>

i965/fs: Use fs_reg for CS/VS atomics pixel mask immediate data

The brw_imm_ud will yield a HW_REG which then will introduce a barrier
for certain optimization opportunities.

No piglit regressions seen with gen8 (simd8vs).

Suggested-by: Matt Turner <mattst88@gmail.com>
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>

i965/fs: Set pixel/sample mask for compute shaders atomic ops

For fragment programs, we pull this mask from the payload header. The same
mask doesn't exist for compute shaders, so we set all bits to enabled.

Previously we were setting 0xff to support SIMD8 VS, but with CS we
support SIMD16, and therefore we change this to 0xffff.

Related commits for SIMD8 VS:

commit d9cd982d556be560af3bcbcdaf62b6b93eb934a5
Author: Ben Widawsky <benjamin.widawsky@intel.com>
Date:   Sun Feb 15 20:06:59 2015 -0800
    i965/simd8vs: Fix SIMD8 atomics

commit 4a95be9772a255776309f23180519a4a8560f2dd
Author: Jordan Justen <jordan.l.justen@intel.com>
Date:   Tue Feb 17 09:57:35 2015 -0800
    i965/simd8vs: Fix SIMD8 atomics (read-only)

Note: this mask is ANDed with the execution mask, so some channels may not end
up issuing the atomic operation.

Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Ben Widawsky <ben@bwidawsk.net>
Reviewed-by: Francisco Jerez <currojerez@riseup.net>

ilo: R32G32B32_FLOAT need no special care on Gen8+

Gen8+ must use VALIGN_4.  Unlike prior Gens, R32G32B32_FLOAT should supposedly
support VALIGN_4.

ilo: 128 BPP formats can use TiledY on Gen7.5+

The restriction is lifted.

nvc0: enable double support

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>