Marek Olšák [Sun, 17 Aug 2014 23:09:31 +0000 (01:09 +0200)]
radeonsi: simplify si_num_banks function
This makes it easier to use.
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
Marek Olšák [Sun, 17 Aug 2014 22:55:40 +0000 (00:55 +0200)]
radeonsi: use r600_draw_rectangle from r600g
Rectangles are easier than triangles for the rasterizer.
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
Marek Olšák [Sun, 17 Aug 2014 14:25:01 +0000 (16:25 +0200)]
radeonsi: save scissor state and sample mask for u_blitter
Cc: mesa-stable@lists.freedesktop.org
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
Marek Olšák [Sun, 17 Aug 2014 22:51:47 +0000 (00:51 +0200)]
radeonsi: don't set CB_SHADER_MASK=1 if there are no color outputs
This hack isn't needed anymore because of the previous u_blitter commit.
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
Marek Olšák [Sun, 17 Aug 2014 22:47:01 +0000 (00:47 +0200)]
gallium/u_blitter: don't use an empty fragment shader if there's a colorbuffer
This is custom code used by some drivers.
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Marek Olšák [Sat, 16 Aug 2014 23:46:31 +0000 (01:46 +0200)]
gallium/util: handle PIPE_BUFFER in util_pipe_tex_to_tgsi_tex
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Marek Olšák [Sat, 16 Aug 2014 23:36:57 +0000 (01:36 +0200)]
rbug: only add textures to the list
rbug-gui cannot display buffers, so it's pointless to add them.
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Marek Olšák [Sat, 16 Aug 2014 23:36:11 +0000 (01:36 +0200)]
rbug: fix a crash in sampler_view_destroy caused by incorrect context
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Marek Olšák [Sat, 16 Aug 2014 23:34:33 +0000 (01:34 +0200)]
rbug: send the actual number of layers to the client
This sends the correct value for array textures.
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Marek Olšák [Sat, 16 Aug 2014 23:33:46 +0000 (01:33 +0200)]
rbug: implement streamout context functions
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Marek Olšák [Sat, 16 Aug 2014 23:33:27 +0000 (01:33 +0200)]
rbug: fix crash in set_vertex_buffers
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Marek Olšák [Sat, 16 Aug 2014 23:32:43 +0000 (01:32 +0200)]
rbug: remove contexts from the list properly
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Emil Velikov [Tue, 19 Aug 2014 09:02:35 +0000 (10:02 +0100)]
ilo: fold drm_intel_get_aperture_sizes() within probe_winsys()
... and store the value in intel_winsys_info/ilo_dev_info.
Suggested-by: Chia-I Wu <olvaffe@gmail.com>
Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>
olv: check for errors and report raw values
Matt Turner [Tue, 15 Jul 2014 02:48:15 +0000 (19:48 -0700)]
i965/cfg: Add a foreach_block_and_inst_safe macro.
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Matt Turner [Fri, 11 Jul 2014 00:30:40 +0000 (17:30 -0700)]
i965/cfg: Add a foreach_inst_in_block_safe macro.
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Matt Turner [Mon, 14 Jul 2014 18:15:51 +0000 (11:15 -0700)]
i965/cfg: Add a foreach_block_safe macro.
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Matt Turner [Sat, 12 Jul 2014 04:16:13 +0000 (21:16 -0700)]
i965: Pass a cfg pointer to generate_{code,assembly}.
The loop over all instructions is now two-fold, over all of the blocks
and all of the instructions in each block.
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Matt Turner [Sat, 12 Jul 2014 05:31:39 +0000 (22:31 -0700)]
i965: Add and use foreach_block macro.
Use this as an opportunity to rename 'block_num' to 'num'. block->num is
clear, and block->block_num has always been redundant.
Matt Turner [Fri, 11 Jul 2014 23:17:47 +0000 (16:17 -0700)]
i965/cfg: Embed link in bblock_t for main block list.
The next patch adds a foreach_block (block, cfg) macro, which works
better if it provides a direct bblock_t pointer, rather than a
bblock_link pointer that you have to use to find the actual block.
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Matt Turner [Sun, 10 Aug 2014 17:28:34 +0000 (10:28 -0700)]
i965/fs: Optimize gl_FrontFacing calculation on Gen4/5.
Doesn't use fewer instructions, but it does avoid writing the flag
register and if we want to switch the representation of true for Gen4/5
in the future, we can just delete the AND instruction.
Matt Turner [Sun, 10 Aug 2014 16:04:49 +0000 (09:04 -0700)]
i965/fs: Optimize gl_FrontFacing calculation on Gen6+.
total instructions in shared programs:
4288650 ->
4282838 (-0.14%)
instructions in affected programs: 595018 -> 589206 (-0.98%)
Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com>
Matt Turner [Sat, 9 Aug 2014 04:00:31 +0000 (21:00 -0700)]
i965: Use ~0 to represent true on Gen >= 6.
total instructions in shared programs:
4292303 ->
4288650 (-0.09%)
instructions in affected programs: 299670 -> 296017 (-1.22%)
Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com>
Matt Turner [Sat, 9 Aug 2014 04:04:26 +0000 (21:04 -0700)]
i965/fs: Optimize emit_bool_to_cond_code for logical exprs.
AND, OR, and XOR can generate the conditional code directly.
total instructions in shared programs:
4293335 ->
4292303 (-0.02%)
instructions in affected programs: 121408 -> 120376 (-0.85%)
Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com>
Matt Turner [Sat, 9 Aug 2014 02:44:22 +0000 (19:44 -0700)]
i965: Use UniformBooleanTrue value for boolean literal true.
Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com>
Matt Turner [Sat, 9 Aug 2014 02:46:05 +0000 (19:46 -0700)]
glsl: Use UniformBooleanTrue value for uniform initializers.
Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com>
Matt Turner [Fri, 8 Aug 2014 18:58:16 +0000 (11:58 -0700)]
mesa: Upload boolean uniforms using UniformBooleanTrue.
Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com>
Matt Turner [Sat, 9 Aug 2014 04:19:42 +0000 (21:19 -0700)]
i965: Remove dead call to _mesa_associate_uniform_storage().
Dead since the call to _mesa_generate_parameters_list_for_uniforms
was removed in commit
12751ef2. So this was why all of that code that
was supposed to fix up the value of a uniform bool to wasn't happening.
Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com>
Matt Turner [Fri, 15 Aug 2014 17:08:14 +0000 (10:08 -0700)]
mapi: Inline shared-glapi/tests/Makefile.
Reviewed-by: Kristian Høgsberg <krh@bitplanet.net>
Matt Turner [Fri, 15 Aug 2014 17:01:10 +0000 (10:01 -0700)]
mapi: Inline glapi/tests/Makefile.
Reviewed-by: Kristian Høgsberg <krh@bitplanet.net>
Matt Turner [Thu, 14 Aug 2014 20:58:04 +0000 (13:58 -0700)]
mapi: Inline glapi/Makefile.
Reviewed-by: Kristian Høgsberg <krh@bitplanet.net>
Matt Turner [Thu, 14 Aug 2014 20:47:16 +0000 (13:47 -0700)]
mapi: Inline es2api/Makefile.
Reviewed-by: Kristian Høgsberg <krh@bitplanet.net>
Matt Turner [Thu, 14 Aug 2014 19:30:22 +0000 (12:30 -0700)]
mapi: Inline es1api/Makefile.
Reviewed-by: Kristian Høgsberg <krh@bitplanet.net>
Matt Turner [Thu, 14 Aug 2014 19:20:12 +0000 (12:20 -0700)]
mapi: Inline shared-glapi/Makefile.
Matt Turner [Thu, 14 Aug 2014 23:07:26 +0000 (16:07 -0700)]
build: Let install-lib-links.mk handle .la files in subdirectories.
The next patches are going to combine some of the mapi subdirectories'
Makefiles into a single Makefile, giving better build parallelism.
lib_LTLIBRARIES will be set to something like
lib_LTLIBRARIES = shared-glapi/libglapi.la es2api/libGLESv2.la
and the current code in install-lib-links.mk simply prepends .libs/ and
replaces the .la in order to create the filenames that it needs to ln/cp
into the LIBDIR. This doesn't work when the .la file is actually in a
subdirectory.
This patch fixes this and puts .libs/ in the right place.
Reviewed-by: Kristian Høgsberg <krh@bitplanet.net>
Reviewed-by: Emil Velikov <emil.l.velikov@gmail.com>
Matt Turner [Sun, 17 Aug 2014 07:45:27 +0000 (00:45 -0700)]
i965: Enable instruction compaction on Gen8+.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Matt Turner [Sun, 15 Jun 2014 18:29:22 +0000 (11:29 -0700)]
i965: Add support for compacting 3-src instructions on Gen8.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Matt Turner [Wed, 18 Jun 2014 22:43:23 +0000 (15:43 -0700)]
i965: Add support for compacting 1- and 2-src instructions on Gen8.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Matt Turner [Sat, 19 Apr 2014 20:38:59 +0000 (13:38 -0700)]
i965/gen8: Add 3-src instruction compaction tables.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Matt Turner [Sat, 19 Apr 2014 20:20:55 +0000 (13:20 -0700)]
i965/gen8: Add instruction compaction tables.
Acked-by: Kenneth Graunke <kenneth@whitecape.org>
Matt Turner [Tue, 17 Jun 2014 19:14:44 +0000 (12:14 -0700)]
i965: Update JIP/UIP compaction code to operate on bytes.
JIP/UIP were previously in units of compacted instructions. On Gen8
they're in units of bytes.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Matt Turner [Sat, 14 Jun 2014 02:38:51 +0000 (19:38 -0700)]
i965: Reverse condition ordering to let us support other gens.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Matt Turner [Tue, 19 Aug 2014 01:18:30 +0000 (18:18 -0700)]
i965/disasm: Add CSEL.
Timothy Arceri [Thu, 14 Aug 2014 21:43:13 +0000 (07:43 +1000)]
mesa: fix copy and paste errors in glBindVertexBuffers
Signed-off-by: Timothy Arceri <t_arceri@yahoo.com.au>
Reviewed-by: Fredrik Höglund <fredrik@kde.org>
Tobias Klausmann [Fri, 25 Jul 2014 15:34:18 +0000 (17:34 +0200)]
nv50/ir: (trivial) initialize pointer to silence warning
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
Signed-off-by: Tobias Klausmann <tobias.johannes.klausmann@mni.thm.de>
Eric Anholt [Mon, 18 Aug 2014 18:07:31 +0000 (11:07 -0700)]
vc4: Add support for swizzling of texture colors.
Fixes swapped colors on the copypix demo and some piglit tests like
pbo-teximage-tiling .
Eric Anholt [Mon, 18 Aug 2014 18:23:04 +0000 (11:23 -0700)]
vc4: Fix handling of non-XYZW swizzles in color outputs.
The SWIZZLE_1 of the winsys destination was dereffing off the end of the
array, which surprisingly often worked out (since nobody reads the
rendered value anyway, so whatever junk was referenced in the QIR didn't
matter), but shader dumping would sometimes segfault.
Eric Anholt [Mon, 18 Aug 2014 18:18:10 +0000 (11:18 -0700)]
vc4: Extract the swizzle handling from vertex fetch.
I want to reuse this elsewhere, and NONE debug output hasn't been useful
so I don't miss it being as detailed as it was before.
Eric Anholt [Mon, 18 Aug 2014 18:46:58 +0000 (11:46 -0700)]
vc4: Add support for color masking.
This gets fbo-colormask-formats working for core formats, which increases
my confidence in some of the swizzle and blend handling.
Eric Anholt [Mon, 18 Aug 2014 17:53:35 +0000 (10:53 -0700)]
vc4: Add a helper for QOP_R4_UNPACK_[ABCD].
Eric Anholt [Mon, 18 Aug 2014 17:24:29 +0000 (10:24 -0700)]
vc4: Don't forget to set up the offset for render targets.
This almost fixes fbo-generatemipmap rendering, except that the 1x1 level
isn't getting rendered.
Eric Anholt [Mon, 18 Aug 2014 17:31:36 +0000 (10:31 -0700)]
vc4: Fix multi-level texture setup.
We weren't accounting for the level 0 offset in the texture setup (so it
only worked if it happened to be a single-level texture), and doing so
required that we get the level 0 offset page aligned so that the offset
bits don't get interpreted as the texture format and such.
Eric Anholt [Mon, 18 Aug 2014 19:46:24 +0000 (12:46 -0700)]
vc4: Fix viewport handling in the uniforms upload.
I had the right viewports in vc4_emit.c, but grabbed the wrong values in
the uniform setup, so primitives would claim to be in the wrong parts of
the screen. (The vc4_emit.c state looks like it just decides how big the
clipping guardband is).
This gets fbo-viewport closer to working (which still has the problem that
the HW is always guard-band clipping), and fixes inverted FBO rendering in
general.
Marek Olšák [Mon, 18 Aug 2014 22:26:01 +0000 (00:26 +0200)]
docs/relnotes: document GLX_MESA_query_renderer
Francisco Jerez [Sat, 16 Aug 2014 13:25:34 +0000 (16:25 +0300)]
clover: Refuse to build a program if there are kernel objects attached to it.
Fixes piglit cl-api-build-program.
Tested-by: EdB <edb+mesa@sigluy.net>
Francisco Jerez [Sun, 17 Aug 2014 20:26:49 +0000 (23:26 +0300)]
clover/util: Pass initial count value to ref_counter constructor.
And mark the ref_count() method as const.
Tested-by: EdB <edb+mesa@sigluy.net>
Francisco Jerez [Sun, 17 Aug 2014 20:18:45 +0000 (23:18 +0300)]
clover/util: Implement minimalist reference to clover::ref_counter object.
Tested-by: EdB <edb+mesa@sigluy.net>
EdB [Tue, 5 Aug 2014 17:09:38 +0000 (19:09 +0200)]
clover: clGetProgramInfo support for OpenCL 1.2.
[ Francisco Jerez: Rework using fold() for conciseness. ]
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
Tested-by: EdB <edb+mesa@sigluy.net>
Ilia Mirkin [Sat, 16 Aug 2014 06:46:01 +0000 (02:46 -0400)]
nouveau: don't keep stale pointer to free'd data
If ->sys is non-null, we might decide that it's where the data is
stored.
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Cc: <mesa-stable@lists.freedesktop.org>
Ilia Mirkin [Mon, 11 Aug 2014 00:10:24 +0000 (20:10 -0400)]
egl: don't exit process on initialization failure
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Kristian Høgsberg <krh@bitplanet.net>
Brian Paul [Fri, 15 Aug 2014 22:55:40 +0000 (16:55 -0600)]
mesa: fix compressed_subtexture_error_check() return value
The function should return GLboolean, not GLenum.
If we detect invalid compressed pixel storage parameters, we should
return GL_TRUE, not GL_FALSE so that the function is no-op'd.
An update to the piglit s3tc-errors test will check this.
Reviewed-by: Matt Turner <mattst88@gmail.com>
Brian Paul [Fri, 15 Aug 2014 22:28:59 +0000 (16:28 -0600)]
mesa: move _mesa_compressed_texture_pixel_storage_error_check()
to pixelstore.c, add const qualifier to the 'packing' parameter.
Add comments.
Reviewed-by: Matt Turner <mattst88@gmail.com>
Brian Paul [Fri, 15 Aug 2014 21:21:01 +0000 (15:21 -0600)]
mesa: minor improvements to _mesa_compute_compressed_pixelstore()
Replace the gl_texture_image parameter with mesa_format since we only
used the image's format.
Add some comments.
Reviewed-by: Matt Turner <mattst88@gmail.com>
Brian Paul [Fri, 15 Aug 2014 22:21:15 +0000 (16:21 -0600)]
util: whitespace and formatting fixes in u_math.h
Trivial.
Ilia Mirkin [Sat, 16 Aug 2014 05:00:39 +0000 (01:00 -0400)]
nouveau: make sure to invalidate any vbo state as well
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Cc: <mesa-stable@lists.freedesktop.org>
Jordan Justen [Wed, 28 May 2014 17:44:13 +0000 (10:44 -0700)]
i965/gen6: Force ALL_SLICES_AT_EACH_LOD for separate stencil/hiz
For gen6 we will use the ALL_SLICES_AT_EACH_LOD miptree layout for
separate stencil/hiz. This is needed because gen6 hiz and separate
stencil only support a single miplevel. When accessing the other LODs,
we will program a tile aligned offset for the bo.
PRM Volume 1, Part 1, 7.18.3.7.2 For separate stencil buffer [DevILK]
to [DevSNB]:
"The separate stencil buffer does not support mip mapping, thus the
storage for LODs other than LOD 0 is not needed."
We still allocate storage for the other stencil mip-levels within a
single texture, but each mip-level will use non-mip-array spacing.
PRM Volume 2, Part 1, 7.5.3 Hierarchical Depth Buffer
"[DevSNB]: The hierarchical depth buffer does not support the LOD
field, it is assumed by hardware to be zero. A separate
hierarachical depth buffer is required for each LOD used, and the
corresponding buffer’s state delivered to hardware each time a new
depth buffer state with modified LOD is delivered."
We allocate storage for the other hiz mip-levels within a single
texture, but each mip-level will use non-mip-array spacing.
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Acked-by: Kenneth Graunke <kenneth@whitecape.org>
Jordan Justen [Wed, 28 May 2014 17:19:37 +0000 (10:19 -0700)]
i965/gen6: Stencil/hiz needs an offset for LOD > 0
Since gen6 separate stencil & hiz only supports LOD0, we need to
program an offset to the LOD when emitting the separate stencil/hiz.
v3:
* Use new array_layout enum
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Acked-by: Kenneth Graunke <kenneth@whitecape.org>
Jordan Justen [Wed, 28 May 2014 17:36:44 +0000 (10:36 -0700)]
i965/gen6: Force tile alignment for each stencil/hiz LOD
Gen6 doesn't support multiple miplevels for hiz and stencil.
Therefore, we must point to the LOD directly during rendering.
But, we also have removed the tile offsets from normal depth surfaces,
so we need to align each LOD to a tile boundary for hiz and stencil.
v3:
* Use new array_layout enum
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Acked-by: Kenneth Graunke <kenneth@whitecape.org>
Jordan Justen [Wed, 28 May 2014 16:30:39 +0000 (09:30 -0700)]
i965: Support array_layout == ALL_SLICES_AT_EACH_LOD for multiple LODs
Previously array_layout ALL_SLICES_AT_EACH_LOD was only used for array
spacing lod0 on gen7+ and therefore was only used with a single mip
level.
gen6 separate stencil & hiz only support LOD0, so we need to allocate
the miptree similar to gen7+ array spacing lod0, except we also need
space for multiple mip levels. (Since OpenGL stencil and depth support
multiple LODs.)
The miptree is allocated with tightly packed array slice spacing, but
we still also pack the miplevels into the region similar to a normal
multi mip level packing.
A 2D Array texture with 2 slices and multiple LODs would look somewhat
like this:
+----------+
| |
| |
+----------+
| |
| |
+----------+
+---+ +-+
| | +-+
+---+ +-+
| | :
+---+
v3:
* Use new array_layout enum
* ASCII art!
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Acked-by: Kenneth Graunke <kenneth@whitecape.org>
Jordan Justen [Wed, 28 May 2014 16:05:37 +0000 (09:05 -0700)]
i965: Allow forcing miptree->array_layout = ALL_SLICES_AT_EACH_LOD
gen6 does not support multiple miplevels with separate
stencil/hiz. Therefore we need to layout its miptree with no mipmap
spacing between the slices of each miplevel.
v3:
* Use new array_layout enum
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Acked-by: Kenneth Graunke <kenneth@whitecape.org>
Jordan Justen [Fri, 13 Jun 2014 22:46:32 +0000 (15:46 -0700)]
i965: Change mipmap array_spacing_lod0 to array_layout (enum)
We will want to setup gen6 separate stencil and hiz miptrees in a
layout that is similar to array_spacing_lod0. This is needed because
gen6 hiz and stencil only support a single mip-level.
In both use cases (gen7+ LOD0 spacing & gen6 separate stencil/hiz),
the array slices will be packed at each LOD without reserving extra
space for LODs within each array slice.
So, we generalize the name of this field and add comments to indicate
the old and new uses.
Motivation for the gen6 change comes from the PRM:
PRM Volume 1, Part 1, 7.18.3.7.2 For separate stencil buffer [DevILK]
to [DevSNB]:
"The separate stencil buffer does not support mip mapping, thus the
storage for LODs other than LOD 0 is not needed."
PRM Volume 2, Part 1, 7.5.3 Hierarchical Depth Buffer
"[DevSNB]: The hierarchical depth buffer does not support the LOD
field, it is assumed by hardware to be zero. A separate
hierarachical depth buffer is required for each LOD used, and the
corresponding buffer’s state delivered to hardware each time a new
depth buffer state with modified LOD is delivered."
v2:
* Rename array_spacing_lod0 to non_mip_arrays
v3:
* Instead, replace array_spacing_lod0 with array_layout enum
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Acked-by: Kenneth Graunke <kenneth@whitecape.org>
Jordan Justen [Tue, 9 Jul 2013 22:36:32 +0000 (15:36 -0700)]
i965/gen6 depth surface: program 3DSTATE_DEPTH_BUFFER to top of surface
(
bf25ee2 for gen6)
Previously we would always find the 2D sub-surface of interest,
and then program the surface to this location. Now we always
program the 3DSTATE_DEPTH_BUFFER at the start of the surface.
To select the lod/slice, we utilize the lod & minimum array
element fields.
We also must disable brw_workaround_depthstencil_alignment for
gen >= 6. Now the hardware will handle alignment when rendering
to additional slices/LODs.
v3:
* Set depth_mt bo RELOC offset to 0, as was done in
bf25ee2
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=56127
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Acked-by: Kenneth Graunke <kenneth@whitecape.org>
Jordan Justen [Fri, 19 Jul 2013 22:44:56 +0000 (15:44 -0700)]
i965/gen6 fbo: make unmatched depth/stencil configs return unsupported
(
f3c886b for gen6)
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Jordan Justen [Tue, 9 Jul 2013 22:32:42 +0000 (15:32 -0700)]
i965/gen6 blorp depth: calculate base surface width/height
(
e3a49e1 for gen6)
This will be used in 3DSTATE_DEPTH_BUFFER in a later patch.
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Jordan Justen [Tue, 9 Jul 2013 22:24:56 +0000 (15:24 -0700)]
i965/gen6 depth surface: calculate minimum array element being rendered
(
a23cfb8 for gen6)
In layered rendering this will be 0. Otherwise it will be the
selected slice.
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Jordan Justen [Tue, 9 Jul 2013 22:19:55 +0000 (15:19 -0700)]
i965/gen6 depth surface: calculate LOD being rendered to
(
08ef1dd for gen6)
This will be used in 3DSTATE_DEPTH_BUFFER in a later patch.
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Jordan Justen [Tue, 9 Jul 2013 22:16:35 +0000 (15:16 -0700)]
i965/gen6 depth surface: calculate depth (array size) for depth surface
(
bc1acaa for gen6)
This will be used in 3DSTATE_DEPTH_BUFFER in a later patch.
Note: Cube maps are treated as 2D arrays with 6 times as
many array elements as the cube map array would have.
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Jordan Justen [Tue, 9 Jul 2013 21:56:38 +0000 (14:56 -0700)]
i965/gen6 depth surface: calculate more specific surface type
(
171e633 for gen6)
This will be used in 3DSTATE_DEPTH_BUFFER in a later patch.
Note: Cube maps are treated as 2D arrays with 6 times as
many array elements as the cube map array would have.
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Jordan Justen [Wed, 30 Jul 2014 18:20:48 +0000 (11:20 -0700)]
i965/gen6_depth_state.c: Remove (gen != 6) code paths
Since this code was branched from brw_misc_state.c, it had support for
gen != 6. We can now remove this.
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Jordan Justen [Wed, 28 May 2014 23:02:12 +0000 (16:02 -0700)]
i965: Split gen6 depth hiz state out from brw
We will program the gen6 hiz depth state differently to enable layered
rendering on gen6.
v2:
* Remove unneeded gen6_emit_depthbuffer as suggested by Topi
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Jordan Justen [Tue, 25 Feb 2014 19:18:25 +0000 (11:18 -0800)]
i965/gen6: Adjust render height in errata case for MSAA
In the gen6 PRM Volume 1 Part 1: Graphics Core, Section
7.18.3.7.1 (Surface Arrays For all surfaces other than separate
stencil buffer):
"[DevSNB] Errata: Sampler MSAA Qpitch will be 4 greater than the
value calculated in the equation above , for every other odd Surface
Height starting from 1 i.e. 1,5,9,13"
Since this Qpitch errata only impacts the sampler, we have to adjust
the input for the rendering surface to achieve the same qpitch. For
the affected heights, we increment the height by 1 for the rendering
surface.
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Acked-by: Chris Forbes <chrisf@ijw.co.nz>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Jordan Justen [Fri, 19 Apr 2013 08:39:51 +0000 (01:39 -0700)]
i965/gen6: Add support for layered renderbuffers
Rather than pointing the surface_state directly at a single
sub-image of the texture for rendering, we now point the
surface_state at the top level of the texture, and configure
the surface_state as needed based on this.
v2:
* Use SET_FIELD as suggested by Topi
* Simplify min_array_element assignment as suggested by Topi
v3:
* Use irb->layer_count for depth instead of rb->Depth
* Make gl_target const
* depth - 1, not depth
v4:
* Merge in
dd43900b &
b875f39e fixes to prevent 3D texture piglit
regressions
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Jordan Justen [Wed, 30 Jul 2014 18:20:48 +0000 (11:20 -0700)]
i965/gen6_surface_state.c: Remove (gen < 6) code path
Since this code was branched from brw_wm_surface_state.c, it had
support for gen < 6. We can now remove this.
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Jordan Justen [Wed, 28 May 2014 21:18:05 +0000 (14:18 -0700)]
i965: Split gen6 renderbuffer surface state from gen5 and older
We will program the gen6 renderbuffer surface state differently to
enable layered rendering on gen6.
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Kenneth Graunke [Wed, 13 Aug 2014 23:03:01 +0000 (16:03 -0700)]
meta: Use instanced rendering for layered clears.
Layered rendering is part of OpenGL 3.2; GL_ARB_draw_instanced is part
of OpenGL 3.1. As such, all drivers supporting layered rendering
already support gl_InstanceID.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Kristian Høgsberg <krh@bitplanet.net>
Kenneth Graunke [Wed, 13 Aug 2014 23:02:17 +0000 (16:02 -0700)]
mesa: Expose vbo_exec_DrawArraysInstanced as _mesa_DrawArraysInstanced.
So we can use it in meta.c.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Kristian Høgsberg <krh@bitplanet.net>
Dave Airlie [Fri, 15 Aug 2014 23:14:17 +0000 (09:14 +1000)]
Revert "hud: don't overrun malloced arrays"
This reverts commit
1cfcd0164e1be7d7b05b693f60a262ad735b7565.
This seems to cause r600g lockups,
https://bugs.freedesktop.org/show_bug.cgi?id=82628
Signed-off-by: Dave Airlie <airlied@redhat.com>
Kristian Høgsberg [Fri, 15 Aug 2014 22:59:59 +0000 (15:59 -0700)]
i965: Guard access to gl_Layer by extension #ifdef
Only assign gl_Layer if we have GL_AMD_vertex_shader_layer. Gen6 doesn't
(currently) have that extension, but it also doesn't support layered
rendering.
Signed-off-by: Kristian Høgsberg <krh@bitplanet.net>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Tested-by: Jordan Justen <jordan.l.justen@intel.com>
Emil Velikov [Fri, 15 Aug 2014 19:07:09 +0000 (20:07 +0100)]
gallium/vc4: PIPE_CAP_VIDEO_MEMORY return the amount of system ram
Suggested-by: Eric Anholt <eric@anholt.net>
Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
Eric Anholt [Thu, 14 Aug 2014 20:27:11 +0000 (13:27 -0700)]
vc4: Add support for blending.
Passes blendminmax and blendsquare. glean's more serious blendFunc fails
in simulation due to binner memory overflow (I really need to work around
that), and fbo-blending-formats fails due to Mesa refusing one of the
getter requests, even before it could fail due to the driver not actually
supporting different formats yet.
Eric Anholt [Wed, 13 Aug 2014 17:43:26 +0000 (10:43 -0700)]
vc4: Drop incorrect attempt to incorrectly invert the primconvert hw_mask.
The hw_mask is the set of primitives you actually support, so this attempt
to provide the set of formats that's unsupported was wrong in two ways (it
was intended to be '~' not '!'). However, we only call this code when
prim isn't one of the actually supported hw_mask bits, so missing out on
the memcpy didn't matter anyway.
Eric Anholt [Wed, 13 Aug 2014 21:46:06 +0000 (14:46 -0700)]
vc4: Use cl_f() instead of cl_u32(fui())
Eric Anholt [Wed, 13 Aug 2014 21:44:57 +0000 (14:44 -0700)]
vc4: Consistently use qir_uniform_f().
Eric Anholt [Tue, 12 Aug 2014 22:50:53 +0000 (15:50 -0700)]
vc4: Consume the implicit varyings for points and lines.
We were triggering simulator assertion failures for not consuming these,
and presumably we want to actually make use of them some day (for things
like point/line antialiasing)
Note that this has the qreg index as 0, which is the same index as the
first GL varyings read. This doesn't matter currently, since that number
isn't used for anything except dumping.
Eric Anholt [Tue, 12 Aug 2014 23:35:33 +0000 (16:35 -0700)]
vc4: Move the deref of the color buffer for simulator into the simulator.
At some point I'm going to want to move the information necessary for the
host buffer upload/download into the BO so that it's independent of the
current vc4->framebuffer, but for now this fixes pointless derefs on
non-simulator in vc4_context.c since the dump_fbo() removal
Kristian Høgsberg [Mon, 7 Jul 2014 23:44:58 +0000 (16:44 -0700)]
i965: Implement fast color clears using meta operations
This patch uses the infrastructure put in place by previous patches
to implement fast color clears and replicated color clears in terms of
meta operations.
This works all the way back to gen7 where fast clear was introduced and
adds support for fast clear on gen8. It replaces the blorp path
completely and improves on a few cases. Layered clears are now done
using instanced rendering and multiple render-target clears use a
MRT shader with rep16 writes.
Signed-off-by: Kristian Høgsberg <krh@bitplanet.net>
Acked-by: Kenneth Graunke <kenneth@whitecape.org>
Kristian Høgsberg [Mon, 7 Jul 2014 22:27:17 +0000 (15:27 -0700)]
i965: Add optimization pass to let us use the replicate data message
The data port has a SIMD16 'replicate data' message, which lets us write
the same color for all 16 pixels by sending the four floats in the
lower half of a register instead of sending 4 times 16 identical
component values in 8 registers.
The message comes with a lot of restrictions and could be made generally
useful by recognizing when those restriction are satisfied. For now,
this lets us enable the optimization when we know it's safe, but we don't
enable it by default. The optimization works for simple color clear shaders
only, but does recognized and support multiple render targets.
Signed-off-by: Kristian Høgsberg <krh@bitplanet.net>
Acked-by: Kenneth Graunke <kenneth@whitecape.org>
Kristian Høgsberg [Sun, 10 Aug 2014 23:00:31 +0000 (16:00 -0700)]
meta: Export _mesa_meta_drawbuffers_from_bitfield()
We'll use this in the i965 fast clear implementation.
Signed-off-by: Kristian Høgsberg <krh@bitplanet.net>
Reviewed-by: Connor Abbott <cwabbott0@gmail.com>
Kristian Høgsberg [Fri, 8 Aug 2014 23:53:53 +0000 (16:53 -0700)]
mesa: Use _mesa_lock_context_textures in _mesa_GetTexParameterfv()
GetTexParamterfv() doesnt change texture state, so instead of
_mesa_lock_texture() we can use _mesa_lock_context_textures(),
which doesn't increase the texture stamp. With this change,
_mesa_update_state_locked() is now only called from under
_mesa_lock_context_textures(), which is right thing to do. Right now
it's the same mutex, but if we made texture locking more fine grained
locking one day, just locking one texture here would be wrong.
This all ignores the fact that texture locking seem a bit
flaky and broken, but we're trying to not blatantly make it worse.
This change allows us to reliably unlock the context textures in the
dd::UpdateState callback as is necessary for meta color resolves.
Signed-off-by: Kristian Høgsberg <krh@bitplanet.net>
Acked-by: Kenneth Graunke <kenneth@whitecape.org>
Kristian Høgsberg [Fri, 8 Aug 2014 23:24:00 +0000 (16:24 -0700)]
i965: Move pre-draw resolve buffers to dd::UpdateState
No functional change except for glBegin/glEnd style rendering, where we now
do the resolves at glBegin time instead of FLUSH_VERTICES time. This is also
the reason for this change, so that when we later switch fast clear resolve to
use meta, we won't be doing meta operations in the middle of a begin/end
sequence.
Signed-off-by: Kristian Høgsberg <krh@bitplanet.net>
Acked-by: Kenneth Graunke <kenneth@whitecape.org>
Kristian Høgsberg [Mon, 7 Jul 2014 23:27:31 +0000 (16:27 -0700)]
i965: Provide a context flag to let us enable fast clear
GEN7+ has the fast clear functionality, which lets us clear the color
buffers using the MCS and a scaled down rectangle. To enable this
we have to set the appropriate bits in the 3DSTATE_PS package.
Signed-off-by: Kristian Høgsberg <krh@bitplanet.net>
Acked-by: Kenneth Graunke <kenneth@whitecape.org>