Paul Mackerras [Sat, 13 Jun 2020 13:00:13 +0000 (23:00 +1000)]
dcache: Reduce back-to-back store latency from 3 cycles to 2
This uses the machinery we already had for comparing the real address
of a new request with the tag of a previous request (r1.reload_tag)
to get better timing on comparing the address of a second store with
the one in progress. The comparison is now on the set size rather
than the page size, but since set size can't be larger than the page
size (and usually will equal the page size), that is OK.
The same comparison can also be used to tell when we can satisfy
a load miss during a cache line refill.
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
Paul Mackerras [Sat, 13 Jun 2020 10:27:50 +0000 (20:27 +1000)]
mmu: Take an extra cycle to do TLB invalidations
This makes the TLB invalidations that occur as a result of a tlbie,
slbia or mtspr instruction take one more cycle. This breaks some
long combinatorial chains from decode2 to dcache and icache and
thus eases timing.
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
Paul Mackerras [Thu, 11 Jun 2020 04:23:50 +0000 (14:23 +1000)]
dcache: Reduce latencies and improve timing
This implements various improvements to the dcache with the aim of
making it go faster.
- We can now execute operations that don't need to access main memory
(cacheable loads that hit in the cache and TLB operations) as soon
as any previous operation has completed, without waiting for the
state machine to become idle.
- Cache line refills start with the doubleword that is needed to
satisfy the load that initiated them.
- Cacheable loads that miss return their data and complete as soon as
the requested doubleword comes back from memory; they don't wait for
the refill to finish.
- We now have per-doubleword valid bits for the cache line being
refilled, meaning that if a load comes in for a line that is in the
process of being refilled, we can return the data and complete it
within a couple of cycles of the doubleword coming in from memory.
- There is now a bypass path for data being written to the cache RAM
so that we can do a store hit followed immediately by a load hit to
the same doubleword. This also makes the data from a refill
available to load hits one cycle earlier than it would be otherwise.
- Stores complete in the cycle where their wishbone operation is
initiated, without waiting for the wishbone cycle to complete.
- During the wishbone cycle for a store, if another store comes in
that is to the same page, and we don't have a stall from the
wishbone, we can send out the write for the second store in the same
wishbone cycle and without going through the IDLE state first. We
limit it to 7 outstanding writes that have not yet been
acknowledged.
- The cache tag RAM is now read on a clock edge rather than being
combinatorial for reading. Its width is rounded up to a multiple of
8 bits per way so that byte enables can be used for writing
individual tags.
- The cache tag RAM is now written a cycle later than previously, in
order to ease timing.
- Data for a store hit is now written one cycle later than
previously. This eases timing since we don't have to get through
the tag matching and on to the write enable within a single cycle.
The 2-stage bypass path means we can still handle a load hit on
either of the two cycles after the store and return the correct
data. (A load hit 3 or more cycles later will get the correct data
from the BRAM.)
- Operations can sit in r0 while there is an uncompleted operation in
r1. Once the operation in r1 is completed, the operation in r0
spends one cycle in r0 for TLB/cache tag lookup and then gets put
into r1.req. This can happen before r1 gets to the IDLE state.
Some operations can then be completed before r1 gets to the IDLE
state - a load miss to the cache line being refilled, or a store to
the same page as a previous store.
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
Paul Mackerras [Tue, 12 May 2020 06:28:42 +0000 (16:28 +1000)]
decode: Work out ispr1/ispr2 in parallel with decode ROM lookup
This makes the logic that calculates which SPRs are being accessed
work in parallel with the instruction decode ROM lookup instead of
being dependent on the opcode found in the decode ROM. The reason
for doing that is that the path from icache through the decode ROM
to the ispr1/ispr2 fields has become a critical path.
Thus we are now using only a very partial decode of the instruction
word in the logic for isp1/isp2, and we therefore can no longer rely
on them being zero in all cases where no SPR is being accessed.
Instead, decode2 now ignores ispr1/ispr2 in all cases except when the
relevant decode.input_reg_a/b or decode.output_reg_a is set to SPR.
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
Paul Mackerras [Fri, 5 Jun 2020 04:22:02 +0000 (14:22 +1000)]
loadstore1: Reduce busy cycles
This reduces the number of cycles where loadstore1 asserts its busy
output, leading to increased throughput of loads and stores. Loads
that hit in the cache can now be executed at the rate of one every two
cycles. Stores take 4 cycles assuming the wishbone slave responds
with an ack the cycle after we assert strobe.
To achieve this, the state machine code is split into two parts, one
for when we have an existing instruction in progress, and one for
starting a new instruction. We can now combinatorially clear busy and
start a new instruction in the same cycle that we get a done signal
from the dcache; in other words we are completing one instruction and
potentially writing back results in the same cycle that we start a new
instruction and send its address and data to the dcache.
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
Paul Mackerras [Fri, 5 Jun 2020 03:29:34 +0000 (13:29 +1000)]
loadstore1: Complete mfspr/mtspr a cycle later
This makes mfspr and mtspr complete (and mfspr write back) on the
cycle after the instruction is received from execute1, rather than
on the same cycle. This makes them match all other instructions
that execute in one cycle. Because these instructions are marked
as single-issue, there wasn't the possibility of having two
instructions complete on the same cycle (which we can't cope with),
but it is better to fix this.
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
Paul Mackerras [Thu, 4 Jun 2020 10:58:32 +0000 (20:58 +1000)]
core: Use a busy signal rather than a stall
This changes the instruction dependency tracking so that we can
generate a "busy" signal from execute1 and loadstore1 which comes
along one cycle later than the current "stall" signal. This will
enable us to signal busy cycles only when we need to from loadstore1.
The "busy" signal from execute1/loadstore1 indicates "I didn't take
the thing you gave me on this cycle", as distinct from the previous
stall signal which meant "I took that but don't give me anything
next cycle". That means that decode2 proactively gives execute1
a new instruction as soon as it has taken the previous one (assuming
there is a valid instruction available from decode1), and that then
sits in decode2's output until execute1 can take it. So instructions
are issued by decode2 somewhat earlier than they used to be.
Decode2 now only signals a stall upstream when its output buffer is
full, meaning that we can fill up bubbles in the upstream pipe while a
long instruction is executing. This gives a small boost in
performance.
This also adds dependency tracking for rA updates by update-form
load/store instructions.
The GPR and CR hazard detection machinery now has one extra stage,
which may not be strictly necessary. Some of the code now really
only applies to PIPELINE_DEPTH=1.
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
Paul Mackerras [Thu, 28 May 2020 23:38:05 +0000 (09:38 +1000)]
icache: Improve latencies when reloading cache lines
The icache can now detect a hit on a line being refilled from memory,
as we have an array of individual valid bits per row for the line
that is currently being loaded. This enables the request that
initiated the refill to be satisfied earlier, and also enables
following requests to the same cache line to be satisfied before the
line is completely refilled. Furthermore, the refill now starts
at the row that is needed. This should reduce the latency for an
icache miss.
We now get a 'sequential' indication from fetch1, and use that to know
when we can deliver an instruction word using the other half of the
64-bit doubleword that was read last cycle. This doesn't make much
difference at the moment, but it frees up cycles where we could test
whether the next line is present in the cache so that we could
prefetch it if not.
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
Paul Mackerras [Thu, 21 May 2020 07:50:54 +0000 (17:50 +1000)]
multiply: Use DSP48 slices for multiplication on Xilinx FPGAs
This adds a custom implementation of the multiplier which uses 16
DSP48E1 slices to do a 64x64 bit multiplication in 2 cycles.
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
Paul Mackerras [Thu, 21 May 2020 03:42:46 +0000 (13:42 +1000)]
multiply: Move selection of result bits into execute1
This puts the logic that selects which bits of the multiplier result
get written into the destination GPR into execute1, moved out from
multiply.
The multiplier is now expected to do an unsigned multiplication of
64-bit operands, optionally negate the result, detect 32-bit
or 64-bit signed overflow of the result, and return a full 128-bit
result.
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
Paul Mackerras [Wed, 3 Jun 2020 01:26:33 +0000 (11:26 +1000)]
core: Double the dcache and icache sizes
This makes the dcache and icache both be 8kB. This still only uses
one BRAM per way per cache on the Artix-7, since the BRAMs were only
half-used previously.
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
Paul Mackerras [Sun, 10 May 2020 08:18:03 +0000 (18:18 +1000)]
core: Remove fetch2 pipeline stage
The fetch2 stage existed primarily to provide a stash buffer for the
output of icache when a stall occurred. However, we can get the same
effect -- of having the input to decode1 stay unchanged on a stall
cycle -- by using the read enable of the BRAMs in icache, and by
adding logic to keep the outputs unchanged on a clock cycle when
stall_in = 1. This reduces branch and interrupt latency by one
cycle.
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
Paul Mackerras [Thu, 14 May 2020 03:25:48 +0000 (13:25 +1000)]
Add core logging
This logs 256 bits of data per cycle to a ring buffer in BRAM. The
data collected can be read out through 2 new SPRs or through the
debug interface.
The new SPRs are LOG_ADDR (724) and LOG_DATA (725). LOG_ADDR contains
the buffer write pointer in the upper 32 bits (in units of entries,
i.e. 32 bytes) and the read pointer in the lower 32 bits (in units of
doublewords, i.e. 8 bytes). Reading LOG_DATA gives the doubleword
from the buffer at the read pointer and increments the read pointer.
Setting bit 31 of LOG_ADDR inhibits the trace log system from writing
to the log buffer, so the contents are stable and can be read.
There are two new debug addresses which function similarly to the
LOG_ADDR and LOG_DATA SPRs. The log is frozen while either or both of
the LOG_ADDR SPR bit 31 or the debug LOG_ADDR register bit 31 are set.
The buffer defaults to 2048 entries, i.e. 64kB. The size is set by
the LOG_LENGTH generic on the core_debug module. Software can
determine the length of the buffer because the length is ORed into the
buffer write pointer in the upper 32 bits of LOG_ADDR. Hence the
length of the buffer can be calculated as 1 << (31 - clz(LOG_ADDR)).
There is a program to format the log entries in a somewhat readable
fashion in scripts/fmt_log/fmt_log.c. The log_entry struct in that
file describes the layout of the bits in the log entries.
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
Paul Mackerras [Sat, 13 Jun 2020 09:59:17 +0000 (19:59 +1000)]
scripts/mw_debug: Make progress counts display on one line
This outputs a carriage return rather than a newline after the
display of the progress count during the load and save operations.
This makes the output more compact and better looking.
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
Paul Mackerras [Thu, 11 Jun 2020 04:57:30 +0000 (14:57 +1000)]
tests/xics: Fix assumption that interrupts happen immediately
Currently the test writes to the XICS and then checks that the
expected interrupt has happened. This turns into a stbcix
instruction followed immediately by a load from the variable that
indicates whether an interrupt has happened. It is possible for
it to take a few cycles for the store to reach the XICS and the
interrupt request signal to come back to the core, particularly
with improvements to the load/store unit and dcache.
This therefore adds a delay between storing to the XICS and
checking for the occurrence of an interrupt, so as to give the
signals time to propagate. The delay loop does an arbitrary 10
iterations, and each iteration does two loads and one store to
(cacheable) memory.
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
Paul Mackerras [Sat, 13 Jun 2020 07:22:56 +0000 (17:22 +1000)]
register_file: Report value being written before asserting it's not X
If a bug causes an indeterminate value to be written to a GPR, an
assert causes simulation to abort. Move the assert after the report
of the GPR index and value so that we get to know what the bad value
is before the simulation terminates.
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
Paul Mackerras [Sat, 13 Jun 2020 02:36:16 +0000 (12:36 +1000)]
Merge pull request #205 from ozbenh/timing
Timing improvements
Paul Mackerras [Sat, 13 Jun 2020 02:27:40 +0000 (12:27 +1000)]
Merge pull request #204 from ozbenh/spi
Add an SPI master flash controller
Benjamin Herrenschmidt [Fri, 12 Jun 2020 11:48:01 +0000 (21:48 +1000)]
syscon: Remove combinational loop on ack and stall
Those hurt timings. Instead latch the wishbone response for one cycle
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Benjamin Herrenschmidt [Fri, 12 Jun 2020 11:47:06 +0000 (21:47 +1000)]
bram: Remove combinational loop on stall
It hurts timing and is pointless
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Benjamin Herrenschmidt [Fri, 12 Jun 2020 11:46:37 +0000 (21:46 +1000)]
uart: Remove combinational loops on ack and stall signal
They hurt timing forcing signals to come from the master and back
again in one cycle. Stall isn't sampled by the master unless there
is an active cycle so masking it with cyc is pointless. Masking acks
is somewhat pointless too as we don't handle early dropping of cyc
in any of our slaves properly anyways.
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Benjamin Herrenschmidt [Wed, 10 Jun 2020 03:35:18 +0000 (13:35 +1000)]
spi: Add booting from flash to litedram init
It will look for an ELF binary at the flash offset specified
for the board (currently 0x300000 on Arty but that could be
changed).
Note: litedram is regenerated in order to rebuild the init code,
which was done using a newer version of litedram from LiteX.
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Benjamin Herrenschmidt [Wed, 10 Jun 2020 03:35:10 +0000 (13:35 +1000)]
spi: Add simulation support
This require the s25fl128s.vhd flash model and FMF libraries,
which will be built when passed to the Makefile via the
FLASH_MODEL_PATH argument. Otherwise a dummy module is used
which ties MISO to '1'.
The model isn't included as I'm not sure its licence (GPL) is
at this point, but it can be obtained from
https://github.com/ozbenh/microspi
FLASH_MODEL_PATH=<path to microspi>/model
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Dan Horák [Fri, 12 Jun 2020 22:46:28 +0000 (00:46 +0200)]
flash-arty: update error message (#203)
Signed-off-by: Dan Horák <dan@danny.cz>
Benjamin Herrenschmidt [Fri, 12 Jun 2020 22:44:43 +0000 (08:44 +1000)]
dmi: Add ASYNC_REG attribute on synchronizers (#200)
This tells Vivado to keep them close among other things
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Benjamin Herrenschmidt [Fri, 12 Jun 2020 22:43:47 +0000 (08:43 +1000)]
icache: Latch PLRU victim output (#199)
This stores the output of the PLRU big mux and clears the
tags and valid bits on the next cycle.
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Paul Mackerras [Fri, 12 Jun 2020 22:01:55 +0000 (08:01 +1000)]
Merge pull request #198 from ozbenh/litedram
Litedram: Timing improvements
Benjamin Herrenschmidt [Fri, 5 Jun 2020 01:32:08 +0000 (11:32 +1000)]
spi: Add SPI Flash controller
This adds an SPI flash controller which supports direct
memory-mapped access to the flash along with a manual
mode to send commands.
The direct mode can be set via generic to default to single
wire or quad mode. The controller supports normal, dual and quad
accesses with configurable commands, clock divider, dummy clocks
etc...
The SPI clock can be an even divider of sys_clk starting at 2
(so max 50Mhz with our typical Arty designs).
A flash offset is carried via generics to syscon to tell SW about
which portion of the flash is reserved for the FPGA bitfile. There
is currently no plumbing to make the CPU reset past that address (TBD).
Note: Operating at 50Mhz has proven unreliable without adding some
delay to the sampling of the input data. I'm working in improving
this, in the meantime, I'm leaving the default set at 25 Mhz.
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Benjamin Herrenschmidt [Thu, 11 Jun 2020 10:18:24 +0000 (20:18 +1000)]
litedram: L2 use latched refill_index
Not a huge difference since wb_req is itself a latch but
may as well
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Benjamin Herrenschmidt [Wed, 10 Jun 2020 13:45:42 +0000 (23:45 +1000)]
litedram: Pipeline store acks in L2
There is a long timing path to generate the ack signal from
the L2 cache as it's fully combinational for stores, including
signals coming from litedram.
Instead, pipeline the store acks. This will introduce a cycle
latency but should improve timing. Also the core will eventually
be smart enough not to wait for store acks to complete them anyway.
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Benjamin Herrenschmidt [Wed, 10 Jun 2020 09:06:02 +0000 (19:06 +1000)]
arty/nexys-video: Update XDC
The DRAM related pins have some small changes in LiteX, so resync
and add the false path information as well.
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Benjamin Herrenschmidt [Wed, 10 Jun 2020 06:47:18 +0000 (16:47 +1000)]
litedram: Add stash buffer to the L2 cache wishbone interface
This breaks the long stall signal coming back to the processor
and helps improve overall timing.
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Benjamin Herrenschmidt [Wed, 10 Jun 2020 08:00:12 +0000 (18:00 +1000)]
litedram: Defer clearing of tags & valids to improve timing
Currently, there's a huge mux gathering the output of all the PLRUs
to select the victim way on cache miss. This is fed combinationally
into the clearing of the valid and tags.
In order to help timing, let's store it instead and perform the
clearing on the next cycle. The L2 doesn't respond to requests
when not in IDLE state so this should have no negative effects.
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Benjamin Herrenschmidt [Wed, 10 Jun 2020 07:58:27 +0000 (17:58 +1000)]
litedram: Improve dram_tb error output
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Anton Blanchard [Fri, 12 Jun 2020 00:25:09 +0000 (10:25 +1000)]
Merge pull request #201 from mikey/github-actions
Move from travis to github workflows
Michael Neuling [Tue, 9 Jun 2020 23:57:15 +0000 (09:57 +1000)]
Move from travis to github workflow
Github workflow gives us longer run times and faster startup.
Major kudos for this goes to @eine for the initial version and for
pushing us in this direction.
Signed-off-by: Michael Neuling <mikey@neuling.org>
Paul Mackerras [Wed, 10 Jun 2020 09:37:01 +0000 (19:37 +1000)]
Merge pull request #194 from ozbenh/misc
Fix syscon registers usage and add "save" function to mw_debug
Benjamin Herrenschmidt [Wed, 10 Jun 2020 03:14:00 +0000 (13:14 +1000)]
gitignore: Add more exlusions
litedram build directory used by the generator and the
verilator obj_dir can be taken out
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Benjamin Herrenschmidt [Tue, 9 Jun 2020 22:36:44 +0000 (08:36 +1000)]
litedram: Fix DRAM init mem using too many address bits
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Benjamin Herrenschmidt [Fri, 5 Jun 2020 12:28:30 +0000 (22:28 +1000)]
litedram: Remove remnants of riscv-inits
We still had some wires bringing an extra serial port out of
litedram for the built-in riscv processor. This is all gone now
so take them out.
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Benjamin Herrenschmidt [Thu, 4 Jun 2020 10:25:57 +0000 (20:25 +1000)]
mw_debug: Add "save" function to save memory to a file
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Benjamin Herrenschmidt [Thu, 4 Jun 2020 01:56:47 +0000 (11:56 +1000)]
sw: Properly mask syscon register fields
Some fields might get extended with extra bits, use the appropriate
masks when reading the values.
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Michael Neuling [Tue, 9 Jun 2020 23:54:35 +0000 (09:54 +1000)]
Merge pull request #196 from ozbenh/makefile-lib-fix
Makefile: Improve unisim library generation
Michael Neuling [Tue, 9 Jun 2020 23:22:50 +0000 (09:22 +1000)]
Merge pull request #195 from shenki/nexys-video
Nexys video
Benjamin Herrenschmidt [Tue, 9 Jun 2020 22:31:49 +0000 (08:31 +1000)]
Makefile: Improve unisim library generation
The rewrite of the Makefile to use "ghdl -c" somewhat broke building
the unisim library as ghdl doesn't yet support putting files in
separate libraries from a single command line invocation.
The workaround at the time was to put the entire project in "unisim"
which is ... weird and will break if we try to add another library
such as fmf.
This fixes it by generating the library separately using "ghdl -i"
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Joel Stanley [Tue, 9 Jun 2020 01:52:57 +0000 (11:22 +0930)]
flash-arty: Re-add support for running from any path
The changes in
d3c274d01ec1 ("flash-arty: Add support for specifying the file type")
added a local jtagspi.cfg, which meant openocd must be run from the root
of the microwatt directory.
This puts the content into the xilinx-xc7.cfg so the script can be used
from any path again.
Signed-off-by: Joel Stanley <joel@jms.id.au>
Joel Stanley [Tue, 9 Jun 2020 00:42:42 +0000 (10:12 +0930)]
flash-arty: Support Nexys Video's a200
Not an Arty but Anton tests on this board.
Signed-off-by: Joel Stanley <joel@jms.id.au>
Michael Neuling [Fri, 5 Jun 2020 10:17:01 +0000 (20:17 +1000)]
Merge pull request #193 from paulusmack/master
Minor improvements and reformatting
Paul Mackerras [Fri, 5 Jun 2020 08:02:33 +0000 (18:02 +1000)]
Merge pull request #182 from mikey/travis
Travis and testing improvements
Benjamin Herrenschmidt [Fri, 5 Jun 2020 06:23:23 +0000 (16:23 +1000)]
icache: Fix icbi potentially clobbering the icache (#192)
icbi currently just resets the icache. This has some nasty side
effects such as also clearing the TLB, but also the wishbone interface.
That means that any ongoing cycle will be dropped.
However, most of our slaves don't handle that well and will continue
sending acks for already issued requests.
Under some circumstances we can thus restart an icache load and get
spurious ack/data from the wishbone left over from the "cancelled"
sequence.
This has broken booting Linux for me.
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Paul Mackerras [Fri, 5 Jun 2020 01:16:56 +0000 (11:16 +1000)]
decode2: Reformat to 4-space indentation
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
Paul Mackerras [Fri, 5 Jun 2020 01:16:07 +0000 (11:16 +1000)]
decode1: Reformat to 4-space indentation
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
Paul Mackerras [Mon, 1 Jun 2020 06:42:05 +0000 (16:42 +1000)]
decode1: Make ld/std and lwa not be single-issue
These were missed earlier when the single-issue flag was turned off on
the other loads and stores by commit
1a244d34707a ("Remove single-issue
constraint for most loads and stores").
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
Michael Neuling [Sat, 23 May 2020 07:00:24 +0000 (17:00 +1000)]
Improve Travis to run as a matrix job
Can now run all 999 random tests and unit tests in Travis.
Kudos for this goes to @eine. Based on his input from here:
https://github.com/antonblanchard/microwatt/pull/182#issuecomment-
637926957
Signed-off-by: Michael Neuling <mikey@neuling.org>
Michael Neuling [Sun, 24 May 2020 02:09:11 +0000 (12:09 +1000)]
Add unit tests to check and check_light
Signed-off-by: Michael Neuling <mikey@neuling.org>
Michael Neuling [Sun, 24 May 2020 02:08:47 +0000 (12:08 +1000)]
Add unit tests make target
We don't run these but we should.
The SOC tests have bit rotted. We need to fix them but leave them out
for now.
Signed-off-by: Michael Neuling <mikey@neuling.org>
Michael Neuling [Sat, 23 May 2020 06:59:51 +0000 (16:59 +1000)]
Add tests_console make target
Will use when splitting out Travis tests later
Signed-off-by: Michael Neuling <mikey@neuling.org>
Paul Mackerras [Fri, 5 Jun 2020 03:16:56 +0000 (13:16 +1000)]
Merge pull request #191 from ozbenh/litedram
Litedram updates with L2 cache and sim support
Benjamin Herrenschmidt [Fri, 5 Jun 2020 01:45:00 +0000 (11:45 +1000)]
litedram: Make the L2 twice as tall
This increases the number of L2 lines from 32 to 64. The BRAM usage is the
same as they were only half used. There's an increase in LUTs and registers
due to the extra tags and valid bits, but none of it should be in a
space constrained or critical timing path.
We could make it wider instead (256 bytes lines) which would reduce usage
instead, but this increases the latency by 8 cycles. Something to consider
once the L2 is capable of early response on miss and starting reloads
from any point in a line.
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Paul Mackerras [Fri, 5 Jun 2020 01:29:31 +0000 (11:29 +1000)]
core: Do addpcis using the main adder (#189)
By adding logic to decode2 to be able to send the instruction address
down the A input, and making CONST_DX_HI (renamed to CONST_DXHI4) add
4 to the immediate value (easy since the bottom 16 bits were zero),
we can do addpcis using the main adder. This reduces the width of the
result mux and frees up one value in insn_type_t, since we can now use
OP_ADD for addpcis.
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
Benjamin Herrenschmidt [Fri, 5 Jun 2020 01:15:35 +0000 (11:15 +1000)]
litedram: Remove old "VexRiscV" based initializations
Support for this has bitrotted and would require refactoring of L2 to
be brought back. It's also not really needed anymore now that we ship
pre-generated litedram and that LiteX supports what we do.
So take it out, which simplifies some of the scripts as well. This also
fixes up CSR alignment the sim model.
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Paul Mackerras [Fri, 5 Jun 2020 00:54:00 +0000 (10:54 +1000)]
Merge pull request #183 from shawnanastasio/addpcis
Add support for the addpcis instruction
Benjamin Herrenschmidt [Mon, 1 Jun 2020 13:58:47 +0000 (23:58 +1000)]
litedram: Update to latest LiteX/LiteDRAM version
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Benjamin Herrenschmidt [Mon, 1 Jun 2020 22:32:17 +0000 (08:32 +1000)]
litedram: Test bench
The test bench test simple access forms for now, it's a starting point
but it already helped find/fix a bug.
Includes a litedram update to be able to operate the sim model without
inits.
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Benjamin Herrenschmidt [Wed, 27 May 2020 01:06:51 +0000 (11:06 +1000)]
litedram: Add an L2 cache with store queue
This adds a cache between the wishbone and litedram with the following
features (at this point, it's still evolving)
- 128 bytes line width in order to have a reasonable amount of
litedram pipelining on the 128-bit wide data port.
- Configurable geometry otherwise
- Stores are acked immediately on wishbone whether hit or miss
(minus a 2 cycles delay if there's a previous load response in the
way) and sent to LiteDRAM via 8 entries (configurable) store queue
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Benjamin Herrenschmidt [Mon, 25 May 2020 10:20:59 +0000 (20:20 +1000)]
litedram: Add support for booting without BRAM
This adds an option to disable the main BRAM and instead copy a
payload stashed along with the init code in the secondary BRAM
into DRAM and boot from there
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Benjamin Herrenschmidt [Fri, 22 May 2020 08:43:50 +0000 (18:43 +1000)]
litedram: Add simulation support
This adds a simulated litedram model along with the necessary
Makefile gunk to verilate it and wrap it for use by ghdl.
The core_dram_tb test bench is a variant of core_tb with
LiteDRAM simulated. It's not built by default, an explicit
make core_dram_tb
is necessary as to not require verilator to be installed for
the normal build process (also it's slow'ish).
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Paul Mackerras [Thu, 4 Jun 2020 23:29:24 +0000 (09:29 +1000)]
Merge pull request #185 from ozbenh/misc
Small fixes to mw_debug, bin2hex and improve BRAM generation in dcache
Michael Neuling [Thu, 4 Jun 2020 22:38:18 +0000 (08:38 +1000)]
Merge pull request #188 from ozbenh/openocd-tweaks
Openocd tweaks
Benjamin Herrenschmidt [Thu, 4 Jun 2020 13:29:29 +0000 (23:29 +1000)]
flash-arty: Add support for specifying the file type
By default openocd tries to "guess" the file type and interpret
it accordingly. For example it will detect an ELF file based on
the presence of an ELF header and will try to load the relevant
segments into the flash.
This may not be what we want. For example, I want to load the raw
ELF file into the flash.
Additionally the ELF parser in most distro's OpenOCD version
only supports ELF32 and will error out.
This adds a "-t" argument to flash-arty to allow us to specify the
file format. For example "-t bin" will treat the file as raw binary.
Unfortunately I had to copy and modify jtagspi.cfg from OpenOCD
to achieve this.
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Benjamin Herrenschmidt [Thu, 4 Jun 2020 13:13:45 +0000 (23:13 +1000)]
flash-arty: Support hex values for address
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Paul Mackerras [Wed, 3 Jun 2020 04:20:02 +0000 (14:20 +1000)]
Merge pull request #168 from shenki/flash-arty
Scripts to write data to the Arty's SPI flash
Benjamin Herrenschmidt [Mon, 25 May 2020 06:48:47 +0000 (16:48 +1000)]
dcache: Rework RAM wrapper to synthetize better on Xilinx
The global wr_en signal is causing Vivado to generate two TDP (True Dual Port)
block RAMs instead of one SDP (Simple Dual Port) for each cache way. Remove
it and instead apply a AND to the individual byte write enables.
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Benjamin Herrenschmidt [Mon, 1 Jun 2020 08:24:15 +0000 (18:24 +1000)]
bin2hex: Make sure to generate little endian files
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Benjamin Herrenschmidt [Thu, 28 May 2020 14:04:46 +0000 (00:04 +1000)]
mw_debug: Fix memory overflow with "sim" backend
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Anton Blanchard [Tue, 2 Jun 2020 01:54:00 +0000 (11:54 +1000)]
Merge pull request #178 from antonblanchard/intercon
Interconnect timing improvements from Ben
Anton Blanchard [Tue, 2 Jun 2020 00:36:06 +0000 (10:36 +1000)]
Merge pull request #184 from antonblanchard/verific
Delete old verific script
Michael Neuling [Tue, 26 May 2020 06:55:20 +0000 (16:55 +1000)]
Delete bit rotted verific script
We can use ghdl-synth and fusesoc now, so verific is a dead path which
has bit rotted.
Signed-off-by: Michael Neuling <mikey@neuling.org>
Shawn Anastasio [Tue, 26 May 2020 01:08:59 +0000 (20:08 -0500)]
Add a new misc test suite with addpcis tests
The two tests obtain NIA with bl+mflr+addi and then compare it
against addpcis with the minimum and maximum immediate operand values.
They were also tested on a real POWER9 system (in userspace) for good
measure.
Signed-off-by: Shawn Anastasio <shawn@anastas.io>
Shawn Anastasio [Tue, 26 May 2020 01:03:02 +0000 (20:03 -0500)]
Implement the addpcis instruction
This commit adds support for the addpcis instruction from ISA 3.0.
A new input_reg_b_t type, CONST_DX_HI, was added to support the
shifted immediate value used in DX-Form instructions.
Signed-off-by: Shawn Anastasio <shawn@anastas.io>
Benjamin Herrenschmidt [Wed, 20 May 2020 11:00:27 +0000 (21:00 +1000)]
litedram: Split the init memory from the main wrapper
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Benjamin Herrenschmidt [Sun, 17 May 2020 05:04:23 +0000 (15:04 +1000)]
irq: Simplify xics->core irq input
Use a simple wire. common.vhdl types are better kept for things
local to the core. We can add more wires later if we need to for
HV irqs etc...
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Benjamin Herrenschmidt [Mon, 11 May 2020 11:22:07 +0000 (21:22 +1000)]
soc: Rework interconnect
This changes the SoC interconnect such that the main 64-bit wishbone out
of the processor is first split between only 3 slaves (BRAM, DRAM and a
general "IO" bus) instead of all the slaves in the SoC.
The IO bus leg is then latched and down-converted to 32 bits data width,
before going through a second address decoder for the various IO devices.
This significantly reduces routing and timing pressure on the main bus,
allowing to get rid of frequent timing violations when synthetizing on
small'ish FPGAs such as the Artix-7 35T found on the original Arty board.
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Benjamin Herrenschmidt [Fri, 15 May 2020 07:43:51 +0000 (17:43 +1000)]
sw: Add full memory map to .h and use it for litedram .lds
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Anton Blanchard [Sat, 23 May 2020 06:50:12 +0000 (16:50 +1000)]
Merge pull request #181 from antonblanchard/Makefile-rework-2
Pass clock frequency to UART sim wrapper
Anton Blanchard [Sat, 23 May 2020 03:46:43 +0000 (13:46 +1000)]
Pass clock frequency to UART sim wrapper
The UART sim wrapper is currently hard wired to 50 MHz.
Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
Anton Blanchard [Thu, 21 May 2020 02:29:55 +0000 (12:29 +1000)]
Merge pull request #180 from antonblanchard/Makefile-rework
Makefile rework
Anton Blanchard [Wed, 20 May 2020 06:27:06 +0000 (16:27 +1000)]
A little less shouting in the Makefile
Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
Anton Blanchard [Wed, 20 May 2020 06:18:58 +0000 (16:18 +1000)]
Fix the simulated DMI
Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
Anton Blanchard [Wed, 20 May 2020 06:07:13 +0000 (16:07 +1000)]
Exit cleanly from testbench on success
Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
Anton Blanchard [Wed, 20 May 2020 05:37:49 +0000 (15:37 +1000)]
Merge Makefile and Makefile.synth
We still need to a way to our FPGA target on the command line, but this
at least gets us down to a common Makefile.
Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
Anton Blanchard [Wed, 20 May 2020 05:01:42 +0000 (15:01 +1000)]
Add Makefile command line variables to enable docker and podman
Instead of having to edit the Makefile, we can now do:
make DOCKER=1
make PODMAN=1
Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
Anton Blanchard [Wed, 20 May 2020 04:29:50 +0000 (14:29 +1000)]
Rework Makefile
Instead of building each file one by one (and having to track all
the dependencies manually), use the ghdl -c command that does
analysis and elaboration in one go.
Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
Anton Blanchard [Tue, 19 May 2020 05:53:54 +0000 (15:53 +1000)]
Merge pull request #179 from antonblanchard/yosys-verilator
Add yosys/verilator support
Anton Blanchard [Tue, 19 May 2020 05:32:04 +0000 (15:32 +1000)]
Improve make clean
Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
Anton Blanchard [Tue, 19 May 2020 05:18:42 +0000 (15:18 +1000)]
Add yosys/verilator support
Add a microwatt-verilator target that simulates the
ghdl -> yosys -> verilog -> verilator path. A good test of
ghdl/yosys synthesis.
Because the everything is run through synthesis, the instruction
image is baked into the build via the RAM_INIT_FILE generic.
Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
Anton Blanchard [Tue, 19 May 2020 04:27:42 +0000 (14:27 +1000)]
Merge pull request #171 from shenki/mw-debug-features
mw debug features
Anton Blanchard [Tue, 19 May 2020 04:04:19 +0000 (14:04 +1000)]
Merge pull request #173 from Jbalkind/core-vcs-syntax
Changing use of others in core files to satisfy VCS
Joel Stanley [Mon, 11 May 2020 04:22:41 +0000 (13:52 +0930)]
mw_debug: Add README
This describes how to build the tool on Fedora, and on Debian which lacks a packaged
liburjtag as of mid 2020.
Signed-off-by: Joel Stanley <joel@jms.id.au>
Joel Stanley [Sun, 10 May 2020 04:00:26 +0000 (13:30 +0930)]
mw_debug: Add usage text
Signed-off-by: Joel Stanley <joel@jms.id.au>