Konstantinos Margaritis [Wed, 21 Sep 2022 18:33:24 +0000 (18:33 +0000)]
getting better, get rid of the ctr, group src/ref loads
Luke Kenneth Casson Leighton [Wed, 21 Sep 2022 17:18:14 +0000 (18:18 +0100)]
scale-up svshape pseudo-code for striding in DCT/FFT
Luke Kenneth Casson Leighton [Wed, 21 Sep 2022 16:56:57 +0000 (17:56 +0100)]
fix dct/fft test-functions with new "scaling" parameter
https://bugs.libre-soc.org/show_bug.cgi?id=930
Luke Kenneth Casson Leighton [Wed, 21 Sep 2022 14:53:53 +0000 (15:53 +0100)]
missed setting zdim in svshape on DCT modes
Konstantinos Margaritis [Wed, 21 Sep 2022 15:33:49 +0000 (15:33 +0000)]
use sv.subf
Konstantinos Margaritis [Wed, 21 Sep 2022 15:30:45 +0000 (15:30 +0000)]
fix braces
Luke Kenneth Casson Leighton [Wed, 21 Sep 2022 14:46:46 +0000 (15:46 +0100)]
whoops stride already has +1 from SVSTATE class
Luke Kenneth Casson Leighton [Wed, 21 Sep 2022 14:40:16 +0000 (15:40 +0100)]
add SVzd to REMAP (svshape) "stride"
https://bugs.libre-soc.org/show_bug.cgi?id=930
Luke Kenneth Casson Leighton [Wed, 21 Sep 2022 14:36:29 +0000 (15:36 +0100)]
add stride-multiplier for 2D DCT/FFT "in-place" offsets
https://bugs.libre-soc.org/show_bug.cgi?id=930
Konstantinos Margaritis [Wed, 21 Sep 2022 14:28:49 +0000 (14:28 +0000)]
Initial SVP64 attempt to vpx_get4x4sse_cs_svp64_real()
Konstantinos Margaritis [Wed, 21 Sep 2022 14:28:14 +0000 (14:28 +0000)]
use mr instead of li/addi pair
Konstantinos Margaritis [Wed, 21 Sep 2022 13:29:02 +0000 (13:29 +0000)]
fix comments
Konstantinos Margaritis [Wed, 21 Sep 2022 13:07:03 +0000 (13:07 +0000)]
add vpx_get4x4sse_cs_svp64_real() and wrapper
Konstantinos Margaritis [Wed, 21 Sep 2022 13:06:13 +0000 (13:06 +0000)]
First form of fully working SVP64 version
Konstantinos Margaritis [Wed, 21 Sep 2022 13:05:13 +0000 (13:05 +0000)]
reduce number of iterations in test, as it takes too long
Konstantinos Margaritis [Wed, 21 Sep 2022 08:50:13 +0000 (08:50 +0000)]
necessary changes for run_a_simulation to work with pypowersim_wrapper
Konstantinos Margaritis [Wed, 21 Sep 2022 08:49:11 +0000 (08:49 +0000)]
Initial attempt for SVP64 asm version of vpx_get_mb_ss_svp64_real()
Luke Kenneth Casson Leighton [Wed, 21 Sep 2022 00:15:46 +0000 (01:15 +0100)]
add sv.madd* to sv_analysis
Jacob Lifshay [Wed, 21 Sep 2022 00:00:48 +0000 (17:00 -0700)]
add sv.maddld test case
Luke Kenneth Casson Leighton [Tue, 20 Sep 2022 23:46:18 +0000 (00:46 +0100)]
minor codemorph, whitespace
Luke Kenneth Casson Leighton [Tue, 20 Sep 2022 20:27:33 +0000 (21:27 +0100)]
sv.bc reclassified as RM-2P-1S by eliminating SPRs.
strictly it should be RM-1P-1S but there is a bug. needs investigation.
sv_analysis temporarily classifies as twin predication for now
Konstantinos Margaritis [Tue, 20 Sep 2022 20:16:25 +0000 (20:16 +0000)]
PoC simplified and isolated unit test for libvpx (VP8 & VP9) that uses pypowersim_wrapper
Konstantinos Margaritis [Tue, 20 Sep 2022 20:14:46 +0000 (20:14 +0000)]
Initial PoC for calling pypowersim from within C code
Luke Kenneth Casson Leighton [Tue, 20 Sep 2022 19:44:51 +0000 (20:44 +0100)]
remove messy string identification, use RM Mode from database
in sv/trans/svp64.py
Luke Kenneth Casson Leighton [Tue, 20 Sep 2022 16:43:32 +0000 (17:43 +0100)]
add quick test and loooong test of pysvp64dis - branches split out
Dmitry Selyutin [Tue, 20 Sep 2022 14:14:03 +0000 (17:14 +0300)]
pysvp64asm: fix sz handling
Dmitry Selyutin [Tue, 20 Sep 2022 13:39:56 +0000 (16:39 +0300)]
power_insn: unify predicates
Dmitry Selyutin [Tue, 20 Sep 2022 12:55:33 +0000 (15:55 +0300)]
test_pysvp64dis: test vli specifier
Dmitry Selyutin [Tue, 20 Sep 2022 12:55:22 +0000 (15:55 +0300)]
pysvp64asm: support vli specifier
Dmitry Selyutin [Tue, 20 Sep 2022 12:55:11 +0000 (15:55 +0300)]
power_insn: support vli specifier
Dmitry Selyutin [Tue, 20 Sep 2022 11:36:18 +0000 (14:36 +0300)]
power_insn: simplify specifiers sorting
Luke Kenneth Casson Leighton [Tue, 20 Sep 2022 11:13:43 +0000 (12:13 +0100)]
missed one sorting order in test_pysvp64dis.py
Luke Kenneth Casson Leighton [Tue, 20 Sep 2022 11:11:57 +0000 (12:11 +0100)]
sort specifiers in pysvp64dis in lexicographical order
Luke Kenneth Casson Leighton [Tue, 20 Sep 2022 11:06:00 +0000 (12:06 +0100)]
add two extra tests, sv.bc/m=r3/sz
Dmitry Selyutin [Tue, 20 Sep 2022 10:23:44 +0000 (13:23 +0300)]
power_insn: custom sz handling for branches
Dmitry Selyutin [Tue, 20 Sep 2022 10:23:15 +0000 (13:23 +0300)]
pysvp64asm: update sz upon snz specifier
Luke Kenneth Casson Leighton [Tue, 20 Sep 2022 09:56:56 +0000 (10:56 +0100)]
add sv.bc/ctr/vsb unit test to test_pysvp64dis.py to show it is possible
Dmitry Selyutin [Tue, 20 Sep 2022 00:45:48 +0000 (03:45 +0300)]
power_insn: support vs/vsi/vsb/vsbi/ctr/cti specifiers
Dmitry Selyutin [Mon, 19 Sep 2022 21:27:23 +0000 (00:27 +0300)]
pysvp64asm: support branch modes
Dmitry Selyutin [Tue, 20 Sep 2022 00:32:37 +0000 (03:32 +0300)]
power_svp64_rm: sync it with tables
Dmitry Selyutin [Mon, 19 Sep 2022 22:09:45 +0000 (01:09 +0300)]
power_insn: support common branch disassembly
Dmitry Selyutin [Mon, 19 Sep 2022 21:47:09 +0000 (00:47 +0300)]
power_insn: simplify branch table
Dmitry Selyutin [Mon, 19 Sep 2022 21:24:37 +0000 (00:24 +0300)]
power_insn: provide SVL/CTR branch fields
Luke Kenneth Casson Leighton [Mon, 19 Sep 2022 21:00:15 +0000 (22:00 +0100)]
add bc_ctr and bc_cti but not used yet
Luke Kenneth Casson Leighton [Mon, 19 Sep 2022 20:56:44 +0000 (21:56 +0100)]
print out reg num in _check_regs, useful debug
Dmitry Selyutin [Mon, 19 Sep 2022 20:29:31 +0000 (23:29 +0300)]
test_pysvp64dis: test els specifier
Dmitry Selyutin [Mon, 19 Sep 2022 20:27:45 +0000 (23:27 +0300)]
power_insn: support els specifier
Luke Kenneth Casson Leighton [Mon, 19 Sep 2022 17:22:42 +0000 (18:22 +0100)]
cut cruft in caller.py
Luke Kenneth Casson Leighton [Mon, 19 Sep 2022 16:04:05 +0000 (17:04 +0100)]
codemorph on rc handling
Luke Kenneth Casson Leighton [Mon, 19 Sep 2022 15:56:01 +0000 (16:56 +0100)]
codemorph
Luke Kenneth Casson Leighton [Mon, 19 Sep 2022 15:44:54 +0000 (16:44 +0100)]
first interation (ha ha) src/dst iterators for ISACaller
Luke Kenneth Casson Leighton [Mon, 19 Sep 2022 14:30:26 +0000 (15:30 +0100)]
codemorph reduce indentation
Luke Kenneth Casson Leighton [Mon, 19 Sep 2022 14:21:31 +0000 (15:21 +0100)]
code cleanup on ISACaller write_output
Luke Kenneth Casson Leighton [Mon, 19 Sep 2022 12:31:23 +0000 (13:31 +0100)]
rename to avoid conflict pred_dz from pred_dst_zero
Luke Kenneth Casson Leighton [Mon, 19 Sep 2022 12:25:03 +0000 (13:25 +0100)]
another code-morph splitting out the src/dst mask preparation
from actual use of it to perform skipping (advancing src/dst step)
Luke Kenneth Casson Leighton [Mon, 19 Sep 2022 08:15:18 +0000 (09:15 +0100)]
add function for calling a simulation
Luke Kenneth Casson Leighton [Mon, 19 Sep 2022 07:37:45 +0000 (08:37 +0100)]
another code-morph working towards getting the predicate-skipping
into the iterator-looping
Luke Kenneth Casson Leighton [Mon, 19 Sep 2022 07:22:26 +0000 (08:22 +0100)]
whitespace
Luke Kenneth Casson Leighton [Mon, 19 Sep 2022 07:21:54 +0000 (08:21 +0100)]
code-morph in StepLoop work towards splitting into iterators
Luke Kenneth Casson Leighton [Mon, 19 Sep 2022 07:12:41 +0000 (08:12 +0100)]
add svstate param to constructor of StepLoop, ISACaller
Luke Kenneth Casson Leighton [Mon, 19 Sep 2022 07:02:48 +0000 (08:02 +0100)]
move two big step/loop functions into separate class out of ISACaller
Dmitry Selyutin [Sun, 18 Sep 2022 21:57:09 +0000 (00:57 +0300)]
power_insn: perform cleanup; turn comments into docstrings
Luke Kenneth Casson Leighton [Sun, 18 Sep 2022 21:19:43 +0000 (22:19 +0100)]
code-comments identifying tables
Luke Kenneth Casson Leighton [Sun, 18 Sep 2022 21:17:22 +0000 (22:17 +0100)]
simplify predicate mask reporting. assign dw=sw=mask then test 2P
and assign sw new value
Luke Kenneth Casson Leighton [Sun, 18 Sep 2022 21:08:04 +0000 (22:08 +0100)]
use widths.get(dw/sw) and test empty/non-empty after.
Luke Kenneth Casson Leighton [Sun, 18 Sep 2022 20:59:57 +0000 (21:59 +0100)]
fix predicate mask case when smask was zero but mmode was not
quick/easy way: use predicates.get((mmode,smask)) and if empty skip
added stack of tests, 1P and 2P, to test_pysvp64dis.py
Luke Kenneth Casson Leighton [Sun, 18 Sep 2022 20:34:39 +0000 (21:34 +0100)]
no, better than hack-job, stop CROpSimpleRM deriving from MRBaseRM
that way it can handle "/rg" on its own
Luke Kenneth Casson Leighton [Sun, 18 Sep 2022 20:32:14 +0000 (21:32 +0100)]
bit of a hack-job, a base class MRBaseRM - MapReduce RM - was confused
there is no need to report "/mr" on a "Simple" mode, which was deriving
from MRBaseRM
Luke Kenneth Casson Leighton [Sun, 18 Sep 2022 20:20:00 +0000 (21:20 +0100)]
correct COopFF3RM and CRopSimpleRM: extra sz field and sz/dz/zz bit 6
Dmitry Selyutin [Sun, 18 Sep 2022 19:34:25 +0000 (22:34 +0300)]
power_insn: introduce common mr/mrr RM class
Dmitry Selyutin [Sun, 18 Sep 2022 18:55:49 +0000 (21:55 +0300)]
power_insn: support ff/pr predicates
Dmitry Selyutin [Sun, 18 Sep 2022 19:17:33 +0000 (22:17 +0300)]
pysvp64asm: restore original BO
Dmitry Selyutin [Sun, 18 Sep 2022 18:56:22 +0000 (21:56 +0300)]
power_insn: fix CR ops classes naming
Dmitry Selyutin [Sun, 18 Sep 2022 18:37:44 +0000 (21:37 +0300)]
power_insn: fix coding style
Dmitry Selyutin [Sun, 18 Sep 2022 18:36:19 +0000 (21:36 +0300)]
power_insn: introduce common dz/sz RM classes
Dmitry Selyutin [Sun, 18 Sep 2022 18:21:24 +0000 (21:21 +0300)]
power_insn: introduce common zz RM class
Dmitry Selyutin [Sun, 18 Sep 2022 18:18:20 +0000 (21:18 +0300)]
power_insn: introduce common Sat RM class
Dmitry Selyutin [Sun, 18 Sep 2022 18:16:43 +0000 (21:16 +0300)]
power_insn: introduce common FFPRRc0 RM class
Dmitry Selyutin [Sun, 18 Sep 2022 18:05:37 +0000 (21:05 +0300)]
power_insn: simplify RM classes naming
Luke Kenneth Casson Leighton [Sun, 18 Sep 2022 19:20:06 +0000 (20:20 +0100)]
add first attempt at swapping inner/outer vl/subvl loops pack/unpack
no swap still fine, swap is borked
Luke Kenneth Casson Leighton [Sun, 18 Sep 2022 19:18:49 +0000 (20:18 +0100)]
add new svstep mode setting up pack/unpack
in simplev.mdwn pseudocode
Luke Kenneth Casson Leighton [Sun, 18 Sep 2022 17:33:01 +0000 (18:33 +0100)]
sigh, check length of string returned, if non-zero add space
Luke Kenneth Casson Leighton [Sun, 18 Sep 2022 17:31:35 +0000 (18:31 +0100)]
sort out CR RM Mode (sz/dz bits moved, consistent)
Luke Kenneth Casson Leighton [Sun, 18 Sep 2022 17:28:50 +0000 (18:28 +0100)]
add comments (links to URLs) into power_insns.py for RM modes
Luke Kenneth Casson Leighton [Sun, 18 Sep 2022 17:25:21 +0000 (18:25 +0100)]
remove f"" use simpler code, easier to read
Luke Kenneth Casson Leighton [Sun, 18 Sep 2022 16:33:32 +0000 (17:33 +0100)]
reverse decode_bo inv/eq/lt/le/etc. thing
rather than piss about modifying the table itself, do an MSB0-LSB0 swap
Luke Kenneth Casson Leighton [Sun, 18 Sep 2022 16:17:04 +0000 (17:17 +0100)]
dumb. accidentally removed test-call
Luke Kenneth Casson Leighton [Sun, 18 Sep 2022 16:14:04 +0000 (17:14 +0100)]
add unit tests for Rc=1 ffirst/predicate-result
to test_pysvp64dis.py
Dmitry Selyutin [Sun, 18 Sep 2022 16:05:42 +0000 (19:05 +0300)]
test_pysvp64dis: test RC1/~RC1 in ff/pr
Dmitry Selyutin [Sun, 18 Sep 2022 16:05:11 +0000 (19:05 +0300)]
power_insn: fix Rc operand accessor
Dmitry Selyutin [Sun, 18 Sep 2022 15:32:33 +0000 (18:32 +0300)]
power_insn: support RC1/~RC1 in ff/pr
Luke Kenneth Casson Leighton [Sun, 18 Sep 2022 15:23:20 +0000 (16:23 +0100)]
comment principle behind new tables in power_insn.py
https://libre-soc.org/irclog/%23libre-soc.2022-09-18.log.html#t2022-09-18T16:22:37
Luke Kenneth Casson Leighton [Sun, 18 Sep 2022 15:17:59 +0000 (16:17 +0100)]
redo branch mode as a table, in power_insn.py
Dmitry Selyutin [Sun, 18 Sep 2022 15:17:05 +0000 (18:17 +0300)]
power_insn: adjust table comments
Dmitry Selyutin [Sun, 18 Sep 2022 15:13:40 +0000 (18:13 +0300)]
power_insn: another minor ld/st imm table cleanup
Dmitry Selyutin [Sun, 18 Sep 2022 15:12:24 +0000 (18:12 +0300)]
pysvp64asm: make zz also set src_zero
Dmitry Selyutin [Sun, 18 Sep 2022 15:08:18 +0000 (18:08 +0300)]
power_insn: minor CR cleanup
Dmitry Selyutin [Sun, 18 Sep 2022 15:06:00 +0000 (18:06 +0300)]
power_insn: minor cleanup
Luke Kenneth Casson Leighton [Sun, 18 Sep 2022 15:06:37 +0000 (16:06 +0100)]
code-morph CR ops to table in power_insn.py
put 3/5-bit detection into one of the options to search in mask/val form
Luke Kenneth Casson Leighton [Sun, 18 Sep 2022 14:52:41 +0000 (15:52 +0100)]
code-morph in power_insn.py - move table-search to separate area