llvmpipe: get rid of llvmpipe_get_texture_image

The only caller left used it only for non display target textures,
hence it was really the same as llvmpipe_get_texture_image_address - it
also had a usage flag but this was ignored anyway.

Reviewed-by: Brian Paul <brianp@vmware.com>

llvmpipe: get rid of llvmpipe_get_texture_image_all

Once used for invoking swizzled->linear conversion for all needed images.
But we now have a single allocation for all images in a resource, thus looping
through all slices is rather pointless, conversion doesn't happen neither.
Also simplify the sampling setup code to use the mip_offsets array in the
resource directly - if the (non display target) resource exists its memory
will already be allocated as well.

Reviewed-by: Brian Paul <brianp@vmware.com>

llvmpipe: allocate regular texture memory upfront

The deferred allocation doesn't really make much sense anymore, since we no
longer allocate swizzled/linear memory in chunks and not per level / slice
neither.
This means we could fail resource creation a bit more (could already fail in
theory anyway) but should not fail maps later (right now, callers can't deal
with neither really).

Reviewed-by: Brian Paul <brianp@vmware.com>

llvmpipe: get rid of linear_img struct

Just use a tex_data pointer directly - the description was no longer correct
neither.

Reviewed-by: Brian Paul <brianp@vmware.com>

llvmpipe: (trivial) rename linear_mip_offsets to mip_offsets

Since switching to non-swizzled rendering we only have "normal", aka linear,
offsets.

Reviewed-by: Brian Paul <brianp@vmware.com>

target-helpers: don't use designated initializers

it looks since ce1a1372280d737a1b85279995529206586ae480 they are now included
in more places, in particular even for things buildable with msvc, and hence
those break the build.

Reviewed-by: Brian Paul <brianp@vmware.com>
Reviewed-by: Emil Velikov <emil.l.velikov@gmail.com>

st/mesa: add support for indirect drawing

gallium/u_vbuf: get draw info from an indirect buffer if there's any

This is required for fallbacks to work with ARB_draw_indirect.

gallium: add facilities for indirect drawing

v2:
Added comments to util_draw_indirect, clarified and fixed map size.
Removed unlikely().

gallium: add PIPE_BIND_COMMAND_ARGS_BUFFER

Intended for use with GL_ARB_draw_indirect's DRAW_INDIRECT_BUFFER
target or for D3D11_RESOURCE_MISC_DRAWINDIRECT_ARGS.

xmlconfig/dri: bool -> unsigned char

Drop stdbool, due to the X server being a pain and having
struct members called bool, although I've sent a patch to fix
that we should retain stupidity here. Use unsigned char
which is what GLboolean is anyways.

Signed-off-by: Dave Airlie <airlied@redhat.com>

i965/fs: Update discard jump to preserve uniform loads via sampler.

Commit 17c7ead7 exposed a bug in how uniform loading happens in the
presence of discard.  It manifested itself in an application as
randomly incorrect pixels on the borders of conditional areas.

This is due to how discards jump to the end of the shader incorrectly
for some channels.  The current implementation checks each 2x2
subspan to preserve derivatives.  When uniform loading via samplers
was turned on, it uses a full execution mask, as stated in
lower_uniform_pull_constant_loads(), and only populates four channels
of the destination (see generate_uniform_pull_constant_load_gen7()).
It happens incorrectly when the first subspan has been jumped over.

The series that implemented this optimization was done before the
changes to use samplers for uniform loads.  Uniform sampler loads
use special execution masks and only populate four channels, so we
can't jump over those or corruption ensues.

This fix only jumps to the end of the shader if all relevant channels
are disabled, i.e. all 8 or 16, depending on dispatch.  This
preserves the original GLbenchmark 2.7 speedup noted in commit
beafced2.

It changes the shader assembly accordingly:

before   : (-f0.1.any4h)  halt(8)  17 2  null { align1 WE_all 1Q };
after(8) : (-f0.1.any8h)  halt(8)  17 2  null { align1 WE_all 1Q };
after(16): (-f0.1.any16h) halt(16) 17 2  null { align1 WE_all 1H };

v2: Cleaned up comments and conditional ordering.
v3: Fix typo.

Signed-off-by: Cody Northrop <cody@lunarg.com>
Reviewed-by: Mike Stroyan <mike@lunarg.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=79948

i965/fs: Mark case unreachable to silence warning.

Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>

i965: Use unreachable() instead of unconditional assert().

Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>

mesa: Make unreachable macro take a string argument.

To aid in debugging.

Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>

i965/vec4: Remove useless conditionals.

Setting a couple of bits is the same cost or less as conditionally
setting a couple of bits.

i965/fs: Pass cfg to calculate_live_intervals().

We've often created the CFG immediately before, so use it when
available.

Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>

i965: Mark fields in the live interval classes protected.

cfg, for instance, is a pointer to a local variable in
calculate_live_intervals, certainly not valid after that function has
returned.

Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>

glsl: Remove now unused foreach_list* macros.

foreach_list_typed_const was never used as far as I can tell.

Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>

i965: Use typed foreach_in_list_safe instead of foreach_list_safe.

Acked-by: Ian Romanick <ian.d.romanick@intel.com>

i965: Use typed foreach_in_list instead of foreach_list.

Acked-by: Ian Romanick <ian.d.romanick@intel.com>

i965: Add and use foreach_inst_in_block macros.

Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>

i965/fs: Use is_head_sentinel() instead of ->prev == NULL.

Makes it more clear what we're doing and requires less knowledge of
exec_list.

Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>

mesa: Add and use foreach_list_typed_safe.

Acked-by: Ian Romanick <ian.d.romanick@intel.com>

mesa: Add and use foreach_in_list_use_after.

Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>

glsl: Replace uses of foreach_list_const.

Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>

glsl: Replace another couple uses of foreach_list.

Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>

glsl: Use foreach_list_typed when possible.

Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>

mesa: Use typed foreach_in_list_safe instead of foreach_list_safe.

Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>

glsl: Use typed foreach_in_list_safe instead of foreach_list_safe.

Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>

mesa: Use typed foreach_in_list instead of foreach_list.

Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>

glsl: Use typed foreach_in_list instead of foreach_list.

Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>

glsl: Add typed foreach_in_list_safe macro.

Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>

glsl: Add typed foreach_in_list/_reverse macros.

Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>

mesa: fix the condition in src/loader/Makefile.am

We want to have the dri common files compiled to define USE_DRICONF.
We need to check both NEED_OPENGL_COMMON and HAVE_DRICOMMON

Signed-off-by: Axel Davy <axel.davy@ens.fr>
Tested-by: Brian Paul <brianp@vmware.com>

mesa: update comment for UniformBufferSize to indicate size is in bytes

Reviewed-by: Roland Scheidegger <sroland@vmware.com>

st/mesa: fix incorrect size of UBO declarations

UniformBufferSize is in bytes so we need to divide by 16 to get the
number of constant buffer slots.  Also, the ureg_DECL_constant2D()
function takes first..last parameters so we need to subtract one
for the last value.

Reviewed-by: Roland Scheidegger <sroland@vmware.com>

st/mesa: don't use address register for constant-indexed ir_binop_ubo_load

Before, we were always using the address register and indirect addressing
to index into a UBO constant buffer.  With this change we only do that
when necessary.

Using the piglit bin/arb_uniform_buffer_object-rendering test as an
example:

Shader code:
  uniform ub_rot {float rotation; };
  ...
  m[1][1] = cos(rotation);

Before:
  IMM[1] INT32 {0, 1, 0, 0}
  1: UARL ADDR[0].x, IMM[1].xxxx
  2: MOV TEMP[0].x, CONST[3][ADDR[0].x].xxxx
  3: COS TEMP[1].x, TEMP[0].xxxx

After:
  0: COS TEMP[0].x, CONST[3][0].xxxx

Reviewed-by: Roland Scheidegger <sroland@vmware.com>

st/mesa: allow 2D indexing for all shader types in translate_src()

Reviewed-by: Roland Scheidegger <sroland@vmware.com>

st/mesa: don't ignore const buf index in src_register()

Otherwise, if we were creating a const buffer src register for a UBO
the index into the UBO was always zero.

Reviewed-by: Roland Scheidegger <sroland@vmware.com>

nvc0: expose 4 vertex streams, use stream ids in xfb

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>

nvc0/ir: only merge emit/restart for identical streams

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>

nvc0/ir: avoid creating restarts with non-0 stream

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>

nvc0/ir: fix emitting vertex stream

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>

mesa/st: add vertex stream support

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Brian Paul <brianp@vmware.com>
Reviewed-by: Roland Scheidegger <sroland@vmware.com>

gallium: add a cap for max vertex streams

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Brian Paul <brianp@vmware.com>
Reviewed-by: Roland Scheidegger <sroland@vmware.com>

gallium: add an index argument to create_query

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Roland Scheidegger <sroland@vmware.com>

gallium: add support for stream in so info

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Brian Paul <brianp@vmware.com>
Reviewed-by: Roland Scheidegger <sroland@vmware.com>

gallium: add vertex stream argument to EMIT/ENDPRIM

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Brian Paul <brianp@vmware.com>
Reviewed-by: Roland Scheidegger <sroland@vmware.com>

i965/fs: Mark predicated PLN instructions with dependency hints.

To implement the unlit_centroid_workaround, previously we emitted

   (+f0) pln(8) g20<1>F g16.4<0,1,0>F g4<8,8,1>F { align1 1Q };
   (-f0) pln(8) g20<1>F g16.4<0,1,0>F g2<8,8,1>F { align1 1Q };

where the flag register contains the channel enable bits from g0.

Since the predicates are complementary, the pair of pln instructions
write to non-overlapping components of the destination, which is the
case that the dependency control hints are designed for.

Typically setting dependency control hints on predicated instructions
isn't safe (if an instruction doesn't execute due to the predicate, it
won't update the scoreboard, leaving it in a bad state) but since we
must have at least one channel executing (i.e., +f0 is true for some
channel) by virtue of the fact that the thread is running, we can put
the +f0 pln instruction last and set the hints:

   (-f0) pln(8) g20<1>F g16.4<0,1,0>F g2<8,8,1>F { align1 NoDDClr 1Q };
   (+f0) pln(8) g20<1>F g16.4<0,1,0>F g4<8,8,1>F { align1 NoDDChk 1Q };

Reviewed-by: Kristian Høgsberg <krh@bitplanet.net>

i965/fs: Predicate PLN instructions used in unlit centroid WA.

Maybe lets us skip some PLN instructions if whole subspans are disabled?

Reviewed-by: Kristian Høgsberg <krh@bitplanet.net>

i965/fs: Add no_dd_{clear,check} fields to fs_inst.

And plumb them through. Also make the assert in the generator look like
the vec4 one.

Reviewed-by: Kristian Høgsberg <krh@bitplanet.net>

i965/fs: Let sat-prop ignore live ranges if producer already has sat.

This sequence (where both x and w are used afterwards) wasn't handled.

   mul.sat x, y, z
   ...
   mov.sat w, x

We assumed that if x was used after the mov.sat, that we couldn't
propagate the saturate modifier, but in fact x was already saturated.

So ignore the live range check if the producing instruction already
saturates its result. Cuts one instruction from hundreds of TF2 shaders.

total instructions in shared programs: 1995631 -> 1994951 (-0.03%)
instructions in affected programs:     155248 -> 154568 (-0.44%)

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

i965/fs: Pass const references to emit functions.

Cuts 10k of .text and saves a bunch of useless struct copies.

i965/vec4: Pass const references to instruction functions.

   text    data     bss     dec     hex filename
4231165  123200   39648 4394013  430c1d i965_dri.so
4186277  123200   39648 4349125  425cc5 i965_dri.so

Cuts 43k of .text and saves a bunch of useless struct copies.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

i965/vec4: Pass const references to vec4_instruction().

   text    data     bss     dec     hex filename
4244821  123200   39648 4407669  434175 i965_dri.so
4231165  123200   39648 4394013  430c1d i965_dri.so

Cuts 13k of .text and saves a bunch of useless struct copies.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

i965/fs: Pass const references to instruction functions.

   text    data     bss     dec     hex filename
4270747  123200   39648 4433595  43a6bb i965_dri.so
4244821  123200   39648 4407669  434175 i965_dri.so

Cuts 25k of .text and saves a bunch of useless struct copies.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

radeonsi: Use dma_copy when possible for si_blit.

This improves GLX DRI3 GPU offloading significantly on CPU
bound benchmarks particularly.
No performance impact for DRI2 GPU offloading.

v2: Add missing tests

Signed-off-by: Axel Davy <axel.davy@ens.fr>
Reviewed-by: Marek Olšák<marek.olsak@amd.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>

glx/dri3: add GPU offloading support.

The differences with DRI2 GPU offloading are:
a) There's no logic for GPU offloading needed in the Xserver

b) for DRI2, the card would render to a back buffer, and
the content would be copied to the front buffer (the same buffers
everytime). Here we can potentially use several back buffers and copy
to buffers with no tiling to share with X. We send them with the
Present extension.

That means than the DRI2 solution is forced to have tearings with GPU
offloading. In the ideal scenario, this DRI3 solution doesn't have this
problem.

However without dma-buf fences, a race can appear (if the card is slow
and the rendering hasn't finished before the server card reads the buffer),
and then old content is displayed. If a user hits this, he should probably
revert to the DRI2 solution (LIBGL_DRI3_DISABLE). Users with cards fast
enough seem to not hit this in practice (I have an Amd hd 7730m, and I
don't hit this, except if I force a low dpm mode)

c) for non-fullscreen apps, the DRI2 GPU offloading solution requires
compositing. This DRI3 solution doesn't have this requirement. Rendering
to a pixmap also works.

d) There is no need to have a DDX loaded for the secondary card.

V4: Fixes some piglit tests

Signed-off-by: Axel Davy <axel.davy@ens.fr>
Signed-off-by: Dave Airlie <airlied@redhat.com>

loader: Use drirc device_id parameter in complement to DRI_PRIME

DRI_PRIME is not very handy, because you have to launch the executable
with it set, which is not always easy to do.
By using drirc, the user specifies the target executable
and the device to use. After that the program will be launched everytime
on the target device.

For example if .drirc contains:

<driconf>
    <device driver="loader">
        <application name="Glmark2" executable="glmark2">
            <option name="device_id" value="pci-0000_01_00_0" />
        </application>
    </device>
</driconf>

Then glmark2 will use if possible the render-node of
ID_PATH_TAG pci-0000_01_00_0.

v2: Fix compilation issue
v3: Add "-lm" and rebase.

Signed-off-by: Axel Davy <axel.davy@ens.fr>
Reviewed-by: Emil Velikov <emil.l.velikov@gmail.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>

loader: add gpu selection code via DRI_PRIME.

v2: Fix the leak of device_name
v3: Rebased

It enables to use the DRI_PRIME env var to specify
which gpu to use.
Two syntax are supported:
If DRI_PRIME is 1 it means: take any other gpu than the default one.
If DRI_PRIME is the ID_PATH_TAG of a device: choose this device if
possible.

The ID_PATH_TAG is a tag filled by udev.
You can check it with 'udevadm info' on the device node.
For example it can be "pci-0000_01_00_0".

Render-nodes need to be enabled to choose another gpu,
and they need to have the ID_PATH_TAG advertised.
It is possible for not very recent udev that the tag
is not advertised for render-nodes, then
ones need to add a file containing:

SUBSYSTEM=="drm", IMPORT{builtin}="path_id"

in /etc/udev/rules.d/

Signed-off-by: Axel Davy <axel.davy@ens.fr>
Reviewed-by: Emil Velikov <emil.l.velikov@gmail.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>

drirc: Add string support

Reviewed-by: Dave Airlie <airlied@redhat.com>
Signed-off-by: Axel Davy <axel.davy@ens.fr>

dri: remove GL types from config queries

This in theory changes ABI for the boolean->bool I think,
but nothing in the tree uses configQueryb AFAICS.

Reviewed-by: Axel Davy <axel.davy@ens.fr>
Signed-off-by: Dave Airlie <airlied@redhat.com>

dri/xmlconfig: remove GL types.

This just drops all the GL types from the xmlconfig and use
std C types from stdint and stdbool.

v2: drop further double and header include.

Reviewed-by: Eric Anholt <eric@anholt.net>
Signed-off-by: Dave Airlie <airlied@redhat.com>

dri3: cache pointer to back instead of looking up.

This is just prep work for the dri3 prime patches.

Signed-off-by: Dave Airlie <airlied@redhat.com>

configure.ac: (trivial) Fixing a typo

Signed-off-by: Alexandre Demers <alexandre.f.demers@gmail.com>
Reviewed-by: Emil Velikov <emil.l.velikov@gmail.com>

targets/egl-static: use inline_drm_helper and Automake.inc helpers

Update all three build systems, and add freedreno to the android
build. Pending future work on the ST we can convert egl-static
to provide either static or dynamic access to the pipe-drivers.

There is no functional change with this patch.

v2: Don't add freedreno to android build, drop the wrapper winsys.

Cc: Chia-I Wu <olv@lunarg.com>
Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>

targets/gbm: convert to static/shared pipe-driver

Move the gbm "target" code to the state-tracker, similar
to other - dri, omx, vdpau... ST.

v2: Drop inclusion of the wrapper winsys and softpipe/llvmpipe.

Cc: Chia-I Wu <olv@lunarg.com>
Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>

targets/xa: provide alternative(static) xa target

Now we can build the xa target (libxatracker) with either static
pipe-drivers or shared ones. Currently we default to static.

 - Remove the unused CFLAGS/CPPFLAGS.
 - Use GALLIUM_TARGET_CFLAGS where applicable.

v2: Update the printout messages at configure.
v3: Drop inclusion of the wrapper winsys and softpipe/llvmpipe.

Cc: Jakob Bornecrantz <jakob@vmware.com>
Cc: Rob Clark <robclark@freedesktop.org>
Cc: Thomas Hellstrom <thellstrom@vmware.com>
Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>

i965/disasm: Fix INTEL_DEBUG=fs on Broadwell for ARB_fp applications.

Apparently INTEL_DEBUG=fs has crashed on Broadwell for anything using
ARB_fragment_program since commit 9cee3ff5.  We need to NULL-check the
right field.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Kristian Høgsberg <krh@bitplanet.net>
Cc: "10.2" <mesa-stable@lists.freedesktop.org>

i965/disasm: Delete gen8_disasm.c.

The functionality has been merged into brw_disasm.c; use that instead.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Kristian Høgsberg <krh@bitplanet.net>

i965/disasm: Stop using gen8_disassemble in favor of brw_disassemble.

At this point, brw_disassemble can do everything gen8_disassemble can
do - and, thanks to the new brw_inst API, it supports all generations.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Kristian Høgsberg <krh@bitplanet.net>

i965/disasm: Improve render target write message disassembly.

Previously, we decoded render target write messages as:

   render ( RT write, 0, 16, 12, 0) mlen 8 rlen 0

which made you remember (or look up) what the numbers meant:

1. The binding table index
2. The raw message control, undecoded:
   - Last Render Target Select
   - Slot Group Select
   - Message Type (SIMD8, normal SIMD16, SIMD16 replicate data, ...)
3. The dataport message type, again (already decoded as "RT write")
4. The write commit bit (0 or 1)

Needless to say, having to decipher that yourself is annoying.  Now, we
do:

   render RT write SIMD16 LastRT Surface = 0 mlen 8 rlen 0

with optional "Hi" and "WriteCommit" for slot group/write commit.

Thanks to the new brw_inst API, we can also stop duplicating code on a
per-generation basis.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Kristian Høgsberg <krh@bitplanet.net>

i965/disasm: Rename msg_target to SFID.

We haven't used the name "message target" in a while - there are a lot
of things called "target", and it gets confusing.  SFID ("Shared
Function ID") is the term commonly used in the modern documentation.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Kristian Høgsberg <krh@bitplanet.net>

i965/disasm: Fix typo in RT UNORM write message.

The name of this message is "Render Target UNORM Write" (Sandybridge
PRM, Volume 4 Part 1, Page 210).  Drop the bogus 'c'.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Kristian Høgsberg <krh@bitplanet.net>

i965/disasm: Use Gen6+ SFID case labels.

Most developers will recognize the Gen6+ SFID names more quickly than
the Gen4-5 ones.  Given that they're the same values, just use the new
names.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Kristian Høgsberg <krh@bitplanet.net>

i965/disasm: "Handle" Gen8+ HF/DF immediate cases.

We should print something properly, but I'm not sure how to properly
print an HF, and we don't have any DFs today to test with.

This is at least better than the current Gen8 disassembler, which would
simply assert fail.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Matt Turner <mattst88@gmail.com>

i965/disasm: Cut piles of duplicate swizzle printing.

Making a helper function saves us from cut and pasting this four times.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Kristian Høgsberg <krh@bitplanet.net>

i965/disasm: Properly decode negate source modifiers on Broadwell.

This is a port of Abdiel's 6f9f916b9b042a294813ab0542390846a38739da
to brw_disasm.c.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Kristian Høgsberg <krh@bitplanet.net>

i965/disasm: Improve disassembly of atomic messages on Haswell+.

This backports the atomic message disassembly support from
gen8_disasm.c, which additionally offers support for decoding atomic
surface read/write messages, and showing SIMD modes and other details.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Kristian Høgsberg <krh@bitplanet.net>

i965/disasm: Actually disassemble Gen7+ URB opcodes.

I never bothered implementing the disassembler for Gen7+ URB opcodes, so
we were just disassembling them as Ironlake/Sandybridge ones.  This
looked pretty bad when running Paul's GS EndPrimitive tests, as the
"write OWord" message was decoded at ff_sync, which doesn't exist.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Kristian Høgsberg <krh@bitplanet.net>

i965/disasm: Decode Broadwell's invm/rsqrtm math functions.

We don't use these yet, but we may as well disassemble them.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Kristian Høgsberg <krh@bitplanet.net>

i965/disasm: Properly disassemble the "atomic" ThreadCtrl value.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Kristian Høgsberg <krh@bitplanet.net>

i965/disasm: Properly disassemble all32h/any32h align1 predicates.

While we're adding things, use symbolic constants rather than magic
numbers.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Kristian Høgsberg <krh@bitplanet.net>

i965: Add #defines for any32h/all32h predication.

These have existed since Ivybridge.  We don't use them today, but the
Gen8+ disassembler supports them, and I'd like to use symbolic names
rather than magic numbers.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Kristian Høgsberg <krh@bitplanet.net>

i965/disasm: Mark ELSE as having UIP on Gen8+.

This makes brw_disasm.c able to disassemble ELSE instructions correctly
on Broadwell.  (gen8_disasm.c already handles this correctly.)

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Kristian Høgsberg <krh@bitplanet.net>

i965/disasm: Properly disassemble jump targets on Gen4-5.

Previously, our dissasembly for flow control instructions looked like:

0x00000040: else(8)         ip          65540D     { align16 switch };

It didn't print InstCount properly for ELSE/ENDIF, and didn't even
attempt to disassemble PopCount.

Now it looks like:

0x00000040: else(8)         Jump: 4     Pop: 1     { align16 switch };

which is much more readable.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Kristian Høgsberg <krh@bitplanet.net>

i965/disasm: Improve disassembly of jump targets on Gen6+.

Previously, flow control instructions generated output like:

(+f0) if(8) 12 8  null         0x000c0008UD { align16 WE_normal 1Q };

which included a dissasembly of the register fields, even though those
are meaningless for flow control instructions---those bits are reused
for another purpose.

It also wasn't immediately obvious which number was UIP and which was
JIP.

With this patch, we instead output:

(+f0) if(8)       JIP: 8       UIP: 12      { align16 WE_normal 1Q };

which is much clearer.

The patch also introduces has_uip/has_jip helper functions which clear
up a some generation/opcode checking mess.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Kristian Høgsberg <krh@bitplanet.net>

i965/disasm: Add support for new Gen8+ register types.

While we're at it, use proper names rather than magic numbers for the
existing fields.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Kristian Høgsberg <krh@bitplanet.net>

i965: Restyle brw_disasm.c.

brw_disasm.c basically wasn't following the Mesa coding style at all.
It used 4-space indent instead of 3-space, didn't cuddle braces, didn't
put function return types on a separate line, put extra spaces in
function calls (between the name and parenthesis), and a number of other
things.

This made it fairly obnoxious to work on, since my editor is configured
to follow Mesa style in the Mesa source repository.  Fixing it to follow
a consistent style now should save time dealing with it later.

These modifications were originally generated by:
$ indent -br -i3 -npcs -ce -cs -l80 --no-tabs
with some manual changes afterwards to fit our style better.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Kristian Høgsberg <krh@bitplanet.net>

i965/disasm: Create an "opcode" temporary.

This saves typing brw_inst_opcode(brw, inst) everywhere.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Kristian Høgsberg <krh@bitplanet.net>

i965/disasm: Eliminate opcode pointer.

opcode is just a pointer to opcode_descs; we may as well use that
directly.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Kristian Høgsberg <krh@bitplanet.net>

Remove the ATI_envmap_bumpmap extension

As far as I can tell, the Intel mesa driver is the only driver in the world
still supporting this legacy extension.  If someone wants to do bump
mapping, they can use shaders.

Signed-off-by: Jason Ekstrand <jason.ekstrand@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> [v1]
Reviewed-by: Chris Forbes <chrisf@ijw.co.nz> [v2]
Reviewed-by: Ian Romanick <idr@freedesktop.org> [v3]

meta: Use AMD_vertex_shader_layer instead of a GS for layered clears.

On i965, enabling and disabling the GS is not free: you have to do a
full pipeline stall, reconfigure the URB and push constant space, and
emit a bunch of state.  Most clears aren't layered, so the GS isn't
needed in the common case.  But we turned it on universally.

Using AMD_vertex_shader_layer allows us to skip setting up the GS
altogether, while achieving the same effect.

According to Ilia, current nVidia GPUs can't do AMD_vertex_shader_layer.
However, since nouveau is Gallium-based, they're unlikely to ever care
about this path.  Intel and AMD GPUs both support the extension.

Since i965 is the only driver using this path which does layered
rendering, we may as well target it at that.

v2: Improve commit message.  No code changes.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Chris Forbes <chrisf@ijw.co.nz>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>

docs: mark "Geometry shader multiple streams" as done for i965

Signed-off-by: Samuel Iglesias Gonsalvez <siglesias@igalia.com>
Reviewed-by: Chris Forbes <chrisf@ijw.co.nz>

i965: Enable vertex streams up to MAX_VERTEX_STREAMS.

Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>

mesa: Enable simultaneous queries on different streams.

It should be possible to query the number of primitives written to each
individual stream by a geometry shader in a single draw call. For that
we need to have up to MAX_VERTEX_STREAM separate query objects.

Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>

i965: Implement GL_PRIMITIVES_GENERATED with non-zero streams.

So far we have been using CL_INVOCATION_COUNT to resolve this query but this
is no good with streams, as only stream 0 reaches the clipping stage. Instead
we will use SO_PRIM_STORAGE_NEEDED which can keep track of the primitives sent
to each individual stream.

Since SO_PRIM_STORAGE_NEEDED is related to the SOL stage and according to
ARB_transform_feedback3 we need to be able to query primitives generated in
each stream whether transform feedback is active or not what we do is to
enable the SOL unit even if transform feedback is not active but disable all
output buffers in that case. This effectively disables transform feedback
but permits activation of statistics enabling SO_PRIM_STORAGE_NEEDED even
when transform feedback is not active.

Reviewed-by: Chris Forbes <chrisf@ijw.co.nz>

i965: Implement GL_TRANSFORM_FEEDBACK_PRIMITIVES_WRITTEN with non-zero streams.

Reviewed-by: Chris Forbes <chrisf@ijw.co.nz>

mesa: Include stream information in indexed queries.

Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>