litex.git
9 years agouart: support async phys
Robert Jordens [Sun, 19 Jul 2015 07:23:35 +0000 (01:23 -0600)]
uart: support async phys

9 years agouart.c: rx overflow fix and tx simplification
Robert Jordens [Sun, 19 Jul 2015 07:23:34 +0000 (01:23 -0600)]
uart.c: rx overflow fix and tx simplification

* fixes the clearing of the rx ringbuffer on rx-overflow
* removes tx_level and tx_cts by restricting the ringbuffer
  to at least one slot empty
* agnostic of the details of the tx irq: works for uarts that
  generate tx interrupts on !tx-full or on tx-empty.
* only rx_produce and tx_consume need to be volatile

9 years agobios: add romboot
Florent Kermarrec [Tue, 14 Jul 2015 15:33:24 +0000 (17:33 +0200)]
bios: add romboot

When firmware is small enough, it can be interesting to run code from an embedded blockram memory (faster and not impacted by memory controller activity).
It can also be a fallback option in case boot from flash failed.
To use this, define ROM_BOOT_ADDRESS and initialize the blockram with the firmware data.

9 years agomake.py: use sys.path.insert(0...) to allow external designs to have specific targets...
Florent Kermarrec [Mon, 13 Jul 2015 15:00:03 +0000 (17:00 +0200)]
make.py: use sys.path.insert(0...) to allow external designs to have specific targets derived from a base target

9 years agomisoclib/video/dvisampler: add fifo_depth parameter
Florent Kermarrec [Mon, 13 Jul 2015 09:03:33 +0000 (11:03 +0200)]
misoclib/video/dvisampler: add fifo_depth parameter

9 years agowishbone2lasmi: fix "READ_DATA" state
Florent Kermarrec [Tue, 7 Jul 2015 13:45:06 +0000 (15:45 +0200)]
wishbone2lasmi: fix "READ_DATA" state

9 years agotools/flterm.py: fix kernel-adr support
Florent Kermarrec [Tue, 7 Jul 2015 12:58:49 +0000 (14:58 +0200)]
tools/flterm.py: fix kernel-adr support

9 years agoliteeth/core: add with_icmp parameter
Florent Kermarrec [Mon, 6 Jul 2015 19:23:19 +0000 (21:23 +0200)]
liteeth/core: add with_icmp parameter

9 years agouse sets for leave_out
Florent Kermarrec [Sun, 5 Jul 2015 20:49:23 +0000 (22:49 +0200)]
use sets for leave_out

9 years agoliteeth/core/mac: adapt depth on AsyncFIFOs according to phy (reduce ressource usage...
Florent Kermarrec [Sun, 5 Jul 2015 20:45:53 +0000 (22:45 +0200)]
liteeth/core/mac: adapt depth on AsyncFIFOs according to phy (reduce ressource usage with MII phy)

9 years agoliteeth: small logic optimizations on mac (eases timings on spartan6)
Florent Kermarrec [Sun, 5 Jul 2015 10:31:52 +0000 (12:31 +0200)]
liteeth: small logic optimizations on mac (eases timings on spartan6)

9 years agosoftware/bios: call eth_mode only if we have an ethernet mac (we don't need to call...
Florent Kermarrec [Sat, 4 Jul 2015 19:04:23 +0000 (21:04 +0200)]
software/bios: call eth_mode only if we have an ethernet mac (we don't need to call it when we have a hardware UDP/IP stack)

9 years agobios: show memtest command in help
Yann Sionneau [Thu, 2 Jul 2015 15:19:55 +0000 (17:19 +0200)]
bios: show memtest command in help

9 years agosoc: support constants without value
Sebastien Bourdeauducq [Sun, 28 Jun 2015 19:35:37 +0000 (21:35 +0200)]
soc: support constants without value

9 years agolibcompiler-rt: add fixdfdi
Sebastien Bourdeauducq [Sat, 27 Jun 2015 21:51:09 +0000 (23:51 +0200)]
libcompiler-rt: add fixdfdi

9 years agoflterm.py: use serial_for_url
Joe Britton [Fri, 26 Jun 2015 09:40:18 +0000 (11:40 +0200)]
flterm.py: use serial_for_url

9 years agolitesata/example_designs: fix core generation (RAID introduced some changes on the...
Florent Kermarrec [Thu, 25 Jun 2015 22:20:58 +0000 (00:20 +0200)]
litesata/example_designs: fix core generation (RAID introduced some changes on the PHY)

9 years agoMerge pull request #14 from olofk/misc_fixes
enjoy-digital [Thu, 25 Jun 2015 21:59:42 +0000 (23:59 +0200)]
Merge pull request #14 from olofk/misc_fixes

Misc fixes

9 years agolitesata/test: Add missing dependency on scrambler in bist_tb
Olof Kindgren [Thu, 25 Jun 2015 23:16:35 +0000 (01:16 +0200)]
litesata/test: Add missing dependency on scrambler in bist_tb

9 years agolitesata/example_designs: Add missing clock in phy instantiation
Olof Kindgren [Thu, 25 Jun 2015 23:15:34 +0000 (01:15 +0200)]
litesata/example_designs: Add missing clock in phy instantiation

9 years agoliteeth/example_designs: use new Keep SynthesisDirective
Florent Kermarrec [Tue, 23 Jun 2015 14:15:28 +0000 (16:15 +0200)]
liteeth/example_designs: use new Keep SynthesisDirective

9 years agosoftware/bios/sdram: flush dcache and l2 in memtest (otherwise we are partially testi...
Florent Kermarrec [Tue, 23 Jun 2015 07:01:34 +0000 (09:01 +0200)]
software/bios/sdram: flush dcache and l2 in memtest (otherwise we are partially testing the cache)

9 years agopipistrello: run at 83+1/3 MHz, cleanup CRG
Robert Jordens [Tue, 23 Jun 2015 00:48:31 +0000 (18:48 -0600)]
pipistrello: run at 83+1/3 MHz, cleanup CRG

9 years agoliteeth/software: fix wishbone bridge
Florent Kermarrec [Mon, 22 Jun 2015 22:53:31 +0000 (00:53 +0200)]
liteeth/software: fix wishbone bridge

9 years agoliteeth/example_designs: add false path between clock domains (speed up implementatio...
Florent Kermarrec [Mon, 22 Jun 2015 22:37:31 +0000 (00:37 +0200)]
liteeth/example_designs: add false path between clock domains (speed up implementation) and use automatic PHY detection

9 years agoliteeth/core/arp: fix table timer (wait_timer adaptation issue)
Florent Kermarrec [Mon, 22 Jun 2015 22:25:26 +0000 (00:25 +0200)]
liteeth/core/arp: fix table timer (wait_timer adaptation issue)

9 years agoliteeth/core/arp: fix missing MAC address in ARP reply
Florent Kermarrec [Mon, 22 Jun 2015 21:15:00 +0000 (23:15 +0200)]
liteeth/core/arp: fix missing MAC address in ARP reply

9 years agosoftware/libbase/system: fix flush_l2_cache
Florent Kermarrec [Fri, 19 Jun 2015 07:00:14 +0000 (09:00 +0200)]
software/libbase/system: fix flush_l2_cache

9 years agosoc/sdram: add L2_SIZE constant and avoid declaring an empty flush_l2_cache function...
Florent Kermarrec [Fri, 19 Jun 2015 06:39:37 +0000 (08:39 +0200)]
soc/sdram: add L2_SIZE constant and avoid declaring an empty flush_l2_cache function when L2_SIZE is not defined

9 years agoindentation
Sebastien Bourdeauducq [Wed, 17 Jun 2015 14:32:17 +0000 (08:32 -0600)]
indentation

9 years agosoc/sdram: add capability to share L2 cache in multi-CPU SoCs
Florent Kermarrec [Wed, 17 Jun 2015 12:52:30 +0000 (14:52 +0200)]
soc/sdram: add capability to share L2 cache in multi-CPU SoCs

9 years agosdram: use wishbone cache as L2 cache and add optional L2 cache to Minicon
Florent Kermarrec [Tue, 16 Jun 2015 17:06:24 +0000 (19:06 +0200)]
sdram: use wishbone cache as L2 cache and add optional L2 cache to Minicon

9 years agolitesata: use 200MHz clock and SATA3 (6.0Gb/s) on all example designs: working :)
Florent Kermarrec [Wed, 10 Jun 2015 10:15:59 +0000 (12:15 +0200)]
litesata: use 200MHz clock and SATA3 (6.0Gb/s) on all example designs: working :)

9 years agolitesata/phy/k7: apply AR# 63869 to keep CDR in hold during SATA link initialization
Florent Kermarrec [Wed, 10 Jun 2015 10:14:48 +0000 (12:14 +0200)]
litesata/phy/k7: apply AR# 63869 to keep CDR in hold during SATA link initialization

self.rxelecidle is already filtered so the "20 USRCLK cycles before setting RXCDRHOLD to 1'b0" are respected.

9 years agosdram: use new Migen Converter in Minicon frontend and small cleanup
Florent Kermarrec [Tue, 2 Jun 2015 17:35:00 +0000 (19:35 +0200)]
sdram: use new Migen Converter in Minicon frontend and small cleanup

9 years agosdram/phy: fix simphy memory usage
Florent Kermarrec [Tue, 2 Jun 2015 17:33:09 +0000 (19:33 +0200)]
sdram/phy: fix simphy memory usage

9 years agosdram: refactor minicon and fix issues with DDRx memories
Florent Kermarrec [Fri, 29 May 2015 10:26:34 +0000 (12:26 +0200)]
sdram: refactor minicon and fix issues with DDRx memories

- simplify code
- fix AddressSlicer
- manage write latency and write to precharge timings
- add odt/reset_n signals

9 years agospiflash: now using 64k sectors
Yann Sionneau [Fri, 15 May 2015 09:03:02 +0000 (11:03 +0200)]
spiflash: now using 64k sectors

9 years agospiflash: cleanup unnecessary parenthesis
Yann Sionneau [Fri, 15 May 2015 09:02:16 +0000 (11:02 +0200)]
spiflash: cleanup unnecessary parenthesis

9 years agolitesata: more doc fixes
Sebastien Bourdeauducq [Tue, 26 May 2015 06:13:13 +0000 (14:13 +0800)]
litesata: more doc fixes

9 years agoMerge branch 'master' of https://github.com/m-labs/misoc
Sebastien Bourdeauducq [Tue, 26 May 2015 05:57:26 +0000 (13:57 +0800)]
Merge branch 'master' of https://github.com/m-labs/misoc

Conflicts:
misoclib/mem/litesata/doc/source/docs/frontend/index.rst

9 years agolitesata: doc fixes
Sebastien Bourdeauducq [Tue, 26 May 2015 05:54:31 +0000 (13:54 +0800)]
litesata: doc fixes

9 years agoliteata: fix spelling & mistakes in doc
Florent Kermarrec [Tue, 26 May 2015 05:37:09 +0000 (07:37 +0200)]
liteata: fix spelling & mistakes in doc

9 years agolitesata: rework frontend doc and add striping, mirroring
Florent Kermarrec [Mon, 25 May 2015 12:04:37 +0000 (14:04 +0200)]
litesata: rework frontend doc and add striping, mirroring

9 years agolitesata: add mirroring
Florent Kermarrec [Mon, 25 May 2015 12:03:14 +0000 (14:03 +0200)]
litesata: add mirroring

9 years agolitesata/examples_designs: add striping
Florent Kermarrec [Mon, 25 May 2015 11:57:27 +0000 (13:57 +0200)]
litesata/examples_designs: add striping

9 years agolitesata/core/link: move buffer on CONTInserter (seems better for timings when set...
Florent Kermarrec [Mon, 25 May 2015 11:55:15 +0000 (13:55 +0200)]
litesata/core/link: move buffer on CONTInserter (seems better for timings when set on sink)

9 years agoliteusb/core/packet: fix missing ,
Florent Kermarrec [Mon, 25 May 2015 11:53:02 +0000 (13:53 +0200)]
liteusb/core/packet: fix missing ,

9 years agolitesata: add striping module for use of multiple HDDs.
Florent Kermarrec [Sat, 23 May 2015 12:12:20 +0000 (14:12 +0200)]
litesata: add striping module for use of multiple HDDs.

9 years agolitesata: do some cleanup and prepare for RAID
Florent Kermarrec [Sat, 23 May 2015 12:08:56 +0000 (14:08 +0200)]
litesata: do some cleanup and prepare for RAID

9 years agocores: replace Timeout with new WaitTimer
Florent Kermarrec [Tue, 12 May 2015 13:49:20 +0000 (15:49 +0200)]
cores: replace Timeout with new WaitTimer

9 years agouart: rename wishbone to bridge
Florent Kermarrec [Sat, 9 May 2015 14:24:28 +0000 (16:24 +0200)]
uart: rename wishbone to bridge

9 years agouart: remove litescope dependency for UARTWishboneBridge and remove frontend
Florent Kermarrec [Sat, 9 May 2015 13:48:54 +0000 (15:48 +0200)]
uart: remove litescope dependency for UARTWishboneBridge and remove frontend

9 years agoliteusb/frontend/dma: remove +4 to length for CRC (we'll do it in core)
Florent Kermarrec [Thu, 7 May 2015 18:03:55 +0000 (20:03 +0200)]
liteusb/frontend/dma: remove +4 to length for CRC (we'll do it in core)

9 years agoliteusb/phy/ft245: rename "ftdi" clock domain to "usb"
Florent Kermarrec [Thu, 7 May 2015 18:03:12 +0000 (20:03 +0200)]
liteusb/phy/ft245: rename "ftdi" clock domain to "usb"

9 years agolitesata: fix packets figure in frontend doc
Florent Kermarrec [Thu, 7 May 2015 09:06:05 +0000 (11:06 +0200)]
litesata: fix packets figure in frontend doc

9 years agoREADME: add note about submodules
Sebastien Bourdeauducq [Thu, 7 May 2015 08:29:30 +0000 (16:29 +0800)]
README: add note about submodules

9 years agolitesata: add doc for frontend
Florent Kermarrec [Wed, 6 May 2015 01:51:02 +0000 (03:51 +0200)]
litesata: add doc for frontend

9 years agolitesata: cleanup README/doc
Florent Kermarrec [Wed, 6 May 2015 00:02:22 +0000 (02:02 +0200)]
litesata: cleanup README/doc

9 years agolitesata: use (some) settings from vivado 2015.1, try to follow all ug476 recommendat...
Florent Kermarrec [Tue, 5 May 2015 23:33:02 +0000 (01:33 +0200)]
litesata: use (some) settings from vivado 2015.1, try to follow all ug476 recommendations to initialize GTX (...), remove automatic reset on top.

Works fine @ 3Gbps, still not working @6.0Gbps

9 years agospiflash: fix miso bitbang with large DQ
Sebastien Bourdeauducq [Tue, 5 May 2015 16:05:25 +0000 (00:05 +0800)]
spiflash: fix miso bitbang with large DQ

9 years agosoc/sdram: Vivado 2015.1 still does not fix issue with L2 cache, update comment...
Florent Kermarrec [Mon, 4 May 2015 10:28:49 +0000 (12:28 +0200)]
soc/sdram: Vivado 2015.1 still does not fix issue with L2 cache, update comment...

9 years agomisoclib/cpu: merge git.py in identifier
Florent Kermarrec [Sat, 2 May 2015 16:42:33 +0000 (18:42 +0200)]
misoclib/cpu: merge git.py in identifier

9 years agoliteusb: add simple example design with wishbone bridge and software to control it
Florent Kermarrec [Sat, 2 May 2015 15:39:22 +0000 (17:39 +0200)]
liteusb: add simple example design with wishbone bridge and software to control it

9 years agorename shadow_address to shadow_base (more appropriate) and use | instead of + (as...
Florent Kermarrec [Sat, 2 May 2015 14:57:32 +0000 (16:57 +0200)]
rename shadow_address to shadow_base (more appropriate) and use | instead of + (as done in artiq)

9 years agoliteeth/core/mac: minor cleanup
Florent Kermarrec [Sat, 2 May 2015 14:48:57 +0000 (16:48 +0200)]
liteeth/core/mac: minor cleanup

9 years agoliteusb/frontend/wishbone: use new packetized mode (allow grouping response in a...
Florent Kermarrec [Sat, 2 May 2015 14:15:58 +0000 (16:15 +0200)]
liteusb/frontend/wishbone: use new packetized mode (allow grouping response in a single packet)

9 years agolitescope/frontend/wishbone: add support for packetized mode
Florent Kermarrec [Sat, 2 May 2015 14:15:08 +0000 (16:15 +0200)]
litescope/frontend/wishbone: add support for packetized mode

9 years agoliteusb/software/wishbone: optimize writes/reads (send a single packet for a command)
Florent Kermarrec [Sat, 2 May 2015 13:25:40 +0000 (15:25 +0200)]
liteusb/software/wishbone: optimize writes/reads (send a single packet for a command)

9 years agodo more test with last changes fix small issues
Florent Kermarrec [Sat, 2 May 2015 12:26:19 +0000 (14:26 +0200)]
do more test with last changes fix small issues

9 years agoliteeth: move mac to core
Florent Kermarrec [Sat, 2 May 2015 10:55:51 +0000 (12:55 +0200)]
liteeth: move mac to core

9 years agocores: avoid having too much directories when possible (for simple cores or cores...
Florent Kermarrec [Sat, 2 May 2015 09:14:55 +0000 (11:14 +0200)]
cores: avoid having too much directories when possible (for simple cores or cores contained in a single file)

9 years agouse similar names for wishbone bridges and move wishbone drivers to [core]/software
Florent Kermarrec [Sat, 2 May 2015 08:24:56 +0000 (10:24 +0200)]
use similar names for wishbone bridges and move wishbone drivers to [core]/software

9 years agotargets/pipistrello: add flash sizes
Zach Smith [Fri, 1 May 2015 18:41:37 +0000 (14:41 -0400)]
targets/pipistrello: add flash sizes

9 years agolitescope: add basic LiteScopeUSB2WishboneFTDIDriver (working but need to be optimized)
Florent Kermarrec [Fri, 1 May 2015 18:33:56 +0000 (20:33 +0200)]
litescope: add basic LiteScopeUSB2WishboneFTDIDriver (working but need to be optimized)

9 years agolitescope: rename host directory to software (to be coherent with others cores)
Florent Kermarrec [Fri, 1 May 2015 18:27:31 +0000 (20:27 +0200)]
litescope: rename host directory to software (to be coherent with others cores)

9 years agoliteusb: add basic wishbone frontend (We could also reuse Etherbone in the future)
Florent Kermarrec [Fri, 1 May 2015 18:20:20 +0000 (20:20 +0200)]
liteusb: add basic wishbone frontend (We could also reuse Etherbone in the future)

9 years agolitescope: fix missing source ack on LiteScopeWishboneBridge
Florent Kermarrec [Fri, 1 May 2015 18:19:49 +0000 (20:19 +0200)]
litescope: fix missing source ack on LiteScopeWishboneBridge

9 years agolitescope/bridge: create a generic wishbone bridge that can be used with different...
Florent Kermarrec [Fri, 1 May 2015 15:42:00 +0000 (17:42 +0200)]
litescope/bridge: create a generic wishbone bridge that can be used with different phys (the phy needs to provide a sink/source with 8bits data).

- we can now pass a phy to LiteScopeWishboneBridge
- LiteScopeUART2Wishbone is only a specific LiteScopeWishboneBridge
- UART mux is removed since complicated and no longer useful (we can now create easily virtual UART over Ethernet, USB or PCIe) or simply add another UART for debug.

9 years agolitescope: use full name in io.py
Florent Kermarrec [Fri, 1 May 2015 15:23:44 +0000 (17:23 +0200)]
litescope: use full name in io.py

9 years agotargets/minispartan6: add USBSoC (working, should also be usable on pipistrello)
Florent Kermarrec [Fri, 1 May 2015 14:16:48 +0000 (16:16 +0200)]
targets/minispartan6: add USBSoC (working, should also be usable on pipistrello)

9 years agoliteusb: refactor software (use python instead of libftdicom in C) and provide simple...
Florent Kermarrec [Fri, 1 May 2015 14:15:15 +0000 (16:15 +0200)]
liteusb: refactor software (use python instead of libftdicom in C) and provide simple example.

small modifications to fastftdi.c are also done to select our interface (A or B) and mode (synchronous, asynchronous)

9 years agoliteusb: continue refactoring (virtual UART and DMA working on minispartan6)
Florent Kermarrec [Fri, 1 May 2015 14:11:15 +0000 (16:11 +0200)]
liteusb: continue refactoring (virtual UART and DMA working on minispartan6)

- rename ft2232h phy to ft245.
- make crc optional
- fix depacketizer
- refactor uart (it's now only a wrapper around standard UART)
- fix and update dma

9 years agocom/uart: add tx and rx fifos.
Florent Kermarrec [Fri, 1 May 2015 13:58:10 +0000 (15:58 +0200)]
com/uart: add tx and rx fifos.

Since ressource usage is low with default depth of 16 (implemented in RAM LUTs) we don't keep old behaviour.
Tested successfully with BIOS and flterm.

9 years agoliteusb: add ft2232h_sync_tb
Florent Kermarrec [Tue, 28 Apr 2015 17:05:34 +0000 (19:05 +0200)]
liteusb: add ft2232h_sync_tb

9 years agoliteusb: add FT2232HPHYAsynchronous PHY (Minispartan6+, Pipistrello), needs more...
Florent Kermarrec [Tue, 28 Apr 2015 17:00:13 +0000 (19:00 +0200)]
liteusb: add FT2232HPHYAsynchronous PHY (Minispartan6+, Pipistrello), needs more simulations and on-board tests

9 years agoliteusb: continue refactoring and add core_tb (should be almost OK)
Florent Kermarrec [Tue, 28 Apr 2015 16:58:38 +0000 (18:58 +0200)]
liteusb: continue refactoring and add core_tb (should be almost OK)

9 years agomisoclib/com/uart: remove liteeth dependency (copy/paste error)
Florent Kermarrec [Tue, 28 Apr 2015 16:53:46 +0000 (18:53 +0200)]
misoclib/com/uart: remove liteeth dependency (copy/paste error)

9 years agoliteeth: use Migen's Packetizer/Depacketizer, remove generic and move etherbone/tty...
Florent Kermarrec [Tue, 28 Apr 2015 16:51:40 +0000 (18:51 +0200)]
liteeth: use Migen's Packetizer/Depacketizer, remove generic and move etherbone/tty to frontend

9 years agolitesata: cleanup link
Florent Kermarrec [Mon, 27 Apr 2015 13:33:01 +0000 (15:33 +0200)]
litesata: cleanup link

9 years agoMerge branch 'master' of https://github.com/m-labs/misoc
Florent Kermarrec [Mon, 27 Apr 2015 13:28:08 +0000 (15:28 +0200)]
Merge branch 'master' of https://github.com/m-labs/misoc

9 years agoliteusb: begin refactoring and simplification (wip)
Florent Kermarrec [Mon, 27 Apr 2015 13:19:54 +0000 (15:19 +0200)]
liteusb: begin refactoring and simplification (wip)

9 years agoliteeth: use new Migen modules from actorlib (avoid duplications between cores)
Florent Kermarrec [Mon, 27 Apr 2015 13:06:37 +0000 (15:06 +0200)]
liteeth: use new Migen modules from actorlib (avoid duplications between cores)

9 years agolitepcie: use new Migen modules from actorlib (avoid duplications between cores)
Florent Kermarrec [Mon, 27 Apr 2015 12:59:29 +0000 (14:59 +0200)]
litepcie: use new Migen modules from actorlib (avoid duplications between cores)

9 years agolitesata: split hdd model (phy, link, transport, command & hdd) and update simulations
Florent Kermarrec [Mon, 27 Apr 2015 12:50:43 +0000 (14:50 +0200)]
litesata: split hdd model (phy, link, transport, command & hdd) and update simulations

9 years agolitesata: use new Migen modules from actorlib/packet.py (avoid duplications between...
Florent Kermarrec [Mon, 27 Apr 2015 12:48:14 +0000 (14:48 +0200)]
litesata: use new Migen modules from actorlib/packet.py (avoid duplications between cores)

9 years agolitesata: remove icarus_workaround.patch (obsolete)
Florent Kermarrec [Mon, 27 Apr 2015 12:44:54 +0000 (14:44 +0200)]
litesata: remove icarus_workaround.patch (obsolete)

9 years agospiflash: use SoC defines, add write_to_flash function
Sebastien Bourdeauducq [Mon, 27 Apr 2015 05:42:32 +0000 (13:42 +0800)]
spiflash: use SoC defines, add write_to_flash function

9 years agoliteeth: do MII/GMII detection in gateware for gmii_mii phy
Florent Kermarrec [Sun, 26 Apr 2015 15:32:25 +0000 (17:32 +0200)]
liteeth: do MII/GMII detection in gateware for gmii_mii phy

9 years agoliteeth/phy/gmii: add default value for pads_register
Florent Kermarrec [Sun, 26 Apr 2015 12:52:05 +0000 (14:52 +0200)]
liteeth/phy/gmii: add default value for pads_register