Gabe Black [Sun, 15 Apr 2012 19:35:49 +0000 (12:35 -0700)]
CPU: Tidy up some formatting and a DPRINTF in the simple CPU base class.
Put the { on the same line as the if and put a space between the if and the
open paren. Also, use the # format modifier which puts a 0x in front of hex
values automatically. If the ExtMachInst type isn't integral and actually
prints something more complicated, the # falls away harmlessly and we aren't
left with a phantom 0x followed by a bunch of unrelated text.
Gabe Black [Sun, 15 Apr 2012 08:07:39 +0000 (01:07 -0700)]
X86: Fix a tiny typo in the load/store microop constructor.
The parameter is _machInst, which is very similar to the member machInst. If
machInst is used to pass the parameter to a lower level constructor, what
really happens is that machInst is set to whatever it already happened to be,
effectively leaving it uninitialized.
Gabe Black [Sun, 15 Apr 2012 06:24:18 +0000 (23:24 -0700)]
X86: Use the AddrTrie class to implement the TLB.
This change also adjusts the TlbEntry class so that it stores the number of
address bits wide a page is rather than its size in bytes. In other words,
instead of storing 4K for a 4K page, it stores 12. 12 is easy to turn into 4K,
but it's a little harder going the other way.
Gabe Black [Sun, 15 Apr 2012 06:22:57 +0000 (23:22 -0700)]
sim: Update some comments in trie.hh that were meant to go in the last change.
Gabe Black [Sun, 15 Apr 2012 06:19:34 +0000 (23:19 -0700)]
sim: A trie data structure specifically to speed up paging lookups.
This change adds a trie data structure which stores an arbitrary pointer type
based on an address and a number of relevant bits. Then lookups can be done
against the trie where the tree is traversed and the first legitimate match
found is returned.
Andreas Hansson [Sat, 14 Apr 2012 09:46:59 +0000 (05:46 -0400)]
Ruby: Use MasterPort base-class pointers where possible
This patch simplifies future patches by changing the pointer type used
in a number of the Ruby testers to use MasterPort instead of using a
derived CpuPort class. There is no reason for using the more
specialised pointers, and there is no longer a need to do any casting.
With the latest changes to the tester, organising ports as readers and
writes, things got a bit more complicated, and the "type" now had to
be removed to be able to fall back to using MasterPort rather than
CpuPort.
Andreas Hansson [Sat, 14 Apr 2012 09:45:55 +0000 (05:45 -0400)]
MEM: Remove the Broadcast destination from the packet
This patch simplifies the packet by removing the broadcast flag and
instead more firmly relying on (and enforcing) the semantics of
transactions in the classic memory system, i.e. request packets are
routed from a master to a slave based on the address, and when they
are created they have neither a valid source, nor destination. On
their way to the slave, the request packet is updated with a source
field for all modules that multiplex packets from multiple master
(e.g. a bus). When a request packet is turned into a response packet
(at the final slave), it moves the potentially populated source field
to the destination field, and the response packet is routed through
any multiplexing components back to the master based on the
destination field.
Modules that connect multiplexing components, such as caches and
bridges store any existing source and destination field in the sender
state as a stack (just as before).
The packet constructor is simplified in that there is no longer a need
to pass the Packet::Broadcast as the destination (this was always the
case for the classic memory system). In the case of Ruby, rather than
using the parameter to the constructor we now rely on setDest, as
there is already another three-argument constructor in the packet
class.
In many places where the packet information was printed as part of
DPRINTFs, request packets would be printed with a numeric "dest" that
would always be -1 (Broadcast) and that field is now removed from the
printing.
Andreas Hansson [Sat, 14 Apr 2012 09:45:07 +0000 (05:45 -0400)]
MEM: Separate snoops and normal memory requests/responses
This patch introduces port access methods that separates snoop
request/responses from normal memory request/responses. The
differentiation is made for functional, atomic and timing accesses and
builds on the introduction of master and slave ports.
Before the introduction of this patch, the packets belonging to the
different phases of the protocol (request -> [forwarded snoop request
-> snoop response]* -> response) all use the same port access
functions, even though the snoop packets flow in the opposite
direction to the normal packet. That is, a coherent master sends
normal request and receives responses, but receives snoop requests and
sends snoop responses (vice versa for the slave). These two distinct
phases now use different access functions, as described below.
Starting with the functional access, a master sends a request to a
slave through sendFunctional, and the request packet is turned into a
response before the call returns. In a system without cache coherence,
this is all that is needed from the functional interface. For the
cache-coherent scenario, a slave also sends snoop requests to coherent
masters through sendFunctionalSnoop, with responses returned within
the same packet pointer. This is currently used by the bus and caches,
and the LSQ of the O3 CPU. The send/recvFunctional and
send/recvFunctionalSnoop are moved from the Port super class to the
appropriate subclass.
Atomic accesses follow the same flow as functional accesses, with
request being sent from master to slave through sendAtomic. In the
case of cache-coherent ports, a slave can send snoop requests to a
master through sendAtomicSnoop. Just as for the functional access
methods, the atomic send and receive member functions are moved to the
appropriate subclasses.
The timing access methods are different from the functional and atomic
in that requests and responses are separated in time and
send/recvTiming are used for both directions. Hence, a master uses
sendTiming to send a request to a slave, and a slave uses sendTiming
to send a response back to a master, at a later point in time. Snoop
requests and responses travel in the opposite direction, similar to
what happens in functional and atomic accesses. With the introduction
of this patch, it is possible to determine the direction of packets in
the bus, and no longer necessary to look for both a master and a slave
port with the requested port id.
In contrast to the normal recvFunctional, recvAtomic and recvTiming
that are pure virtual functions, the recvFunctionalSnoop,
recvAtomicSnoop and recvTimingSnoop have a default implementation that
calls panic. This is to allow non-coherent master and slave ports to
not implement these functions.
Andreas Hansson [Sat, 14 Apr 2012 09:44:27 +0000 (05:44 -0400)]
Regression: Add ANSI colours to highlight test status
This patch adds a very basic pretty-printing of the test status
(passed or failed) to highlight failing tests even more: green for
passed, and red for failed. The printing only uses ANSI it the target
output is a tty and supports ANSI colours. Hence, any regression
scripts that are outputting to files or sending e-mails etc should
still be fine.
Andreas Hansson [Sat, 14 Apr 2012 09:43:31 +0000 (05:43 -0400)]
clang/gcc: Fix compilation issues with clang 3.0 and gcc 4.6
This patch addresses a number of minor issues that cause problems when
compiling with clang >= 3.0 and gcc >= 4.6. Most importantly, it
avoids using the deprecated ext/hash_map and instead uses
unordered_map (and similarly so for the hash_set). To make use of the
new STL containers, g++ and clang has to be invoked with "-std=c++0x",
and this is now added for all gcc versions >= 4.6, and for clang >=
3.0. For gcc >= 4.3 and <= 4.5 and clang <= 3.0 we use the tr1
unordered_map to avoid the deprecation warning.
The addition of c++0x in turn causes a few problems, as the
compiler is more stringent and adds a number of new warnings. Below,
the most important issues are enumerated:
1) the use of namespaces is more strict, e.g. for isnan, and all
headers opening the entire namespace std are now fixed.
2) another other issue caused by the more stringent compiler is the
narrowing of the embedded python, which used to be a char array,
and is now unsigned char since there were values larger than 128.
3) a particularly odd issue that arose with the new c++0x behaviour is
found in range.hh, where the operator< causes gcc to complain about
the template type parsing (the "<" is interpreted as the beginning
of a template argument), and the problem seems to be related to the
begin/end members introduced for the range-type iteration, which is
a new feature in c++11.
As a minor update, this patch also fixes the build flags for the clang
debug target that used to be shared with gcc and incorrectly use
"-ggdb".
Steve Reinhardt [Fri, 13 Apr 2012 15:13:04 +0000 (08:13 -0700)]
SCons: restore Werror option in src/SConscript
Partial backout of cset
8b223e308b08.
Although it's great that there's currently no need
for Werror=false in the current tree, some of us
have uncommitted code that still needs this option.
Andreas Hansson [Thu, 12 Apr 2012 12:35:56 +0000 (08:35 -0400)]
Stats: Update with use of std::map for ordered iteration in Ruby
This patch updates the stats to reflect the changes due to the use of
std::map instead of the hash map order-dependent iteration in Ruby.
Andreas Hansson [Thu, 12 Apr 2012 12:35:49 +0000 (08:35 -0400)]
Ruby: Ensure order-dependent iteration uses an ordered map
This patch fixes a bug in Ruby that caused non-deterministic
simulation when changing the underlying hash map implementation. The
reason is order-dependent behaviour in combination with iteration over
the hash map contents. The two locations where a sorted container is
assumed are now changed to make use of a std::map instead of the
unordered hash map.
With this change, the stats changes slightly and the follow-on
changeset will update the relevant statistics.
Gabe Black [Tue, 10 Apr 2012 06:20:30 +0000 (23:20 -0700)]
tests: Fix building unit tests.
Unit tests shouldn't build in gem5's main function because they have thier
own.
Brad Beckmann [Sat, 7 Apr 2012 00:51:47 +0000 (17:51 -0700)]
rubytest: remove spurious printf
Brad Beckmann [Fri, 6 Apr 2012 23:16:24 +0000 (16:16 -0700)]
regress: ruby random tester and hammer stats updates
Brad Beckmann [Fri, 6 Apr 2012 20:47:08 +0000 (13:47 -0700)]
ruby: set SimpleTiming as the default cpu
Lisa Hsu [Fri, 6 Apr 2012 20:47:08 +0000 (13:47 -0700)]
slicc: Controllers attached to Sequencers no longer have to be named L1Cache.
Brad Beckmann [Fri, 6 Apr 2012 20:47:07 +0000 (13:47 -0700)]
sim-ruby: checkpointing fixes and dependent eventq improvements
Fixes checkpointing with respect to lost events after swapping event queues.
Also adds DPRINTFs to better understand what's going on when Ruby serializes
and unserializes.
Brad Beckmann [Fri, 6 Apr 2012 20:47:07 +0000 (13:47 -0700)]
slicc: fixed error message when the type has no inheritance
Brad Beckmann [Fri, 6 Apr 2012 20:47:07 +0000 (13:47 -0700)]
MOESI_hammer: tbe allocation and dependent wakeup fixes
Brad Beckmann [Fri, 6 Apr 2012 20:47:07 +0000 (13:47 -0700)]
python: added __nonzero__ function to SimObject Bool params
Brad Beckmann [Fri, 6 Apr 2012 20:47:06 +0000 (13:47 -0700)]
MOESI_hammer: fixed bug with single cpu + flushes, then modified the regression tester to check this functionality
Brad Beckmann [Fri, 6 Apr 2012 20:47:06 +0000 (13:47 -0700)]
rubytest: seperated read and write ports.
This patch allows the ruby tester to support protocols where the i-cache and d-cache
are managed by seperate controllers.
Andreas Hansson [Fri, 6 Apr 2012 17:46:31 +0000 (13:46 -0400)]
MEM: Enable multiple distributed generalized memories
This patch removes the assumption on having on single instance of
PhysicalMemory, and enables a distributed memory where the individual
memories in the system are each responsible for a single contiguous
address range.
All memories inherit from an AbstractMemory that encompasses the basic
behaviuor of a random access memory, and provides untimed access
methods. What was previously called PhysicalMemory is now
SimpleMemory, and a subclass of AbstractMemory. All future types of
memory controllers should inherit from AbstractMemory.
To enable e.g. the atomic CPU and RubyPort to access the now
distributed memory, the system has a wrapper class, called
PhysicalMemory that is aware of all the memories in the system and
their associated address ranges. This class thus acts as an
infinitely-fast bus and performs address decoding for these "shortcut"
accesses. Each memory can specify that it should not be part of the
global address map (used e.g. by the functional memories by some
testers). Moreover, each memory can be configured to be reported to
the OS configuration table, useful for populating ATAG structures, and
any potential ACPI tables.
Checkpointing support currently assumes that all memories have the
same size and organisation when creating and resuming from the
checkpoint. A future patch will enable a more flexible
re-organisation.
--HG--
rename : src/mem/PhysicalMemory.py => src/mem/AbstractMemory.py
rename : src/mem/PhysicalMemory.py => src/mem/SimpleMemory.py
rename : src/mem/physical.cc => src/mem/abstract_mem.cc
rename : src/mem/physical.hh => src/mem/abstract_mem.hh
rename : src/mem/physical.cc => src/mem/simple_mem.cc
rename : src/mem/physical.hh => src/mem/simple_mem.hh
Tushar Krishna [Thu, 5 Apr 2012 21:51:26 +0000 (17:51 -0400)]
NetworkTest: remove unnecessary memory allocation
Nilay Vaish [Thu, 5 Apr 2012 16:09:19 +0000 (11:09 -0500)]
Config: corrects the way Ruby attaches to the DMA ports
With recent changes to the memory system, a port cannot be assigned a peer
port twice. While making use of the Ruby memory system in FS mode, DMA
ports were assigned peer twice, once for the classic memory system
and once for the Ruby memory system. This patch removes this double
assignment of peer ports.
Andreas Hansson [Thu, 5 Apr 2012 14:45:26 +0000 (10:45 -0400)]
Ruby: Fix the example configurations option parsing
This patch fixes the, currently broken, Ruby example scripts to
reflect the changes in the parsing of command-line options.
Andreas Hansson [Thu, 5 Apr 2012 14:44:35 +0000 (10:44 -0400)]
Python: Make the All proxy traverse SimObject children as well
This patch changes the behaviour of the All proxy parameter to not
only consider the direct children, but also do a pre-order depth-first
traversal of the object tree and append all results from the
children.
This is used in a later patch to find all the memories in the system,
independent of where they are located in the hierarchy.
Andreas Hansson [Tue, 3 Apr 2012 07:50:14 +0000 (03:50 -0400)]
Atomic: Remove the physmem_port and access memory directly
This patch removes the physmem_port from the Atomic CPU and instead
uses the system pointer to access the physmem when using the fastmem
option. The system already keeps track of the physmem and the valid
memory address ranges, and with this patch we merely make use of that
existing functionality. As a result of this change, the overloaded
getMasterPort in the Atomic CPU can be removed, thus unifying the CPUs.
Gabe Black [Sat, 31 Mar 2012 19:27:33 +0000 (12:27 -0700)]
X86: Fix address size handling so real mode works properly.
Virtual (pre-segmentation) addresses are truncated based on address size, and
any non-64 bit linear address is truncated to 32 bits. This means that real
mode addresses aren't truncated down to 16 bits after their segment bases are
added in.
Andreas Hansson [Fri, 30 Mar 2012 16:57:48 +0000 (12:57 -0400)]
MEM: Remove legacy DRAM in preparation for memory updates
This patch removes the DRAM memory class in preparation for updates to
the memory system, with the first one introducing an abstract memory
class, and removing the assumption of a single physical memory.
Andreas Hansson [Fri, 30 Mar 2012 13:42:36 +0000 (09:42 -0400)]
Ruby: Remove the physMemPort and instead access memory directly
This patch removes the physMemPort from the RubySequencer and instead
uses the system pointer to access the physmem. The system already
keeps track of the physmem and the valid memory address ranges, and
with this patch we merely make use of that existing functionality. The
memory is modified so that it is possible to call the access functions
(atomic and functional) without going through the port, and the memory
is allowed to be unconnected, i.e. have no ports (since Ruby does not
attach it like the conventional memory system).
William Wang [Fri, 30 Mar 2012 13:40:11 +0000 (09:40 -0400)]
MEM: Introduce the master/slave port sub-classes in C++
This patch introduces the notion of a master and slave port in the C++
code, thus bringing the previous classification from the Python
classes into the corresponding simulation objects and memory objects.
The patch enables us to classify behaviours into the two bins and add
assumptions and enfore compliance, also simplifying the two
interfaces. As a starting point, isSnooping is confined to a master
port, and getAddrRanges to slave ports. More of these specilisations
are to come in later patches.
The getPort function is not getMasterPort and getSlavePort, and
returns a port reference rather than a pointer as NULL would never be
a valid return value. The default implementation of these two
functions is placed in MemObject, and calls fatal.
The one drawback with this specific patch is that it requires some
code duplication, e.g. QueuedPort becomes QueuedMasterPort and
QueuedSlavePort, and BusPort becomes BusMasterPort and BusSlavePort
(avoiding multiple inheritance). With the later introduction of the
port interfaces, moving the functionality outside the port itself, a
lot of the duplicated code will disappear again.
Andreas Hansson [Fri, 30 Mar 2012 13:38:35 +0000 (09:38 -0400)]
CPU: Unify initMemProxies across CPUs and simulation modes
This patch unifies where initMemProxies is called, in the init()
method of each BaseCPU subclass, before TheISA::initCPU is
called. Moreover, it also ensures that initMemProxies is called in
both full-system and syscall-emulation mode, thus unifying also across
the modes. An additional check is added in the ThreadState to ensure
that initMemProxies is only called once.
Nilay Vaish [Wed, 28 Mar 2012 16:01:53 +0000 (11:01 -0500)]
Config: Change the way options are added
I am not too happy with the way options are added in files se.py and fs.py
currently. This patch moves all the options to the file Options.py, functions
from which are called when required.
Nilay Vaish [Tue, 27 Mar 2012 23:23:21 +0000 (18:23 -0500)]
Config: Move setWorkCountOptions() to Simulation.py
The function is presently defined in FSConfig.py, which does not seem to be
the correct place for it.
Andreas Hansson [Mon, 26 Mar 2012 09:37:00 +0000 (05:37 -0400)]
range_map: Enable const find and iteration
This patch adds const access functions to the range_map to enable its use
in a const context, similar to the STL container classes.
Andreas Hansson [Mon, 26 Mar 2012 09:35:24 +0000 (05:35 -0400)]
Power: Change bitfield name to avoid conflicts with range_map
This patch changes the name of a bitfield from W to W_FIELD to avoid
clashes with W being used as a class (typename) in the templatized
range_map. It also changes L to L_FIELD to avoid future problems. The
problem manifestes itself when the CPU includes a header that in turn
includes range_map.hh. The relevant parts of the decoder are updated.
Andreas Hansson [Fri, 23 Mar 2012 10:54:25 +0000 (06:54 -0400)]
Ruby: Fix Set::print for 32-bit hosts
This patch fixes a compilation error caused by a length mismatch on
32-bit hosts. The ifdef and sprintf is replaced by a csprintf.
Andreas Hansson [Thu, 22 Mar 2012 10:37:21 +0000 (06:37 -0400)]
MEM: Unify bus access methods and prepare for master/slave split
This patch unifies the recvFunctional, recvAtomic and recvTiming to
all be based on a similar structure: 1) extract information about the
incoming packet, 2) send it out to the appropriate snoopers, 3)
determine where it is going, and 4) forward it to the right
destination. The naming of variables across the different access
functions is now consistent as well.
Additionally, the patch introduces the member functions releaseBus and
retryWaiting to better distinguish between the two cases when we
should tell a sender to retry. The first case is when the bus goes
from busy to idle, and the second case is when it receives a retry
from a destination that did not immediatelly accept a packet.
As a very minor change, the MMU debug flag is no longer used in the bus.
Andreas Hansson [Thu, 22 Mar 2012 10:36:27 +0000 (06:36 -0400)]
MEM: Split SimpleTimingPort into PacketQueue and ports
This patch decouples the queueing and the port interactions to
simplify the introduction of the master and slave ports. By separating
the queueing functionality from the port itself, it becomes much
easier to distinguish between master and slave ports, and still retain
the queueing ability for both (without code duplication).
As part of the split into a PacketQueue and a port, there is now also
a hierarchy of two port classes, QueuedPort and SimpleTimingPort. The
QueuedPort is useful for ports that want to leave the packet
transmission of outgoing packets to the queue and is used by both
master and slave ports. The SimpleTimingPort inherits from the
QueuedPort and adds the implemention of recvTiming and recvFunctional
through recvAtomic.
The PioPort and MessagePort are cleaned up as part of the changes.
--HG--
rename : src/mem/tport.cc => src/mem/packet_queue.cc
rename : src/mem/tport.hh => src/mem/packet_queue.hh
Andreas Hansson [Thu, 22 Mar 2012 10:34:50 +0000 (06:34 -0400)]
Scons: Remove Werror=False in SConscript files
This patch removes the overriding of "-Werror" in a handful of
cases. The code compiles with gcc 4.6.3 and clang 3.0 without any
warnings, and thus without any errors. There are no functional changes
introduced by this patch. In the future, rather than ypassing
"-Werror", address the warnings.
Andreas Hansson [Wed, 21 Mar 2012 23:02:03 +0000 (19:02 -0400)]
Python: Fix a conditional expression that requires Python 2.5
This patch changes a conditional expression to a conventional if/else
block, which does not require Python >= 2.5.
Ali Saidi [Wed, 21 Mar 2012 15:36:45 +0000 (10:36 -0500)]
ARM: Update stats for IT and conditional branch changes
Nathanael Premillieu [Wed, 21 Mar 2012 15:34:06 +0000 (10:34 -0500)]
ARM: Fix case where cond/uncond control is mis-specified
Ali Saidi [Wed, 21 Mar 2012 15:34:06 +0000 (10:34 -0500)]
ARM: Clean up condCodes in IT blocks.
Geoffrey Blake [Wed, 21 Mar 2012 15:34:06 +0000 (10:34 -0500)]
ARM: IT doesn't need to be serializing.
Andrew Lukefahr [Wed, 21 Mar 2012 15:34:06 +0000 (10:34 -0500)]
O3: Fix sizing of decode to rename skid buffer.
Koan-Sin Tan [Wed, 21 Mar 2012 15:34:05 +0000 (10:34 -0500)]
ARM: Add RTC to PBX System
Brian Grayson [Wed, 21 Mar 2012 15:34:05 +0000 (10:34 -0500)]
O3: Fix size of skid buffer between fetch and decode when widths are different
Ali Saidi [Wed, 21 Mar 2012 15:34:05 +0000 (10:34 -0500)]
ARM: Fix uninitialized value in ARM RTC model.
Tushar Krishna [Mon, 19 Mar 2012 21:34:17 +0000 (17:34 -0400)]
Garnet: Stats at vnet granularity + code cleanup
This patch
(1) Moves redundant code from fixed and flexible networks to BaseGarnetNetwork.
(2) Prints network stats at vnet granularity.
Andreas Hansson [Mon, 19 Mar 2012 10:36:09 +0000 (06:36 -0400)]
gcc: Clean-up of non-C++0x compliant code, first steps
This patch cleans up a number of minor issues aiming to get closer to
compliance with the C++0x standard as interpreted by gcc and clang
(compile with std=c++0x and -pedantic-errors). In particular, the
patch cleans up enums where the last item was succeded by a comma,
namespaces closed by a curcly brace followed by a semi-colon, and the
use of the GNU-extension typeof (replaced by templated functions). It
does not address variable-length arrays, zero-size arrays, anonymous
structs, range expressions in switch statements, and the use of long
long. The generated CPU code also has a large number of issues that
remain to be fixed, mainly related to overflows in implicit constant
conversion (due to shifts).
Andreas Hansson [Mon, 19 Mar 2012 10:35:04 +0000 (06:35 -0400)]
clang: Fix recently introduced clang compilation errors
This patch makes the code compile with clang 2.9 and 3.0 again by
making two very minor changes. Firt, it maintains a strict typing in
the forward declaration of the BaseCPUParams. Second, it adds a
FullSystemInt flag of the type unsigned int next to the boolean
FullSystem flag. The FullSystemInt variable can be used in
decode-statements (expands to switch statements) in the instruction
decoder.
Andreas Hansson [Mon, 19 Mar 2012 10:34:02 +0000 (06:34 -0400)]
scripts: Fix to ensure that port connection count is always set
This patch ensures that the port connection count is set to zero in those
cases when the port is not connected.
Nilay Vaish [Fri, 16 Mar 2012 12:47:03 +0000 (07:47 -0500)]
ruby_fs.py: Add call to createInterruptController()
Nilay Vaish [Fri, 16 Mar 2012 12:46:45 +0000 (07:46 -0500)]
FSConfig.py: fix a typo makeLinuxAlphaRubySystem
Marc Orr [Fri, 16 Mar 2012 10:29:07 +0000 (03:29 -0700)]
build: remove implicit-cache setting of scons from recent build faster patch
Nilay Vaish [Sun, 11 Mar 2012 21:51:38 +0000 (16:51 -0500)]
se.py: Changes to ruby portion due to SE/FS merge
With the SE/FS merge, interrupt controller is created irrespective of the
mode. This patch creates the interrupt controller when Ruby is used and
connects its ports.
Brian Grayson [Sun, 11 Mar 2012 14:20:54 +0000 (10:20 -0400)]
O3: Add fatal when fetchWidth > Impl::MaxWidth.
Ali Saidi [Fri, 9 Mar 2012 21:45:47 +0000 (16:45 -0500)]
ARM: Fix memory starting at non-zero address and exceeding max mem for a system.
Ali Saidi [Fri, 9 Mar 2012 20:33:07 +0000 (15:33 -0500)]
ARM: Update stats for CBNZ fix.
Brian Grayson [Fri, 9 Mar 2012 20:32:41 +0000 (15:32 -0500)]
ARM: Fix branch prediction issue with CB(N)Z instruction
Ali Saidi [Fri, 9 Mar 2012 14:59:29 +0000 (09:59 -0500)]
ARM: Update stats for valgrind fix and replace config.inis which are out of date.
Geoffrey Blake [Fri, 9 Mar 2012 14:59:28 +0000 (09:59 -0500)]
O3/Ozone: Eliminate dead code counting software prefetch insts
Eliminates dead code in the O3 and Ozone CPU models that counted
software prefetch instructions separately for the ALPHA ISA only.
Geoffrey Blake [Fri, 9 Mar 2012 14:59:28 +0000 (09:59 -0500)]
CheckerCPU: Make some basic regression tests for CheckerCPU
Adds regression tests for the CheckerCPU. ARM ISA support
only at this point.
Geoffrey Blake [Fri, 9 Mar 2012 14:59:28 +0000 (09:59 -0500)]
CheckerCPU: Add function stubs to non-ARM ISA source to compile with CheckerCPU
Making the CheckerCPU a runtime time option requires the code to be compatible
with ISAs other than ARM. This patch adds the appropriate function
stubs to allow compilation.
Geoffrey Blake [Fri, 9 Mar 2012 14:59:27 +0000 (09:59 -0500)]
CheckerCPU: Make CheckerCPU runtime selectable instead of compile selectable
Enables the CheckerCPU to be selected at runtime with the --checker option
from the configs/example/fs.py and configs/example/se.py configuration
files. Also merges with the SE/FS changes.
Ali Saidi [Fri, 9 Mar 2012 14:59:26 +0000 (09:59 -0500)]
ARM: Don't reset CPUs that are going to be switched in.
Ali Saidi [Fri, 9 Mar 2012 14:59:26 +0000 (09:59 -0500)]
System: Move code in initState() back into constructor whenever possible.
The change to port proxies recently moved code out of the constructor into
initState(). This is needed for code that loads data into memory, however
for code that setups symbol tables, kernel based events, etc this is the wrong
thing to do as that code is only called when a checkpoint isn't being restored
from.
Ali Saidi [Fri, 9 Mar 2012 14:59:26 +0000 (09:59 -0500)]
ARM: Fix valgrind reported error on O3 that was causing minor stats changes.
Ali Saidi [Fri, 9 Mar 2012 14:59:25 +0000 (09:59 -0500)]
cache: Allow main memory to be at disjoint address ranges.
Gabe Black [Thu, 8 Mar 2012 10:10:03 +0000 (02:10 -0800)]
Fix the SPARC fs regression by adding a call to createInterruptController.
Marc Orr [Wed, 7 Mar 2012 03:07:41 +0000 (19:07 -0800)]
build scripts: Made minor modifications to reduce build overhead time.
1. --implicit-cache behavior is default.
2. makeEnv in src/SConscript is conditionally called.
3. decider set to MD5-timestamp
4. NO_HTML build option changed to SLICC_HTML (defaults to False)
Andreas Hansson [Tue, 6 Mar 2012 16:14:54 +0000 (11:14 -0500)]
Stats: Update stats for changeset 8868
Changeset 8868 slightly changes the statistics for the parser and
bzip2 regressions for ARM o3-timing. This patch merely updates the
statistics to reflect these changes.
Steve Reinhardt [Fri, 2 Mar 2012 22:05:00 +0000 (14:05 -0800)]
SConstruct: rename and document AddM5Option
Got rid of gratuitous M5 reference in the function name.
In the process, wondered why we have this function at all and
spent time trying to get rid of it and eventually firgured out
why it's needed. Put the answer in a comment so we don't have
to wonder again.
Steve Reinhardt [Fri, 2 Mar 2012 21:53:52 +0000 (13:53 -0800)]
SConstruct: update comments & doc strings
Lots of references to 'M5' still, and some to SE/FS
Steve Reinhardt [Fri, 2 Mar 2012 17:17:42 +0000 (09:17 -0800)]
DynInst: get rid of dead MyHash code.
Not sure what this was ever used for, but it
doesn't seem used anymore.
Andreas Hansson [Fri, 2 Mar 2012 14:21:48 +0000 (09:21 -0500)]
CPU: Check that the interrupt controller is created when needed
This patch adds a creation-time check to the CPU to ensure that the
interrupt controller is created for the cases where it is needed,
i.e. if the CPU is not being switched in later and not a checker CPU.
The patch also adds the "createInterruptController" call to a number
of the regression scripts.
Andreas Hansson [Fri, 2 Mar 2012 14:18:50 +0000 (09:18 -0500)]
Stats: Fix the realview regression stats after nvmem move
This patch updates the realview regressions stats to reflect that nvmem
moved in the object hierarchy and is now under system.realview.
Andreas Hansson [Fri, 2 Mar 2012 14:16:50 +0000 (09:16 -0500)]
Ruby: Rename RubyPort::sendTiming to avoid overriding base class
This patch renames the sendTiming member function in the RubyPort to
avoid inadvertently hiding Port::sendTiming (discovered through some
rather painful debugging). The RubyPort does, in fact, rely on the
functionality of the queued port and the implementation merely
schedules a send the next cycle. The new name for the member function
is sendNextCycle to better reflect this behaviour.
In the unlikely event that we ever shift to using C++11 the member
functions in Port should have a "final" identifier to prevent any
overriding in derived classes.
Ali Saidi [Fri, 2 Mar 2012 14:18:19 +0000 (08:18 -0600)]
ARM: FIx a bug preventing multiple cores booting a VExpress_EMM machine.
New kernel code verifies that multi-processor extensions are available
before booting secondary CPUs.
Ali Saidi [Fri, 2 Mar 2012 04:43:23 +0000 (22:43 -0600)]
ARM: FIx missing cf controller connection.
Chander Sudanthi [Thu, 1 Mar 2012 23:26:36 +0000 (17:26 -0600)]
VNC: spacing
Fixed some spacing in a switch statement
Ali Saidi [Thu, 1 Mar 2012 23:26:31 +0000 (17:26 -0600)]
ARM: Add support for Versatile Express extended memory map
Also clean up how we create boot loader memory a bit.
Ali Saidi [Thu, 1 Mar 2012 23:26:31 +0000 (17:26 -0600)]
ARM: Add RTC device for ARM platforms.
This change implements a PL031 real time clock.
--HG--
rename : src/dev/arm/timer_sp804.cc => src/dev/arm/rtc_pl031.cc
rename : src/dev/arm/timer_sp804.hh => src/dev/arm/rtc_pl031.hh
Matt Horsnell [Thu, 1 Mar 2012 23:26:31 +0000 (17:26 -0600)]
ARM: Add limited CP14 support.
New kernels attempt to read CP14 what debug architecture is available.
These changes add the debug registers and return that none is currently
available.
Ali Saidi [Thu, 1 Mar 2012 23:26:31 +0000 (17:26 -0600)]
Cache: Fix an issue with LRU when bonus block is used to complete transaction.
The block is never inserted because it's the one extra block in the cache, but
it can be invalidated twice in a row. In that case the block doesn't have a
new master id (beacuse it was never inserted), however it is valid and
the accounting goes wrong at that point.
Dam Sunwoo [Thu, 1 Mar 2012 23:26:31 +0000 (17:26 -0600)]
ARM: move kernel func event to correct location.
With the recent series of patches, the symbol table loading moved from
"construct" time to "init" time, but the kernel function event
callback registration was left behind. This patch moves it to the
proper location.
Giacomo Gabrielli [Thu, 1 Mar 2012 23:26:30 +0000 (17:26 -0600)]
ARM: fix bits-to-fp conversion function declarations.
Add extra declarations to allow the compiler to pick up the right function.
Please note that these declarations have been added as part of the
clang-related changes.
Nilay Vaish [Thu, 1 Mar 2012 17:37:03 +0000 (11:37 -0600)]
x86: Fix x86 TLB and Walker
This patch adds a function to X86 tlb that returns the
walker port. This port is required for correctly connecting
the walker ports for the cpu just switched in
Nilay Vaish [Thu, 1 Mar 2012 17:37:02 +0000 (11:37 -0600)]
x86: Fix switching of CPUs
This patch prevents creation of interrupt controller for
cpus that will be switched in later
Nilay Vaish [Thu, 1 Mar 2012 17:36:59 +0000 (11:36 -0600)]
Config: make option ruby available always
Andreas Hansson [Wed, 29 Feb 2012 09:47:51 +0000 (04:47 -0500)]
MEM: Make all the port proxy members const
This is a trivial patch that merely makes all the member functions of
the port proxies const. There is no good reason why they should not
be, and this change only serves to make it explicit that they are not
modified through their use.
Andreas Hansson [Wed, 29 Feb 2012 09:26:58 +0000 (04:26 -0500)]
SWIG: Ensure ptrdiff_t is a known type in gcc >= 4.6.1
This patch fixes a compilation error that occurs with gcc >= 4.6.1,
caused by swig not including cstddef and not using the std:: namespace
prefix for ptrdiff_t. There is an old patch,
http://reviews.m5sim.org/r/913/ that no longer applies cleanly and
this might be re-iterating the same issue.
We work around the problem by always enforcing the inclusion of
cstddef in all swig interface declarations, and also by explicitly
using std::ptrdiff_t.
Steve Reinhardt [Wed, 29 Feb 2012 06:51:39 +0000 (01:51 -0500)]
EIO: update stats (mostly order change, some renames)
Gabe Black [Sun, 26 Feb 2012 23:33:07 +0000 (15:33 -0800)]
Make the IO bridge accept address headed to all the local APICs.
Gabe Black [Sun, 26 Feb 2012 23:32:53 +0000 (15:32 -0800)]
X86: Use the M5PanicFault fault in execute methods instead of calling panic.
If an instruction is executed speculatively and hits a situation where it
wants to panic, it should return a fault instead. If the instruction was
misspeculated, the fault can be thrown away. If the instruction wasn't
misspeculated, the fault will be invoked and the panic will still happen.
Andreas Hansson [Fri, 24 Feb 2012 16:52:49 +0000 (11:52 -0500)]
MEM: Simplify cache ports preparing for master/slave split
This patch splits the two cache ports into a master (memory-side) and
slave (cpu-side) subclass of port with slightly different
functionality. For example, it is only the CPU-side port that blocks
incoming requests, and only the memory-side port that schedules send
events outside of what the transmit list dictates.
This patch simplifies the two classes by relying further on
SimpleTimingPort and also generalises the latter to better accommodate
the changes (introducing trySendTiming and scheduleSend). The
memory-side cache port overrides sendDeferredPacket to be able to not
only send responses from the transmit list, but also send requests
based on the MSHRs.
A follow on patch further simplifies the SimpleTimingPort and the
cache ports.