Palmer Dabbelt [Mon, 24 Apr 2017 15:15:04 +0000 (08:15 -0700)]
Merge pull request #94 from riscv/commitlog
Fix builds with "--enable-commitlog"
Palmer Dabbelt [Wed, 19 Apr 2017 22:48:42 +0000 (15:48 -0700)]
Fix builds with "--enable-commitlog"
Megan Wachs [Tue, 18 Apr 2017 21:04:57 +0000 (14:04 -0700)]
debug: Able to successfully examine a single hart.
Megan Wachs [Tue, 18 Apr 2017 20:47:10 +0000 (13:47 -0700)]
debug: Use Debug-Module specific constants instead of global defines.
Megan Wachs [Tue, 18 Apr 2017 18:44:00 +0000 (11:44 -0700)]
debug: Add fence and fence.i to ensure Debug RAM is ready.
Megan Wachs [Tue, 18 Apr 2017 18:34:31 +0000 (11:34 -0700)]
debug: Checkpoint which somewhat works with OpenOCD v13, but still has some bugs.
Megan Wachs [Tue, 18 Apr 2017 04:21:35 +0000 (21:21 -0700)]
debug: move the debug_rom defines to a seperate file
Megan Wachs [Tue, 18 Apr 2017 02:45:42 +0000 (19:45 -0700)]
debug: Use more unique debug ROM names
Megan Wachs [Tue, 18 Apr 2017 02:36:01 +0000 (19:36 -0700)]
debug: Use a more practical debug ROM
Megan Wachs [Tue, 18 Apr 2017 02:28:49 +0000 (19:28 -0700)]
debug: Move things around, but addresses now conflict with ROM.
Megan Wachs [Mon, 17 Apr 2017 22:19:29 +0000 (15:19 -0700)]
debug: consider COMMAND.transfer bit, and implment HARTINFO
Megan Wachs [Mon, 17 Apr 2017 21:11:43 +0000 (14:11 -0700)]
debug: Compiles again with new debug_defines.h file, but not tested.
Megan Wachs [Mon, 17 Apr 2017 18:31:31 +0000 (11:31 -0700)]
debug: bump the debug_defines to match spec
Megan Wachs [Mon, 17 Apr 2017 17:59:38 +0000 (10:59 -0700)]
Merge remote-tracking branch 'origin/priv-1.10' into HEAD
Andrew Waterman [Tue, 11 Apr 2017 00:35:24 +0000 (17:35 -0700)]
Implement new FP encoding
https://groups.google.com/a/groups.riscv.org/d/msg/isa-dev/_r7hBlzsEd8/cWPyJKMzCQAJ
Andrew Waterman [Sat, 8 Apr 2017 00:57:59 +0000 (17:57 -0700)]
Implement vectored interrupt proposal
https://github.com/riscv/riscv-isa-manual/commit/
4dcaa944ba40e074d25516a157fc37f7491b71cc
Andrew Waterman [Thu, 6 Apr 2017 03:37:01 +0000 (20:37 -0700)]
Add --enable-misaligned option for misaligned ld/st support
Resolves #93
Yunsup Lee [Sat, 1 Apr 2017 02:14:19 +0000 (19:14 -0700)]
update encoding.h to get PMP updates
Andrew Waterman [Sat, 1 Apr 2017 02:11:52 +0000 (19:11 -0700)]
Update LICENSE copyright date
Wesley W. Terpstra [Thu, 30 Mar 2017 07:02:49 +0000 (00:02 -0700)]
fdt: move interrupt controller into its own node
Andrew Waterman [Tue, 28 Mar 2017 04:43:48 +0000 (21:43 -0700)]
Set badaddr=0 on illegal instruction traps
Andrew Waterman [Tue, 28 Mar 2017 04:21:57 +0000 (21:21 -0700)]
On EBREAK, set badaddr to pc
Andrew Waterman [Mon, 27 Mar 2017 21:30:22 +0000 (14:30 -0700)]
Separate page faults from physical memory access exceptions
Andrew Waterman [Sat, 25 Mar 2017 01:10:41 +0000 (18:10 -0700)]
Default to 2 GiB of memory
Andrew Waterman [Thu, 23 Mar 2017 20:24:10 +0000 (13:24 -0700)]
Require little-endian host
Wesley W. Terpstra [Wed, 22 Mar 2017 20:57:56 +0000 (13:57 -0700)]
riscv: replace rtc device with a real clint implementation
Wesley W. Terpstra [Wed, 22 Mar 2017 03:53:09 +0000 (20:53 -0700)]
sim: declare cores as interrupt-controllers for clint
Wesley W. Terpstra [Tue, 21 Mar 2017 23:47:13 +0000 (16:47 -0700)]
bootrom: set a0 to hartid and a1 to dtb before boot
Wesley W. Terpstra [Tue, 21 Mar 2017 23:44:43 +0000 (16:44 -0700)]
configstring: rename variables to dts
Wesley W. Terpstra [Tue, 21 Mar 2017 23:40:01 +0000 (16:40 -0700)]
riscv: remove dependency on num_cores
Wesley W. Terpstra [Tue, 21 Mar 2017 23:06:49 +0000 (16:06 -0700)]
bootrom: include compiled dtb
Wesley W. Terpstra [Sat, 4 Mar 2017 03:02:03 +0000 (19:02 -0800)]
sim: create DTS instead of config string
Wesley W. Terpstra [Sat, 4 Mar 2017 02:51:37 +0000 (18:51 -0800)]
sim: define emulated CPU clock rate to be 1GHz
Wesley W. Terpstra [Sat, 4 Mar 2017 02:50:37 +0000 (18:50 -0800)]
autoconf: put location of 'dtc' into config.h
Palmer Dabbelt [Tue, 21 Mar 2017 20:11:53 +0000 (13:11 -0700)]
spec bump
Andrew Waterman [Mon, 20 Mar 2017 07:48:16 +0000 (00:48 -0700)]
PUM -> SUM; expose MXR to S-mode
Andrew Waterman [Thu, 16 Mar 2017 19:36:32 +0000 (12:36 -0700)]
Simplify interrupt-stack discipline
https://github.com/riscv/riscv-isa-manual/commit/
f2ed45b1791bb602657adc2ea9ab5fc409c62542
Andrew Waterman [Mon, 13 Mar 2017 21:48:52 +0000 (14:48 -0700)]
Implement mstatus.TW, mstatus.TVM, and mstatus.TSR
Andrew Waterman [Tue, 7 Mar 2017 09:58:41 +0000 (01:58 -0800)]
Don't overload illegal instruction trap in interactive code
Andrew Waterman [Mon, 27 Feb 2017 00:13:17 +0000 (16:13 -0800)]
Sv57 and Sv64 are not spec'd yet
Andrew Waterman [Sat, 25 Feb 2017 23:28:27 +0000 (15:28 -0800)]
New counter enable scheme
https://github.com/riscv/riscv-isa-manual/issues/10
Tim Newsome [Sat, 25 Feb 2017 18:17:14 +0000 (10:17 -0800)]
Update bits to latest spec.
Tim Newsome [Thu, 23 Feb 2017 20:12:25 +0000 (12:12 -0800)]
Implement halt request.
Also clean up some vestigial code.
Tim Newsome [Wed, 22 Feb 2017 04:22:10 +0000 (20:22 -0800)]
Improve debug performance.
It's still pitiful, but less so. (5KB/s download speed.)
The tweaks involve switching to the other context as soon as it might be
helpful. The two contexts are executing code, and handling JTAG TAP
input.
Tim Newsome [Wed, 22 Feb 2017 03:32:24 +0000 (19:32 -0800)]
Don't waste time spinning in place in debug mode
Andrew Waterman [Tue, 21 Feb 2017 02:48:35 +0000 (18:48 -0800)]
serialize simulator on wfi
This improves simulator perf when a thread is idle, or waiting on HTIF.
Andrew Waterman [Tue, 21 Feb 2017 01:17:17 +0000 (17:17 -0800)]
Take M-mode interrupts over S-mode interrupts
Andrew Waterman [Tue, 21 Feb 2017 01:16:58 +0000 (17:16 -0800)]
permit MMIO loads to MSIP bit
Andrew Waterman [Sun, 19 Feb 2017 01:24:04 +0000 (17:24 -0800)]
Make HW setting of PTE A/D bits optional (by configure arg)
https://github.com/riscv/riscv-isa-manual/issues/14
Andrew Waterman [Sat, 18 Feb 2017 11:03:10 +0000 (03:03 -0800)]
Spike uarch needs TLB flush after SPTBR write
Tim Newsome [Sat, 18 Feb 2017 02:50:44 +0000 (18:50 -0800)]
Compress log output of jump-to-self loops.
This helps hugely when reading "spike -l" output when debugging is going
on.
Tim Newsome [Thu, 16 Feb 2017 22:15:44 +0000 (14:15 -0800)]
Remove noisy debugs.
This version was able to download code, and run to a breakpoint.
Tim Newsome [Thu, 16 Feb 2017 04:41:06 +0000 (20:41 -0800)]
Set cmderr when data is accessed while busy.
Tim Newsome [Thu, 16 Feb 2017 03:05:20 +0000 (19:05 -0800)]
Implement autoexec. DMI op 2 is just write now.
Now passing MemTest{8,16,32,64}
Tim Newsome [Wed, 15 Feb 2017 23:45:20 +0000 (15:45 -0800)]
Implement resume (untested).
Andrew Waterman [Wed, 15 Feb 2017 11:06:34 +0000 (03:06 -0800)]
sfence.vm -> sfence.vma
Tim Newsome [Tue, 14 Feb 2017 05:29:26 +0000 (21:29 -0800)]
Implement program buffer preexec/postexec.
I only tested preexec.
Tim Newsome [Mon, 13 Feb 2017 19:13:04 +0000 (11:13 -0800)]
dbus -> dmi
Tim Newsome [Mon, 13 Feb 2017 17:53:23 +0000 (09:53 -0800)]
Abstract register read mostly working.
Fails with not supported for 128-bit.
Fails with exception (on rv32) with 64-bit.
Succeeds (on rv32) with 32-bit.
Tim Newsome [Sun, 12 Feb 2017 18:20:37 +0000 (10:20 -0800)]
Fix stack overflow and support --rbb-port=0
Tim Newsome [Sat, 11 Feb 2017 03:08:16 +0000 (19:08 -0800)]
Entering debug mode now jumps to "dynamic rom"
Tim Newsome [Fri, 10 Feb 2017 19:31:30 +0000 (11:31 -0800)]
Implement hartstatus field.
Tim Newsome [Fri, 10 Feb 2017 04:50:14 +0000 (20:50 -0800)]
Remove gdbserver support.
Maybe some day we can bring it back, implementing direct access into
registers and memory so it would be fast. That would be the way to
usefully debug code running in spike, as opposed to the way that mirrors
the actual debug design as it might be implemented in hardware.
Tim Newsome [Thu, 9 Feb 2017 04:40:52 +0000 (20:40 -0800)]
Add writable ibuf and data registers.
Tim Newsome [Thu, 9 Feb 2017 03:47:57 +0000 (19:47 -0800)]
Serve up a correct dmcontrol register.
Andrew Waterman [Wed, 8 Feb 2017 22:16:08 +0000 (14:16 -0800)]
Encode VM type in sptbr, not mstatus
https://github.com/riscv/riscv-isa-manual/issues/4
Also, refactor gdbserver code to not duplicate VM decoding logic.
Tim Newsome [Tue, 7 Feb 2017 19:27:48 +0000 (11:27 -0800)]
OpenOCD does a dmi read and gets dummy value back.
Tim Newsome [Tue, 7 Feb 2017 17:07:59 +0000 (09:07 -0800)]
Merge pull request #83 from bacam/gdb-protocol-fixes
Gdb protocol fixes
Tim Newsome [Tue, 7 Feb 2017 04:15:34 +0000 (20:15 -0800)]
Remove unnecessary circular buffer code.
Tim Newsome [Tue, 7 Feb 2017 03:17:23 +0000 (19:17 -0800)]
Refactor remote bitbang code.
Tim Newsome [Fri, 3 Feb 2017 23:48:15 +0000 (15:48 -0800)]
OpenOCD RISC-V code now gets to scan out dtmcontrol.
Tim Newsome [Fri, 3 Feb 2017 21:29:47 +0000 (13:29 -0800)]
OpenOCD can now scan out the hacked IDCODE.
Tim Newsome [Fri, 3 Feb 2017 19:29:54 +0000 (11:29 -0800)]
OpenOCD connects, and sends some data that we receive.
Andrew Waterman [Fri, 3 Feb 2017 03:25:49 +0000 (19:25 -0800)]
Fix interrupt delegation for coprocessors
Andrew Waterman [Thu, 2 Feb 2017 07:11:59 +0000 (23:11 -0800)]
For FMIN(sNaN, x) and FMIN(qNaN, qNaN), return canonical NaN
Resolves #76
Andrew Waterman [Thu, 2 Feb 2017 06:33:38 +0000 (22:33 -0800)]
Set xPIE=1 on xRET
Resolves #88.
Andrew Waterman [Sun, 8 Jan 2017 02:03:16 +0000 (18:03 -0800)]
Only allow SIP.SSIP to be toggled if the interrupt is delegated
Andrew Waterman [Sun, 8 Jan 2017 01:56:22 +0000 (17:56 -0800)]
Make SIP.STIP read-only
h/t Ron Minnich
See https://groups.google.com/a/groups.riscv.org/forum/#!topic/isa-dev/JV-Hj3W5Kw8
David Craven [Sat, 31 Dec 2016 15:24:42 +0000 (16:24 +0100)]
Comply with GNU coding standards.
Currently the DESTDIR variable is not used correctly which leads to
bogus RUNPATH entries.
https://www.gnu.org/prep/standards/html_node/DESTDIR.html
Brian Campbell [Fri, 30 Dec 2016 21:14:50 +0000 (21:14 +0000)]
Only read exception flag in gdb register read/write. (#85)
The flag is 32 bits, and if we read 64/128 bits then we get fragments of
S1 too and can accidentally send an error. Fixes #84.
Brian Campbell [Wed, 21 Dec 2016 17:53:45 +0000 (17:53 +0000)]
Fix gdb communication error (#82)
Brian Campbell [Tue, 20 Dec 2016 12:32:51 +0000 (12:32 +0000)]
Remove extra gdb protocol responses on register writes
Brian Campbell [Mon, 19 Dec 2016 17:54:19 +0000 (17:54 +0000)]
Fix gdb protocol register read of S0
Stefan O'Rear [Sat, 17 Dec 2016 02:24:41 +0000 (18:24 -0800)]
Use correct format codes for reg_t and size_t
Fixes 32-bit build.
Tim Newsome [Fri, 16 Dec 2016 05:12:34 +0000 (21:12 -0800)]
Fix single stepping over faulting instructions. (#80)
Tim Newsome [Mon, 12 Dec 2016 20:48:58 +0000 (12:48 -0800)]
Reuse the ebreak constants in encoding.h.
Andy Wright [Thu, 1 Dec 2016 20:04:34 +0000 (15:04 -0500)]
Added comments about the modified Duff's Device in execute.cc (#77)
Andrew Waterman [Mon, 14 Nov 2016 00:10:30 +0000 (16:10 -0800)]
Fix 32-bit host portability bug
Ben Gamari [Sat, 12 Nov 2016 01:06:12 +0000 (19:06 -0600)]
Ensure that g++ knows it is building a PCH (#75)
It seems that g++ 5.4 doesn't realize that it is building a precompiled
header unless you pass it -x c++-header.
Andrew Waterman [Thu, 10 Nov 2016 21:40:37 +0000 (13:40 -0800)]
AMOs should always return store faults, not load faults
This commit also factors out the common AMO code into mmu_t.
Tim Newsome [Mon, 31 Oct 2016 20:10:45 +0000 (13:10 -0700)]
Make reading/writing fpu regs work.
Temporarily turn them on in mstatus if necessary.
Tim Newsome [Mon, 31 Oct 2016 19:25:15 +0000 (12:25 -0700)]
Minor code cleanup.
Tim Newsome [Mon, 31 Oct 2016 18:57:15 +0000 (11:57 -0700)]
Check for exception after register write.
Tim Newsome [Fri, 28 Oct 2016 21:01:42 +0000 (14:01 -0700)]
Check for exception after reading a register.
Tim Newsome [Fri, 28 Oct 2016 20:30:43 +0000 (13:30 -0700)]
Fix error message.
It was erroneously complaining that gdb sent too much data even when it
wasn't.
Tim Newsome [Tue, 25 Oct 2016 20:17:40 +0000 (13:17 -0700)]
Increase gdb receive buffer.
Newer gdbs send larger memory write packets when downloading.
Also improve error reporting when gdb sends packets that don't fit in
the buffer.
Andrew Waterman [Mon, 10 Oct 2016 20:32:25 +0000 (13:32 -0700)]
Don't force load trigger timing to After
Allow the CSR writer to make the choice.
@timsifive @colinschmidt this fixes the failing rv64mi-p-breakpoint test.
Tim Newsome [Fri, 7 Oct 2016 15:56:05 +0000 (08:56 -0700)]
Don't die when gdb thinks XLEN is 64 but it's 32.
Instead, just give gdb what it asks for.
Also when gdb does a register write, let the user know that it's likely
misconfigured and tell them how to fix it.
This is probably as well as issue #72 can be fixed in spike.
Tim Newsome [Fri, 30 Sep 2016 21:08:26 +0000 (14:08 -0700)]
Return an error to gdb when memory reads fail. (#71)
Tim Newsome [Thu, 29 Sep 2016 18:24:04 +0000 (11:24 -0700)]
Update trigger behavior. (#70)
M-mode writes to tdata1 with dmode set are ignored instead of raising an
exception.
Add the same behavior for tdata2.