Samuel Pitoiset [Mon, 13 Jan 2020 08:49:49 +0000 (09:49 +0100)]
radv/gfx10: re-enable NGG GS
Now that NGG GS queries are implemented, it should be safe enough
to enable NGG GS by default. It can be disabled with RADV_DEBUG=nongg
if necessary.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3380>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3380>
Samuel Pitoiset [Mon, 13 Jan 2020 17:30:50 +0000 (18:30 +0100)]
radv/gfx10: implement NGG GS queries
The number of generated primitives is only counted by the hardware
if GS uses the legacy path. For NGG GS, we need to accumulate that
value in the NGG GS itself. To achieve that, we use a plain GDS
atomic operation.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3380>
Samuel Pitoiset [Tue, 14 Jan 2020 08:14:07 +0000 (09:14 +0100)]
radv/gfx10: add a separate flag for creating a GDS OA buffer
For implementing NGG GS queries, we decided to use GDS but GDS OA
is only required for NGG streamout.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3380>
Michel Dänzer [Tue, 28 Jan 2020 10:12:24 +0000 (11:12 +0100)]
winsys/amdgpu: Close KMS handles for other DRM file descriptions
When a BO or amdgpu_screen_winsys is destroyed.
Should fix leaking such BOs in other DRM file descriptions.
v2:
* Pass the correct file descriptor to drmIoctl (Pierre-Eric
Pelloux-Prayer)
* Use _mesa_hash_table_remove
v3:
* Close handles in amdgpu_winsys_unref as well
v4:
* Adapt to amdgpu_winsys::sws_list_lock.
Closes: https://gitlab.freedesktop.org/mesa/mesa/issues/2270
Fixes: 11a3679e3aba "winsys/amdgpu: Make KMS handles valid for original
DRM file descriptor"
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3582>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3582>
Michel Dänzer [Tue, 28 Jan 2020 10:07:15 +0000 (11:07 +0100)]
winsys/amdgpu: Re-use amdgpu_screen_winsys when possible
Namely, if os_same_file_description determined that the DRM file
descriptor references the same file description.
v2:
* Adapt to amdgpu_winsys::sws_list_lock.
v3:
* Fix comparison of amdgpu_screen_winsys file descriptions, see
https://gitlab.freedesktop.org/mesa/mesa/issues/2413 .
* Lock amdgpu_winsys::sws_list_lock for traversing the sws_list in
amdgpu_winsys_create.
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3582>
Jason Ekstrand [Wed, 29 Jan 2020 04:25:48 +0000 (22:25 -0600)]
anv: Rename a variable
The name "desc" shadows another variable. Name it "desc_data" like all
of the other descriptor data variables in this file.
Jason Ekstrand [Tue, 28 Jan 2020 23:42:31 +0000 (17:42 -0600)]
anv/block_pool: Ensure allocations have contiguous maps
Because softpin block pools are made up of a set of BOs with different
maps, it was possible for a single state to end up straddling blocks.
To fix this, we pass a contiguous size to anv_block_pool_grow and it
ensures that the next allocation in the pool will have at least that
size.
We also add an assert in anv_block_pool_map to ensure we always get
contiguous maps. Prior to the changes to anv_block_pool_grow, the unit
tests failed with this assert. With this patch, the tests pass.
This was causing problems on Gen12 where we allocate the pages for the
AUX table from the dynamic state pool. The first chunk, which gets
allocated very early in the pool's history, is 1MB which was enough that
it was getting multiple BOs. This caused the gen_aux_map code to write
outside of the map and overwrite the instruction state pool buffer which
lead to GPU hangs.
Fixes: 731c4adcf9b "anv/allocator: Add support for non-userptr"
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Jason Ekstrand [Tue, 28 Jan 2020 22:21:56 +0000 (16:21 -0600)]
anv: Re-use one old BT block in reset_batch_bo_chain
We intentionally throw away all but one BT block but then we set
cmd_buffer->bt_block to ANV_STATE_NULL instead of the one we hung on to.
This causes the command buffer to immediately re-emit STATE_BASE_ADDRESS
the first time a BT is needed for no good reason.
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Jason Ekstrand [Tue, 28 Jan 2020 22:20:35 +0000 (16:20 -0600)]
anv: Set actual state pool sizes when we have softpin
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Rhys Perry [Wed, 9 Oct 2019 14:27:07 +0000 (15:27 +0100)]
nir/algebraic: add some half packing optimizations
pipeline-db (ACO):
Totals from affected shaders:
SGPRS: 29200 -> 29200 (0.00 %)
VGPRS: 17372 -> 17372 (0.00 %)
Spilled SGPRs: 105 -> 105 (0.00 %)
Spilled VGPRs: 0 -> 0 (0.00 %)
Private memory VGPRs: 0 -> 0 (0.00 %)
Scratch size: 0 -> 0 (0.00 %) dwords per thread
Code Size:
1406576 ->
1389256 (-1.23 %) bytes
LDS: 83 -> 83 (0.00 %) blocks
Max Waves: 3976 -> 3976 (0.00 %)
pipeline-db (LLVM):
Totals from affected shaders:
SGPRS: 21320 -> 21320 (0.00 %)
VGPRS: 17056 -> 17036 (-0.12 %)
Spilled SGPRs: 22 -> 22 (0.00 %)
Spilled VGPRs: 503 -> 487 (-3.18 %)
Private memory VGPRs: 0 -> 0 (0.00 %)
Scratch size: 396 -> 396 (0.00 %) dwords per thread
Code Size:
1441244 ->
1423292 (-1.25 %) bytes
LDS: 463 -> 463 (0.00 %) blocks
Max Waves: 3609 -> 3611 (0.06 %)
v2: add pattern for ishr
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Connor Abbott <cwabbott0@gmail.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/2271>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/2271>
Rhys Perry [Wed, 9 Oct 2019 14:03:45 +0000 (15:03 +0100)]
nir/algebraic: add patterns for a >> #b << #b
Fixes compilation of a Battlefront 2 shader with ACO by removing VGPR
spilling. The reassociation makes it worse on LLVM though.
pipeline-db (ACO):
Totals from affected shaders:
SGPRS: 10704 -> 10688 (-0.15 %)
VGPRS: 18736 -> 18528 (-1.11 %)
Spilled SGPRs: 70 -> 70 (0.00 %)
Spilled VGPRs: 0 -> 0 (0.00 %)
Private memory VGPRs: 0 -> 0 (0.00 %)
Scratch size: 0 -> 0 (0.00 %) dwords per thread
Code Size: 909696 -> 885796 (-2.63 %) bytes
LDS: 225 -> 225 (0.00 %) blocks
Max Waves: 1115 -> 1129 (1.26 %)
pipeline-db (LLVM):
Totals from affected shaders:
SGPRS: 8472 -> 8424 (-0.57 %)
VGPRS: 14284 -> 14368 (0.59 %)
Spilled SGPRs: 0 -> 0 (0.00 %)
Spilled VGPRs: 442 -> 503 (13.80 %)
Private memory VGPRs: 0 -> 0 (0.00 %)
Scratch size: 268 -> 396 (47.76 %) dwords per thread
Code Size: 862568 -> 853028 (-1.11 %) bytes
LDS: 0 -> 0 (0.00 %) blocks
Max Waves: 971 -> 964 (-0.72 %)
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Connor Abbott <cwabbott0@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/2271>
Samuel Pitoiset [Wed, 29 Jan 2020 08:18:20 +0000 (09:18 +0100)]
aco: fix VS input loads with MUBUF on GFX6
Only MTBUF supports vec3.
Fixes: 03a0d39366d ("aco: use MUBUF in some situations instead of splitting vertex fetches")
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3615>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3615>
Rhys Perry [Mon, 13 Jan 2020 14:53:56 +0000 (14:53 +0000)]
aco: run p_wqm instructions in WQM
If the p_wqm ends up creating copies, these need to be in WQM. Helps (but
doesn't completely fix) artifacts in Strange Brigade. The actual issue
still exists and is harder to fix.
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Fixes: 93c8ebfa780 ('aco: Initial commit of independent AMD compiler')
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3273>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3273>
Rhys Perry [Thu, 2 Jan 2020 19:13:53 +0000 (19:13 +0000)]
aco: ensure predecessors' p_logical_end is in WQM when a p_phi is in WQM
We want any copies to be in WQM. I don't know if this fixes any real
application, but I can create a vkrunner test than reproduces the issue.
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Fixes: 93c8ebfa780 ('aco: Initial commit of independent AMD compiler')
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3273>
Icecream95 [Sun, 26 Jan 2020 01:59:24 +0000 (14:59 +1300)]
pan/midgard: Fix a liveness info leak
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3566>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3566>
Jonathan Marek [Sat, 4 Jan 2020 19:17:15 +0000 (14:17 -0500)]
etnaviv: implement UBOs
At the same time, use pre-HALTI2 to use address register for indirect
uniform loads, since integers/LOAD instruction isn't always available.
Passes all dEQP-GLES3.functional.ubo.* on GC7000L. GC3000 with an extra
flush hack passes most of them, but still fails on some of the cases with
many loads.
Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3389>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3389>
Rob Clark [Sat, 25 Jan 2020 22:44:55 +0000 (14:44 -0800)]
freedreno/a6xx: convert blend state to stateobj
And move to new register builders while we are at it.
Signed-off-by: Rob Clark <robdclark@chromium.org>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3565>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3565>
Rob Clark [Sat, 25 Jan 2020 21:44:59 +0000 (13:44 -0800)]
freedreno/a6xx: remove special handling based on MRT format
Logicop in particular is supposed to work for integer formats.. but
maybe this situation doesn't happen in gles. The only thing that isn't
required for integer formats is blending.
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3565>
Rob Clark [Fri, 17 Jan 2020 22:00:13 +0000 (14:00 -0800)]
mesa/st: random whitespace cleanup
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3565>
Rob Clark [Fri, 17 Jan 2020 21:58:44 +0000 (13:58 -0800)]
freedreno: use PIPE_CAP_RGB_OVERRIDE_DST_ALPHA_BLEND
This lets us drop a bunch of special handling for xRGB blend.
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3565>
Thomas Hellstrom [Tue, 28 Jan 2020 12:04:23 +0000 (13:04 +0100)]
gallium/util: Increase the debug_flush map depth
Some piglit tests trigger a map depth assert when debug_flush is active.
Fix this by increasing the map depth from 16 to 32.
Signed-off-by: Thomas Hellstrom <thellstrom@vmware.com>
Reviewed-by: Charmaine Lee <charmainel@vmware.com>
Reviewed-by: Brian Paul <brianp@vmware.com>
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3614>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3614>
Thomas Hellstrom [Tue, 28 Jan 2020 11:49:30 +0000 (12:49 +0100)]
svga: Avoid discard DMA uploads
Newer versions of the device code will make discard DMA uploads
sub-optimal. Disable them for guest-backed aware code, where we previously
had them conditionally enabled.
Signed-off-by: Thomas Hellstrom <thellstrom@vmware.com>
Reviewed-by: Charmaine Lee <charmainel@vmware.com>
Reviewed-by: Brian Paul <brianp@vmware.com>
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3614>
Thomas Hellstrom [Tue, 21 Jan 2020 09:58:25 +0000 (10:58 +0100)]
winsys/svga: Enable transhuge pages for buffer objects
If the kernel supports it, enable transhuge pages for graphics buffer
objects. Except for the syscall itself, this is never expected to cause
any negative performance implications.
Signed-off-by: Thomas Hellstrom <thellstrom@vmware.com>
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3614>
Roland Scheidegger [Thu, 24 Oct 2019 04:10:46 +0000 (06:10 +0200)]
winsys/svga: use new ioctl for logging
Use the new ioctl for logging (rather than duplicating what the kernel
is doing). This way it's also independent from the actual guest/host
mechanism to do the logging.
Signed-off-by: Roland Scheidegger <sroland@vmware.com>
Reviewed-by: Thomas Hellstrom <thellstrom@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3614>
Samuel Pitoiset [Tue, 28 Jan 2020 13:49:16 +0000 (14:49 +0100)]
radv: remove the non conformant VK implementation warning on GFX10
It's no longer true.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3597>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3597>
Samuel Pitoiset [Tue, 28 Jan 2020 10:34:06 +0000 (11:34 +0100)]
radv: bump conformance version to 1.2.0.0
https://www.khronos.org/conformance/adopters/conformant-products#submission_472
https://www.khronos.org/conformance/adopters/conformant-products#submission_473
https://www.khronos.org/conformance/adopters/conformant-products#submission_474
Fixes dEQP-VK.api.driver_properties.conformance_version.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3597>
Samuel Pitoiset [Mon, 27 Jan 2020 10:08:26 +0000 (11:08 +0100)]
radv: implement VK_AMD_shader_explicit_vertex_parameter
Closes: https://gitlab.freedesktop.org/mesa/mesa/issues/2402
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3578>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3578>
Samuel Pitoiset [Mon, 27 Jan 2020 10:07:42 +0000 (11:07 +0100)]
radv: gather which input PS variables use an explicit interpolation mode
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3578>
Samuel Pitoiset [Mon, 27 Jan 2020 11:16:41 +0000 (12:16 +0100)]
aco: implement VK_AMD_shader_explicit_vertex_parameter
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3578>
Samuel Pitoiset [Fri, 24 Jan 2020 09:18:06 +0000 (10:18 +0100)]
ac/llvm: implement VK_AMD_shader_explicit_vertex_parameter
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3578>
Samuel Pitoiset [Fri, 24 Jan 2020 09:55:55 +0000 (10:55 +0100)]
spirv: implement SPV_AMD_shader_explicit_vertex_parameter
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3578>
Samuel Pitoiset [Mon, 27 Jan 2020 10:34:00 +0000 (11:34 +0100)]
nir: lower interp_deref_at_vertex to load_input_vertex
This introduces a new NIR intrinsic for loading inputs at a specific
vertex index.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3578>
Samuel Pitoiset [Fri, 24 Jan 2020 15:01:04 +0000 (16:01 +0100)]
nir: add nir_intrinsic_interp_deref_at_vertex
From the SPV_AMD_shader_explicit_vertex_parameter extension:
"Returns the value of the input <interpolant> without any
interpolation, i.e. the raw output value of previous shader
stage."
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3578>
Samuel Pitoiset [Fri, 24 Jan 2020 15:13:01 +0000 (16:13 +0100)]
nir: lower SYSTEM_VALUE_BARYCENTRIC_* to nir_load_barycentric()
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3578>
Samuel Pitoiset [Fri, 24 Jan 2020 10:36:37 +0000 (11:36 +0100)]
nir: add nir_intrinsic_load_barycentric_model
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3578>
Samuel Pitoiset [Fri, 24 Jan 2020 09:54:06 +0000 (10:54 +0100)]
spirv: add support for SpvBuiltInBaryCoord*
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3578>
Samuel Pitoiset [Fri, 24 Jan 2020 09:52:25 +0000 (10:52 +0100)]
compiler: add new SYSTEM_VALUE_BARYCENTRIC_*
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3578>
Samuel Pitoiset [Mon, 27 Jan 2020 17:45:26 +0000 (18:45 +0100)]
compiler: add PERSP to the existing barycentric system values
We need the LINEAR versions for AMD_shader_explicit_vertex_parameter.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3578>
Samuel Pitoiset [Fri, 24 Jan 2020 09:16:56 +0000 (10:16 +0100)]
spirv: add support for SpvDecorationExplicitInterpAMD
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3578>
Samuel Pitoiset [Fri, 24 Jan 2020 09:14:42 +0000 (10:14 +0100)]
compiler: add a new explicit interpolation mode
This introduces one more interpolation mode INTERP_MODE_EXPLICIT,
which is needed for AMD_shader_explicit_vertex_parameter.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3578>
Eduardo Lima Mitev [Sun, 26 Jan 2020 22:25:17 +0000 (22:25 +0000)]
turnip: Fix issues in tu_compute_pipeline_create() that may lead to crash
The shader object is destroyed even if its creation failed. It is also
not destroyed if its compilation or upload fails, leading to leaks.
Finally, tu_compute_pipeline_create() should set output var
pPipeline to VK_NULL_HANDLE if it fails.
Avoids crash on
dEQP-VK.api.object_management.alloc_callback_fail_multiple.compute_pipeline
Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3572>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3572>
Eduardo Lima Mitev [Fri, 24 Jan 2020 12:02:22 +0000 (12:02 +0000)]
turnip: Remove failed command buffer from pool
When an error condition occurs during tu_create_cmd_buffer(), the
cmd buffer has already been added to a pool, so the cleanup code should
remove it.
Fixes a crash (assert in tu_device::tu_bo_finish()) in dEQP tests:
dEQP-VK.api.object_management.max_concurrent.command_buffer_primary
dEQP-VK.api.object_management.max_concurrent.command_buffer_secondary
due to pool attempting to destroy an invalid command buffer.
Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3572>
Pierre-Eric Pelloux-Prayer [Thu, 16 Jan 2020 11:31:24 +0000 (12:31 +0100)]
radeonsi: stop using the VM_ALWAYS_VALID flag
Allocation all the bo as ALWAYS_VALID means they must all fit in memory
(vram + gtt) at each command submission.
This causes some trouble when the total allocated memory is greater than
the available memory.
Possible solutions:
- being able to tag/untag a bo as ALWAYS_VALID: would require kernel changes
- disable VM_ALWAYS_VALID when memory usage is more than a percentage of the
available memory
- disable VM_ALWAYS_VALID entirely
v1 of this patch implemented option 2. v2 (this version) implements option 3.
Related issues:
- https://gitlab.freedesktop.org/drm/amd/issues/607
- https://gitlab.freedesktop.org/mesa/mesa/issues/1257
It also helps with some piglit tests (-t maxsize -t "max[_-].*size" -t maxuniformblocksize):
instead of crashing the machine, the tests fail cleanly.
Closes: https://gitlab.freedesktop.org/mesa/mesa/issues/2190
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3430>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3430>
Samuel Pitoiset [Tue, 28 Jan 2020 16:51:02 +0000 (17:51 +0100)]
radv: enable VK_AMD_shader_fragment_mask on GFX6-GFX7
Works fine.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3603>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3603>
Kenneth Graunke [Tue, 28 Jan 2020 01:21:03 +0000 (17:21 -0800)]
loader: Check if the kernel driver is i915 before loading iris
To prevent it from trying to load on say gma500 hardware.
Reviewed-by: Eric Engestrom <eric@engestrom.ch>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3595>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3595>
Jordan Justen [Thu, 16 Jan 2020 21:16:24 +0000 (13:16 -0800)]
anv: Emit CS Stall before Instruction Cache flush for gen12 WA
Before flushing the instruction cache with a pipe control, we need to
use a CS Stall pipe control.
Ref: GEN:BUG:
1409226450
Rework: Add stall-at-scoreboard (Lionel)
Rework: Merge with other anvil pre-invalidate stalls (Lionel)
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3457>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3457>
Jordan Justen [Thu, 16 Jan 2020 21:16:24 +0000 (13:16 -0800)]
iris: Emit CS Stall before Instruction Cache flush for gen12 WA
Before flushing the instruction cache with a pipe control, we need to
use a CS Stall pipe control.
Ref: GEN:BUG:
1409226450
Rework: Add stall-at-scoreboard (Lionel)
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3457>
Erik Faye-Lund [Mon, 20 Jan 2020 16:35:55 +0000 (17:35 +0100)]
zink: set compareEnable when setting compareOp
We need to enable compareEnable for compareOp to be valid, and ANV was
recently updated to respect this. So let's update Zink to match.
This fixes the shadow-variants of several piglit regressions, like these:
spec@arb_shader_texture_lod@execution@tex-miplevel-selection
spec@glsl-1.20@execution@tex-miplevel-selection
Fixes: a19cdf989b1 ("anv: only use VkSamplerCreateInfo::compareOp if enabled")
Reviewed-by: Eric Engestrom <eric@engestrom.ch>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3473>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3473>
Eric Anholt [Tue, 17 Dec 2019 05:23:02 +0000 (21:23 -0800)]
ci: Enable -Werror on the meson-i386 build.
I find warnings to be very disruptive to my workflow (using emacs's "go to
next error" feature), and I periodically have to go clean up other
people's drivers to get back to finding my own warnings in the noise. I
know I'm not the only one doing something like this.
We don't want to enable -Werror by default in builds, since it means that
end users will have builds spuriously fail based on what compiler version
and opt flags they have compared to what the devs are using. However, it
is quite easy to have CI ensure that we at least don't introduce warnings
on the compiler version that it uses.
For now I've just enabled it on meson-i386 to cover a bunch of Mesa core
and get us started on ratcheting up warnings-cleanliness in the tree,
without me having to fix up all the drivers at once.
Reviewed-by: Daniel Stone <daniels@collabora.com>
Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Eric Engestrom <eric@engestrom.ch>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3539>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3539>
Eric Anholt [Fri, 24 Jan 2020 22:35:49 +0000 (14:35 -0800)]
mesa/st: Fix compiler warnings from INTEL_shader_integer_functions.
Fixes: 1d165b054863 ("glsl: Add new expressions for INTEL_shader_integer_functions2")
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3539>
Eric Anholt [Tue, 17 Dec 2019 05:17:17 +0000 (21:17 -0800)]
iris: Silence warning about AUX_USAGE_MC.
It was recently introduced and not added to iris yet it looks like.
Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3539>
Eric Anholt [Tue, 17 Dec 2019 03:58:39 +0000 (19:58 -0800)]
vulkan/wsi: Fix compiler warning when no WSI platforms are enabled.
Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3539>
Dylan Baker [Tue, 28 Jan 2020 19:36:21 +0000 (11:36 -0800)]
docs: update news, calendar, and link release notes for 19.3.3
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3604>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3604>
Dylan Baker [Tue, 28 Jan 2020 19:32:51 +0000 (11:32 -0800)]
docs: Add SHA 256 sums for 19.3.3
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3604>
Dylan Baker [Tue, 28 Jan 2020 19:06:07 +0000 (11:06 -0800)]
docs: Add relnotes for 19.3.3 release
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3604>
Jason Ekstrand [Mon, 27 Jan 2020 20:42:20 +0000 (14:42 -0600)]
intel/mi_builder: Force write completion on Gen12+
Otherwise, we have no guarantee that the write actually lands before we
move on to other things. Doing this on every SDI is probably a bit
harsh but it's safe. We should figure out a good way to avoid this when
we can.
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3593>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3593>
Jason Ekstrand [Tue, 28 Jan 2020 04:10:36 +0000 (22:10 -0600)]
anv: Replace one more aux_surface.isl.size_B check
This one was missed in
41bffe09135.
Fixes: 41bffe09135 "anv: Replace aux_surface.isl.size_B checks with..."
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3593>
Jason Ekstrand [Tue, 28 Jan 2020 00:22:14 +0000 (18:22 -0600)]
intel/blorp: Handle bit-casting UNORM and BGRA formats
In
f132e0fddfa, I attempted to allow BLORP to do CCS_E copies by using
the UNORM formats instead. However, the old BLORP bit-cast code could
only handle RGBA formats and asserted on anything other than UINT
formats. The reason we didn't catch this is because it only comes up on
Gen12 platforms which aren't in our normal CI yet.
Fixes: f132e0fddfad "intel/blorp: Add support for CCS_E copies with..."
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3593>
Daniel Schürmann [Tue, 28 Jan 2020 11:32:09 +0000 (12:32 +0100)]
aco: fix combine_salu_not_bitwise() when SCC is used
Previously, we didn't use the SCC bit, and thus, we didn't care about it.
With 'aco: Transform uniform bitwise instructions to 32-bit if possible.'
that changed, so that we have to handle it.
Fixes: 8a32f57fff56b3b94f1b5589feba38016f39427c ('aco: Transform uniform bitwise instructions to 32-bit if possible.')
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3598>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3598>
Drew Davenport [Mon, 27 Jan 2020 18:13:19 +0000 (11:13 -0700)]
radeonsi: Clear uninitialized variable
|view| was not initialized leading to flaky test failures in SkQP
test unitTest_ES2BlendWithNoTexture.
Fixes: 029bfa3d253 "radeonsi: add ability to bind images as image buffers"
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3592>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3592>
Brian Ho [Mon, 27 Jan 2020 03:50:42 +0000 (19:50 -0800)]
anv: Handle unavailable queries in vkCmdCopyQueryPoolResults
If VK_QUERY_RESULT_WAIT_BIT is not set, there is currently no
special handling of unavailable queries in vkCmdCopyQueryPoolResults,
and anv will write an invalid value for the query result.
This commit updates vkCmdCopyQueryPoolResults for unavailable
queries to return 0 if the VK_QUERY_RESULT_PARTIAL_BIT flag is set
and if not, skip writing altogether.
Cc: <mesa-stable@lists.freedesktop.org>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3586>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3586>
Brian Ho [Sun, 26 Jan 2020 23:12:11 +0000 (15:12 -0800)]
anv: Properly fetch partial results in vkGetQueryPoolResults
Currently, fetching the partial results (VK_QUERY_RESULT_PARTIAL_BIT)
of an unavailable occlusion query via vkGetQueryPoolResults can
return invalid values. anv returns slot.end - slot.begin, but in the
case of unavailable queries, slot.end is still at the initial value
of 0. If slot.begin is non-zero, the occlusion count underflows to
a value that is likely outside the acceptable range of the partial
result.
This commit fixes vkGetQueryPoolResults by always returning 0 if the
query is unavailable and the VK_QUERY_RESULT_PARTIAL_BIT is set.
Cc: <mesa-stable@lists.freedesktop.org>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3586>
Rhys Perry [Tue, 28 Jan 2020 13:29:14 +0000 (13:29 +0000)]
aco: fix rebase error from GS copy shader support
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Fixes: f8f7712666b ('aco: implement GS copy shaders')
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3601>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3601>
Tapani Pälli [Fri, 24 Jan 2020 12:46:21 +0000 (14:46 +0200)]
anv/android: make format_supported_with_usage static
Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Acked-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3532>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3532>
Tapani Pälli [Thu, 23 Jan 2020 07:48:47 +0000 (09:48 +0200)]
anv/android: setup gralloc1 usage from gralloc0 usage manually
This cuts away dependency to libgrallocusage.
Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Acked-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3532>
Rhys Perry [Fri, 3 Jan 2020 17:13:42 +0000 (17:13 +0000)]
aco: use MUBUF in some situations instead of splitting vertex fetches
Fixes most of the regressions from splitting vertex fetches in an earlier
commit.
pipeline-db (Vega):
Totals from affected shaders:
SGPRS: 0 -> 0 (0.00 %)
VGPRS: 0 -> 0 (0.00 %)
Spilled SGPRs: 0 -> 0 (0.00 %)
Spilled VGPRs: 0 -> 0 (0.00 %)
Private memory VGPRs: 0 -> 0 (0.00 %)
Scratch size: 0 -> 0 (0.00 %) dwords per thread
Code Size: 0 -> 0 (0.00 %) bytes
LDS: 0 -> 0 (0.00 %) blocks
Max Waves: 0 -> 0 (0.00 %)
pipeline-db (Navi):
Totals from affected shaders:
SGPRS: 562696 -> 558344 (-0.77 %)
VGPRS: 395596 -> 393752 (-0.47 %)
Spilled SGPRs: 0 -> 0 (0.00 %)
Spilled VGPRs: 0 -> 0 (0.00 %)
Private memory VGPRs: 0 -> 0 (0.00 %)
Scratch size: 0 -> 0 (0.00 %) dwords per thread
Code Size:
11600912 ->
11311804 (-2.49 %) bytes
LDS: 0 -> 0 (0.00 %) blocks
Max Waves: 101839 -> 102372 (0.52 %)
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3086>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3086>
Rhys Perry [Fri, 3 Jan 2020 17:38:23 +0000 (17:38 +0000)]
aco: value-number MUBUF instructions
We will have to do this when we start creating MUBUF instructions for
load_input because NIR might not be able to tell they are identical since
it doesn't know whether two vertex attributes have the same offset.
No pipeline-db changes.
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3086>
Rhys Perry [Fri, 13 Dec 2019 13:23:11 +0000 (13:23 +0000)]
aco: handle unaligned vertex fetch on GFX10
pipeline-db (Vega):
Totals from affected shaders:
SGPRS: 0 -> 0 (0.00 %)
VGPRS: 0 -> 0 (0.00 %)
Spilled SGPRs: 0 -> 0 (0.00 %)
Spilled VGPRs: 0 -> 0 (0.00 %)
Private memory VGPRs: 0 -> 0 (0.00 %)
Scratch size: 0 -> 0 (0.00 %) dwords per thread
Code Size: 0 -> 0 (0.00 %) bytes
LDS: 0 -> 0 (0.00 %) blocks
Max Waves: 0 -> 0 (0.00 %)
pipeline-db (Navi):
Totals from affected shaders:
SGPRS: 795000 -> 802368 (0.93 %)
VGPRS: 579632 -> 581280 (0.28 %)
Spilled SGPRs: 0 -> 0 (0.00 %)
Spilled VGPRs: 0 -> 0 (0.00 %)
Private memory VGPRs: 0 -> 0 (0.00 %)
Scratch size: 0 -> 0 (0.00 %) dwords per thread
Code Size:
17208408 ->
17583652 (2.18 %) bytes
LDS: 0 -> 0 (0.00 %) blocks
Max Waves: 145731 -> 145279 (-0.31 %)
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3086>
Rhys Perry [Fri, 13 Dec 2019 13:23:27 +0000 (13:23 +0000)]
aco: skip unused channels at the start when fetching vertices
pipeline-db (Vega):
Totals from affected shaders:
SGPRS: 161320 -> 161224 (-0.06 %)
VGPRS: 153968 -> 149408 (-2.96 %)
Spilled SGPRs: 0 -> 0 (0.00 %)
Spilled VGPRs: 0 -> 0 (0.00 %)
Private memory VGPRs: 0 -> 0 (0.00 %)
Scratch size: 0 -> 0 (0.00 %) dwords per thread
Code Size:
4331496 ->
4331308 (-0.00 %) bytes
LDS: 0 -> 0 (0.00 %) blocks
Max Waves: 27814 -> 28594 (2.80 %)
pipeline-db (Navi):
Totals from affected shaders:
SGPRS: 161504 -> 161408 (-0.06 %)
VGPRS: 153836 -> 149440 (-2.86 %)
Spilled SGPRs: 0 -> 0 (0.00 %)
Spilled VGPRs: 0 -> 0 (0.00 %)
Private memory VGPRs: 0 -> 0 (0.00 %)
Scratch size: 0 -> 0 (0.00 %) dwords per thread
Code Size:
4327572 ->
4327604 (0.00 %) bytes
LDS: 0 -> 0 (0.00 %) blocks
Max Waves: 27837 -> 28618 (2.81 %)
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3086>
Rhys Perry [Mon, 9 Dec 2019 12:18:51 +0000 (12:18 +0000)]
aco: rework vertex fetching a bit
This will make it easier to skip unused channels at the start and to split
unaligned loads on GFX10.
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3086>
Rhys Perry [Tue, 14 Jan 2020 13:01:53 +0000 (13:01 +0000)]
amd/common,radv: move vertex_format_table to ac_shader_util.{h,c}
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3086>
Jan Zielinski [Tue, 28 Jan 2020 11:09:11 +0000 (12:09 +0100)]
gallium/swr: fix tessellation state save/restore
Tessellation state should be saved with TCS/TES state
when binding new state and restored if old state
is set again.
Reviewed-by: Krzysztof Raszkowski <krzysztof.raszkowski@intel.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3596>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3596>
Vasily Khoruzhick [Sun, 26 Jan 2020 18:30:17 +0000 (10:30 -0800)]
lima: disable early-z if fragment shader uses discard
We have to disable early-z if fragment shader uses discard,
otherwise we'll get misrendering.
Reported-by: Icenowy Zheng <icenowy@aosc.io>
Reviewed-by: Andreas Baierl <ichgeh@imkreisrum.de>
Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3570>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3570>
Vasily Khoruzhick [Sat, 25 Jan 2020 21:31:53 +0000 (13:31 -0800)]
lima: ppir: always create move and update ld_tex successors for all blocks
Always create a mov for ld_tex since we can't rely on
ppir_node_has_single_src_succ() if we have multiple blocks. And since
ld_tex successor can be in a different block we have to update their
ppir_src as well.
Reviewed-by: Erico Nunes <nunes.erico@gmail.com>
Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3564>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3564>
Vasily Khoruzhick [Sat, 25 Jan 2020 19:40:37 +0000 (11:40 -0800)]
lima: ppir: don't delete root ld_tex nodes without successors in current block
We don't clone ld_tex nodes into each block anymore, so ld_tex may have
successors in another block.
Fixes: c8554f849e41 ("lima/ppir: don't clone texture loads")
Reviewed-by: Erico Nunes <nunes.erico@gmail.com>
Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3564>
Rob Clark [Tue, 19 Nov 2019 17:43:22 +0000 (09:43 -0800)]
freedreno/drm: fix invalid-cmdstream-size with older kernels
A cmdstream of size zero is invalid. But this can appear in various
places where we emit a pointer to state. This doesn't show up with
newer kernels (newer than v5.0) which use "softpin", but on earlier
kernels can result in:
[drm:msm_ioctl_gem_submit [msm]] *ERROR* invalid cmdstream size: 0
Since the pointer value doesn't matter in these cases, the easy solution
is just to not emit a cmds table entry in this case.
Signed-off-by: Rob Clark <robdclark@chromium.org>
Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/2805>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/2805>
Marek Olšák [Mon, 27 Jan 2020 22:40:38 +0000 (17:40 -0500)]
Revert "winsys/amdgpu: Re-use amdgpu_screen_winsys when possible"
This reverts commit
b60f5cbc15a99ddd9251bce40eae7d84c3a1c373.
This fixes dmesg errors and X freezes:
[ 29.543096] amdgpu 0000:0c:00.0: No GEM object associated to handle 0x00000009, can't create framebuffer
[ 29.543103] amdgpu 0000:0c:00.0: No GEM object associated to handle 0x00000009, can't create framebuffer
Marek Olšák [Mon, 27 Jan 2020 22:40:32 +0000 (17:40 -0500)]
Revert "winsys/amdgpu: Close KMS handles for other DRM file descriptions"
This reverts commit
552028c013cc1d49a2b61ebe0fc3a3781a9ba826.
Required by the next reverted commit.
Jason Ekstrand [Wed, 22 Jan 2020 20:26:24 +0000 (14:26 -0600)]
anv: Insert holes for non-existant XFB varyings
Thanks to optimizations, it's possible for varyings to get deleted but
still leave the variable there for nir_gather_xfb_info to find. If we
get into this case, insert a hole.
Fixes: 36ee2fd61c8 "anv: Implement the basic form of..."
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3520>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3520>
Jason Ekstrand [Wed, 22 Jan 2020 20:25:08 +0000 (14:25 -0600)]
intel/genxml: Make SO_DECL::"Hole Flag" a Boolean
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3520>
Sagar Ghuge [Wed, 15 Jan 2020 00:12:31 +0000 (16:12 -0800)]
intel/compiler: Clear accumulator register before EOT
v2: (Francisco Jerez)
- Drop vec4 changes.
- Handle explicit acc0 operand and implicit one.
- Make sure instruction is SIMD16, prediction is off and default mask
control set to true.
v3: (Francisco Jerez)
- Clear accumulator only when it's written.
- Use BRW_MASK_DISABLE instead of true.
- Use correct width for brw_acc_reg().
- Fix last_inst_offset.
v4: (Francisco Jerez)
- Don't check for last instruction for accummulator write.
Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3376>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3376>
Alyssa Rosenzweig [Mon, 27 Jan 2020 18:37:36 +0000 (13:37 -0500)]
pan/midgard: Remove float_bitcast
Now unused.
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3588>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3588>
Samuel Pitoiset [Mon, 27 Jan 2020 14:17:25 +0000 (15:17 +0100)]
radv: do not allow sparse resources with multi-planar formats
It's unsupported.
Fixes some fails or hangs with
dEQP-VK.sparse_resources.image_sparse_binding.*
Cc: 19.3 <mesa-stable@lists.freedesktop.org>
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3581>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3581>
Boris Brezillon [Mon, 20 Jan 2020 17:40:43 +0000 (18:40 +0100)]
panfrost/midgard: Prettify embedded constant prints
Until now, embedded constants were printed as all 32 bits integer or
floats, but the compiler can pack constant from different types if
severa instructions with different reg_mode and native type refer to
the constant register. Let's implement something smarter so users don't
have to do a manual conversion when looking at a trace.
Note that 8-bit constants are not decoded yet, as we're not sure how
the writemask is encoded in that case.
Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3536>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3536>
Boris Brezillon [Fri, 24 Jan 2020 08:22:48 +0000 (09:22 +0100)]
panfrost/midgard: Add a condense_writemask() helper
This way we can convert an 8-bit writemask (Midgard specific
representation) into the more common 1-bit/component representation.
8-bit mode is not supported yet, as we're not sure how the writemask is
encoded for this mode.
Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3536>
Rhys Perry [Fri, 24 Jan 2020 17:37:11 +0000 (17:37 +0000)]
aco: fix literal application with v_cndmask_b32/v_addc_co_u32/etc
No pipeline-db changes
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Fixes: 0be74090696 ('aco: rewrite literal combining')
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3541>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3541>
Rhys Perry [Thu, 23 Jan 2020 20:03:40 +0000 (20:03 +0000)]
aco: always add sgprs to sgpr_ids when choosing literals
Even if it's a literal, we should add this to sgpr_ids.
No pipeline-db changes.
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Fixes: 0be74090696 ('aco: rewrite literal combining')
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3541>
Rhys Perry [Thu, 23 Jan 2020 19:34:06 +0000 (19:34 +0000)]
aco: fix operand to scc when selecting SGPR ufind_msb/ifind_msb
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Fixes: 93c8ebfa78 ('aco: Initial commit of independent AMD compiler')
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3541>
Rhys Perry [Thu, 23 Jan 2020 19:30:29 +0000 (19:30 +0000)]
aco: fix WaR check for >64-bit FLAT/GLOBAL instructions
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Fixes: 5986e0019 ('aco: improve WAR hazard workaround with >64bit stores')
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3541>
Alyssa Rosenzweig [Mon, 27 Jan 2020 13:34:49 +0000 (08:34 -0500)]
pan/midgard: Handle tag 0x4 as texture
Used for barriers which work as texture ops.
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3580>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3580>
Alyssa Rosenzweig [Fri, 24 Jan 2020 02:20:16 +0000 (21:20 -0500)]
pan/midgard: Validate barriers use a barrier tag
...and that non-barriers don't use a barrier tag. It's not clear what
the difference means quite yet, though.
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3580>
Alyssa Rosenzweig [Fri, 24 Jan 2020 02:17:07 +0000 (21:17 -0500)]
pan/midgard: Disassemble barrier instructions
We don't need to print all the usual texture noise; just the relevant
fields and the rest can be guarded to zero.
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3580>
Alyssa Rosenzweig [Fri, 24 Jan 2020 01:54:14 +0000 (20:54 -0500)]
pan/midgard: Record TEXTURE_OP_BARRIER
It's 0x0B for whatever reason.
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3580>
Alyssa Rosenzweig [Wed, 22 Jan 2020 13:51:19 +0000 (08:51 -0500)]
pan/decode: Drop MFBD compute shader stuff
This is triggering all sorts of failures in pandecode and is only mostly
spurious. Let's not overwhelm ourselves with this yet.
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3580>
Icecream95 [Fri, 24 Jan 2020 06:45:17 +0000 (19:45 +1300)]
panfrost: Don't copy uniforms when the size is zero
This fixes a crash when using Gallium HUD with QuakeSpasm when gamma
correction shaders (a QuakeSpasm feature, not part of Mesa) are used.
Reviewd-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3549>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3549>
Florian Will [Mon, 27 Jan 2020 09:30:21 +0000 (10:30 +0100)]
radv/winsys: set IB flags prior to submit in the sysmem path
This fixes missing scene objects in ZUSI 3 + dxvk. Index / vertex buffer
upload using thousands of CopyBuffer commands in one huge Vulkan command
buffer, mixed with lots of render pass begin/end and draw calls, failed
for some of the buffers.
radv divides the huge command buffer into 3 IBs, and they had random
flags set because the field was uninitialized. Maybe IBs got discarded
if they had the PREAMBLE bit set.
Signed-off-by: Florian Will <florian.will@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Cc: <mesa-stable@lists.freedesktop.org>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3577>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3577>
Pierre-Eric Pelloux-Prayer [Tue, 21 Jan 2020 17:56:03 +0000 (18:56 +0100)]
docs: document AMD_DEBUG variable
See https://gitlab.freedesktop.org/mesa/mesa/issues/2022
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3492>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3492>
Pierre-Eric Pelloux-Prayer [Tue, 21 Jan 2020 17:46:28 +0000 (18:46 +0100)]
radeonsi: move AMD_DEBUG tests to AMD_TEST
AMD_DEBUG env var is stored in a 64 bits int and has 64 different values.
This commit makes some space by moving the test* special values to AMD_TEST.
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3492>
Dave Airlie [Sun, 26 Jan 2020 21:21:17 +0000 (07:21 +1000)]
gallivm/nir: add missing break for isub.
Pointed out by coverity scan.
Fixes: 3adf74f2ef55 ("gallivm: pick integer builders for alu instructions.")
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3571>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3571>
Lionel Landwerlin [Fri, 24 Jan 2020 21:45:41 +0000 (23:45 +0200)]
isl: add gen12 comment about CCS for linear tiling
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3551>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3551>
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