Andreas Hansson [Thu, 21 Apr 2016 08:48:19 +0000 (04:48 -0400)]
mem: Remove unused cache stats
Prune cache stats that are never actually used.
Andreas Hansson [Thu, 21 Apr 2016 08:48:07 +0000 (04:48 -0400)]
mem: Deallocate all write-queue entries when sent
This patch removes the write-queue entry tracking previously used for
uncacheable writes. The write-queue entry is now deallocated as soon
as the packet is sent. As a result we also forego the stats for
uncacheable writes. Additionally, there is no longer a need to attach
the write-queue entry to the packet.
Andreas Hansson [Thu, 21 Apr 2016 08:48:06 +0000 (04:48 -0400)]
mem: Align downstream cache packet creation in atomic and timing
This patch makes the control flow more uniform in atomic and timing,
ultimately making the code easier to understand.
Andreas Hansson [Thu, 21 Apr 2016 08:48:04 +0000 (04:48 -0400)]
config: Add missing point of coherency to memcheck script
Bring in line with changes to the XBar class.
Andreas Sandberg [Mon, 18 Apr 2016 09:40:50 +0000 (10:40 +0100)]
scons: Fix Python 2.6 compatibility
Don't use Python 2.7-style with statements in the SConstruct file.
Andreas Sandberg [Mon, 18 Apr 2016 09:31:38 +0000 (10:31 +0100)]
style: Fix Python 2.6 compatibility
The style checker code needs to disable autojunk when diffing source
files using Python's difflib. Support for this was only introduced in
Python 2.7, which leads to a TypeError exception on older Python
version. This changeset adds a fallback mechanism for old Python
versions.
Joel Hestness [Fri, 15 Apr 2016 17:34:02 +0000 (12:34 -0500)]
ruby: Fix block_on behavior
Ruby's controller block_on behavior aimed to block MessageBuffer requests into
SLICC controllers when a Locked_RMW was in flight. Unfortunately, this
functionality only partially works: When non-Locked_RMW memory accesses are
issued to the sequencer to an address with an in-flight Locked_RMW, the
sequencer may pass those accesses through to the controller. At the controller,
a number of incorrect activities can occur depending on the protocol. In
MOESI_hammer, for example, an intermediate IFETCH will cause an L1D to L2
transfer, which cannot be serviced, because the block_on functionality blocks
the trigger queue, resulting in a deadlock. Further, if an intermediate store
arrives (e.g. from a separate SMT thread), the sequencer allows the request
through to the controller, and the atomicity of the Locked_RMW may be broken.
To avoid these problems, disallow the Sequencer from passing any memory
accesses to the controller besides Locked_RMW_Write when a Locked_RMW is in-
flight.
Bjoern A. Zeeb [Fri, 15 Apr 2016 15:03:03 +0000 (10:03 -0500)]
arm,dev: remove PMU assertion hit on reset
Remve the assertion that we always need to add a delta larger than
zero as that does not seem to be true when we hit it in the
'PMU reset cycle counter to zero' case.
Committed by Jason Lowe-Power <power.jg@gmail.com>
Bjoern A. Zeeb [Fri, 15 Apr 2016 15:02:58 +0000 (10:02 -0500)]
mem: FreeBSD does not provide MAP_NORESERVE either
Like OS X, FreeBSD does not support MAP_NORESERVE.
Handle accordingly and update comment.
Committed by Jason Lowe-Power <power.jg@gmail.com>
Abdul Mutaal Ahmad [Fri, 15 Apr 2016 14:55:26 +0000 (09:55 -0500)]
misc: Bugfix in TLM memInhibit Command
memInhibitAsserted() has been removed from packet.hh. This change has been
reflected in TLM based SystemC memory.
This patch also adds a number of panics asserting the SystemC memory only
sees requests it expects.
Committed by Jason Lowe-Power <power.jg@gmail.com>
Mohammad Alian [Thu, 14 Apr 2016 18:07:42 +0000 (14:07 -0400)]
dist: config file for distributed switch
Distributed gem5 is the result of the convergence effort between
multi-gem5 and pd-gem5. It relies on the base multi-gem5 infrastructure
for packet forwarding, synchronisation and checkpointing but combines
those with the elaborated network switch model from pd-gem5.
Andreas Hansson [Wed, 13 Apr 2016 16:13:44 +0000 (12:13 -0400)]
misc: Fix issues flagged by gcc 6
A few warnings (and thus errors) pop up after being added to -Wall:
1. -Wmisleading-indentation
In the auto-generated code there were instances of if/else blocks that
were not indented to gcc's liking. This is addressed by adding braces.
2. -Wshift-negative-value
gcc is clever enougn to consider ~0 a negative constant, and
rightfully complains. This is addressed by using mask() which
explicitly casts to unsigned before shifting.
That is all. Porting done.
Andreas Hansson [Tue, 12 Apr 2016 09:28:39 +0000 (05:28 -0400)]
misc: Appease clang...again
Once again, clang is having issues with recently committed code.
Unfortunately HSAIL_X86 is still broken.
Andreas Hansson [Sat, 9 Apr 2016 16:13:40 +0000 (12:13 -0400)]
stats: Match current behaviour
Small changes to the branch predictor and BTB caused stats changes
throughout.
Curtis Dunham [Fri, 8 Apr 2016 16:01:45 +0000 (11:01 -0500)]
stats: update stats for thermals, indirect BP
Rekai Gonzalez Alberquilla [Thu, 7 Apr 2016 16:32:38 +0000 (11:32 -0500)]
mem: Add priority to QueuedPrefetcher
Queued prefetcher entries now count with a priority field. The idea is to
add packets ordered by priority and then by age.
For the existing algorithms in which priority doesn't make sense, it is set
to 0 for all deferred packets in the queue.
Rekai Gonzalez Alberquilla [Thu, 7 Apr 2016 16:32:38 +0000 (11:32 -0500)]
mem: Handful extra features for BasePrefetcher
Some common functionality added to the base prefetcher, mainly dealing with
extracting the block address, page address, block index inside the page and
some other information that can be inferred from the block address. This is
used for some prefetching algorithms, and having the methods in the base,
as well as the block size and other information is the sensible way.
Victor Garcia [Thu, 7 Apr 2016 16:32:38 +0000 (11:32 -0500)]
mem: Add Program Counter to MemTraceProbe
Rekai Gonzalez Alberquilla [Wed, 27 May 2015 12:50:01 +0000 (13:50 +0100)]
mem: Add unused prefetch counter in caches
Added stat to the cache to account for HardPF'ed blocks that are evicted
before being referenced (over-prefetching).
Mitch Hayenga [Thu, 7 Apr 2016 14:30:20 +0000 (09:30 -0500)]
mem: Remove threadId from memory request class
In general, the ThreadID parameter is unnecessary in the memory system
as the ContextID is what is used for the purposes of locks/wakeups.
Since we allocate sequential ContextIDs for each thread on MT-enabled
CPUs, ThreadID is unnecessary as the CPUs can identify the requesting
thread through sideband info (SenderState / LSQ entries) or ContextID
offset from the base ContextID for a cpu.
This is a re-spin of
20264eb after the revert (
bd1c6789) and includes
some fixes of that commit.
Mitch Hayenga [Tue, 5 Apr 2016 17:20:19 +0000 (12:20 -0500)]
cpu: Implement per-thread GHRs
Branch predictors that use GHRs should index them on a
per-thread basis. This makes that so.
This is a re-spin of
fb51231 after the revert (
bd1c6789).
Mitch Hayenga [Tue, 5 Apr 2016 16:48:37 +0000 (11:48 -0500)]
cpu: Add an indirect branch target predictor
This patch adds a configurable indirect branch predictor that can be indexed
by a combination of GHR and path history hashes. Implements the functionality
described in:
"Target prediction for indirect jumps" by Chang, Hao, and Patt
http://dl.acm.org/citation.cfm?id=264209
This is a re-spin of
fb9d142 after the revert (
bd1c6789).
Mitch Hayenga [Tue, 5 Apr 2016 16:44:27 +0000 (11:44 -0500)]
cpu: Fix BTB threading oversight
The extant BTB code doesn't hash on the thread id but does check the
thread id for 'btb hits'. This results in 1-thread of a multi-threaded
workload taking a BTB entry, and all other threads missing for the same branch
missing.
Sascha Bischoff [Wed, 6 Apr 2016 16:55:17 +0000 (17:55 +0100)]
misc: Bail out of DVFS dot if we cannot resolve the domains
This changeset updates the dot output to bail out if it is unable to
resolve the voltage or clock domains (which will cause it to raise an
AttributeError). Additionally, the DVFS dot output is disabled by
default for speed purposes.
Minor fixup for
0aeca8f.
Andreas Sandberg [Thu, 7 Apr 2016 09:42:07 +0000 (10:42 +0100)]
Revert to
74c1e6513bd0 (sim: Thermal support for Linux)
Andreas Sandberg [Wed, 6 Apr 2016 18:43:31 +0000 (19:43 +0100)]
Revert power patch sets with unexpected interactions
The following patches had unexpected interactions with the current
upstream code and have been reverted for now:
e07fd01651f3: power: Add support for power models
831c7f2f9e39: power: Low-power idle power state for idle CPUs
4f749e00b667: power: Add power states to ClockedObject
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
--HG--
extra : amend_source :
0b6fb073c6bbc24be533ec431eb51fbf1b269508
Mitch Hayenga [Tue, 5 Apr 2016 17:39:21 +0000 (12:39 -0500)]
mem: Remove threadId from memory request class
In general, the ThreadID parameter is unnecessary in the memory system
as the ContextID is what is used for the purposes of locks/wakeups.
Since we allocate sequential ContextIDs for each thread on MT-enabled
CPUs, ThreadID is unnecessary as the CPUs can identify the requesting
thread through sideband info (SenderState / LSQ entries) or ContextID
offset from the base ContextID for a cpu.
Curtis Dunham [Tue, 5 Apr 2016 17:20:19 +0000 (12:20 -0500)]
cpu: Implement per-thread GHRs
Branch predictors that use GHRs should index them on a
per-thread basis. This makes that so.
Mitch Hayenga [Tue, 5 Apr 2016 16:48:37 +0000 (11:48 -0500)]
cpu: Add an indirect branch target predictor
This patch adds a configurable indirect branch predictor that can be indexed
by a combination of GHR and path history hashes. Implements the functionality
described in:
"Target prediction for indirect jumps" by Chang, Hao, and Patt
http://dl.acm.org/citation.cfm?id=264209
Mitch Hayenga [Tue, 5 Apr 2016 16:44:27 +0000 (11:44 -0500)]
cpu: Fix BTB threading oversight
The extant BTB code doesn't hash on the thread id but does check the
thread id for 'btb hits'. This results in 1-thread of a multi-threaded
workload taking a BTB entry, and all other threads missing for the same branch
missing.
David Guillen Fandos [Tue, 5 Apr 2016 15:52:28 +0000 (10:52 -0500)]
power: Add support for power models
This patch adds some basic support for power models in gem5.
The power interface is defined so it can interact with thermal
models as well. It implements a simple power evaluator that
can be used for simple power models that express power in the
form of a math expression. These expressions can use stats
within the same SimObject (or down its hierarchy) and some
magic variables such as "temp" for temperature.
In future patches we will extend this functionality to allow
slightly more complex expressions.
The model allows it to be extended to use other kinds of models.
Finally, the thermal model is updated to use the power usage as input.
Akash Bagdia [Tue, 9 Dec 2014 10:42:08 +0000 (10:42 +0000)]
power: Low-power idle power state for idle CPUs
Add functionality to the BaseCPU that will put the entire CPU into a low-power
idle state whenever all threads in it are idle.
Akash Bagdia [Tue, 18 Nov 2014 14:00:48 +0000 (14:00 +0000)]
power: Add power states to ClockedObject
Add 4 power states to the ClockedObject, provides necessary access functions
to check and update the power state. Default power state is UNDEFINED, it is
responsibility of the respective simulation model to provide the startup state
and any other logic for state change.
Add number of transition stat.
Add distribution of time spent in clock gated state.
Add power state residency stat.
Add dump call back function to allow stats update of distribution and residency
stats.
David Guillen Fandos [Wed, 13 May 2015 14:02:25 +0000 (15:02 +0100)]
sim: Thermal support for Linux
This patch enables Linux to read the temperature using hwmon infrastructure.
In order to use this in your gem5 you need to compile the kernel using the
following configs:
CONFIG_HWMON=y
CONFIG_SENSORS_VEXPRESS=y
And a proper dts file (containing an entry such as):
dcc {
compatible = "arm,vexpress,config-bus";
arm,vexpress,config-bridge = <&v2m_sysreg>;
temp@0 {
compatible = "arm,vexpress-temp";
arm,vexpress-sysreg,func = <4 0>;
label = "DCC";
};
};
David Guillen Fandos [Tue, 12 May 2015 09:26:47 +0000 (10:26 +0100)]
sim: Adding thermal model support
This patch adds basic thermal support to gem5. It models energy dissipation
through a circuital equivalent, which allows us to use RC networks.
This lays down the basic infrastructure to do so, but it does not "work" due
to the lack of power models. For now some hardcoded number is used as a PoC.
The solver is embedded in the patch.
Mitch Hayenga [Tue, 5 Apr 2016 13:08:12 +0000 (08:08 -0500)]
cpu: Add instruction opclass histogram to minor
Sascha Bischoff [Tue, 15 Dec 2015 09:40:56 +0000 (09:40 +0000)]
misc: Add secondary dot output for DVFS domains
This patch adds a secondary dot output file which shows the DVFS domains. This
has been done separately for now to avoid cluttering the already existing
diagram. Due to the way that the clock domains are assigned to components in
gem5, this output must be generated after the C++ objects have been
instantiated. This further motivates the need to generate this file separately
to the current dot output, and not to replace it entirely.
Sascha Bischoff [Fri, 11 Dec 2015 17:29:53 +0000 (17:29 +0000)]
sim: Add additional debug information when draining
This patch adds some additional information when draining the system which
allows the user to debug which SimObject(s) in the system is failing to drain.
Only enabled for the builds with tracing enabled and is subject to the Drain
debug flag being set at runtime.
Sascha Bischoff [Fri, 1 Apr 2016 15:22:44 +0000 (16:22 +0100)]
sim: Fix clock_domain unserialization
This patch addresses an issue with the unserialization of clock
domains. Previously, the previous performance level was not restored
due to a bug in the code, which detected the post-unserialize update
as superfluous. This patch splits the setting of the clock domain into
two parts. The original interface of perfLevel is retained, but the
actual update takes place in signalPerfLevelUpdate, which is private
to the class. The perfLevel method checks that if the new performance
level is different to the previous performance level, and will only
call signalPerfLevelUpdate if there is a change. Therefore, the
performance level is only updated, and voltage domains notified, if
there is an actual change. The split functionality allows
signalPerfLevelUpdate to be called by startup() to explicitly force an
update post unserialization.
Geoffrey Blake [Tue, 5 Apr 2016 10:29:02 +0000 (05:29 -0500)]
cpu: Query CPU for inst executed from Python
This patch adds the ability for the simulator to query the number of
instructions a CPU has executed so far per hw-thread. This can be used
to enable more flexible periodic events such as taking checkpoints
starting 1s into simulation and X instructions thereafter.
Steve Reinhardt [Fri, 1 Apr 2016 23:38:16 +0000 (16:38 -0700)]
syscall_emul: remove mmapFlagTable
After all this it turns out we don't even use it.
Steve Reinhardt [Fri, 1 Apr 2016 23:38:15 +0000 (16:38 -0700)]
syscall_emul: factor out flag tables into common file
The openFlagTable and mmapFlagTables for emulated Linux
platforms are basically identical, but are specified
repetitively for every platform. Use a common file
that gets included for each platform so that we only
have one copy, making them more consistent and simplifying
changes (like adding #ifdefs).
In the process, made some minor fixes that slipped through
due to previous inconsistencies, and added more #ifdefs
to try to fix building on alternative hosts.
Andreas Sandberg [Wed, 30 Mar 2016 15:21:27 +0000 (16:21 +0100)]
misc: Don't build region.py as a PySource
The style refactor change (style: Refactor the style checker as a
Python package) moved region.py from src/python/m5/util/ to
util/style/. The SConscript update accidentally got lost in that
commit. This commit removes region.py from src/python/SConscript.
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
--HG--
extra : amend_source :
f69b75bf636dd4a4232af3e10c29f7eaa4d59dc8
Andreas Sandberg [Wed, 30 Mar 2016 14:56:02 +0000 (15:56 +0100)]
arm: Clean up m5ops assembly library
The m5ops assembly library contains a lot of repetitive code. This
changeset adds two macros, FOREACH_M5OP and FOREACH_M5_ANNOTATION, to
m5ops.h that simplify architecture-specific implementations. The ARM
and ARMv8 m5op implementations have been updated to use the new
macros.
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Curtis Dunham <curtis.dunham@arm.com>
Andreas Sandberg [Wed, 30 Mar 2016 14:36:50 +0000 (15:36 +0100)]
style: Change maximum line length to 79 characters
The old style guide used to mandate 78 characters as the maximum line
length to accommodate traditional diffs on 80-column terminals. This
is an uncommon use case and it has therefore been decided (see email
thread on gem5-dev [1]) that a maximum length of 79-characters makes
more sense.
[1] http://comments.gmane.org/gmane.comp.emulators.m5.devel/29789
Signed-off-by: Andreas Sandberg <aandreas.sandberg@arm.com>
Reviewed-by: Brandon Potter <brandon.potter@amd.com>
--HG--
rename : util/style.py => util/hgstyle.py
extra : rebase_source :
63efcc4da2585ef8c323d6f322736f64d71742f8
Andreas Sandberg [Wed, 30 Mar 2016 14:36:16 +0000 (15:36 +0100)]
style: Add a style checker that doesn't depend on Mercurial
The current style checker script, hgstyle.py, assumes that it is being
run from Mercurial. This means that it depends on the Mercurial Python
libraries, which aren't necessarily present if using git. This
changeset adds a new style checker script, style.py, that has
been designed to be run from the command line.
The script has support for detecting which revision control system is
used and is able to query both git and Mercurial for changes. This
enables the script to operate on modified regions and/or all of the
modified files in the repository.
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Curtis Dunham <curtis.dunham@arm.com>
Reviewed-by: Steve Reinhardt <steve.reinhardt@amd.com>
--HG--
extra : rebase_source :
2b420aff79d190f32557bc8822518cbc5d93e999
Andreas Sandberg [Wed, 30 Mar 2016 14:35:33 +0000 (15:35 +0100)]
scons: Automatically install the git style hook
Add a check in the main SConscript that installs the git pre-commit
hook in util/ if git is used.
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Curtis Dunham <curtis.dunham@arm.com>
[andreas.sandberg@arm.com: Cleanups suggested by Steve]
Reviewed-by: Steve Reinhardt <steve.reinhardt@amd.com>
--HG--
extra : rebase_source :
4b805cdd74bc5442a65abf8a62e3e341f352c04e
Andreas Sandberg [Wed, 30 Mar 2016 14:33:29 +0000 (15:33 +0100)]
style: Add a git pre-commit hook
Add a git pre-commit hook that verifies that files that are about to
be committed. Since git stages changes into an index and the index
contains the changes that will be committed, the style checker only
looks at the state of files in the index.
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-by: Curtis Dunham <curtis.dunham@arm.com>
Reviewed-by: Steve Reinhardt <steve.reinhardt@amd.com>
--HG--
extra : rebase_source :
22a028bf13524cba188bd7896a0304f4c14ffeeb
Andreas Sandberg [Wed, 30 Mar 2016 14:33:04 +0000 (15:33 +0100)]
style: Add repository helper functions
Add an AbstractRepo class and implementations for git and Mercurial
that provide a common interface to query repository status for style
checkers. The class defines the interfaces to list modified files that
are about to be committed and methods to identify changed regions.
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-by: Curtis Dunham <curtis.dunham@arm.com>
Reviewed-by: Steve Reinhardt <steve.reinhardt@amd.com>
--HG--
rename : util/style.py => util/hgstyle.py
extra : rebase_source :
da1f482a1ecac2b0be437dc400b4a66bd3b301cc
Andreas Sandberg [Wed, 30 Mar 2016 14:32:17 +0000 (15:32 +0100)]
style: Remove style validators
Style validators provide a subset of the style verifier functionality
and are only exposed through the "hg m5format" command. This
functionality seems to be both redundant and unused.
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
--HG--
extra : rebase_source :
f4847ac3ddc86f6684565b65a942e04979972a7b
Andreas Sandberg [Wed, 30 Mar 2016 14:31:23 +0000 (15:31 +0100)]
style: Add a control character checker
Add a style checker that verifies that source code doesn't contain
non-printable (control) characters. The only allowed control
characters are:
* 0x0a / \n: New line
* 0x09 / \t: Tab (the whitespace checker enforces no-tabs for C/C++ files)
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Brandon Potter <brandon.potter@amd.com>
--HG--
extra : rebase_source :
9ba3e2971774a7b3d73cda34bbee1f19c4add746
Andreas Sandberg [Wed, 30 Mar 2016 14:30:32 +0000 (15:30 +0100)]
style: Refactor the style checker as a Python package
Refactor the style checker into a Python module that can be reused by
command line tools that integrate with git. In particular:
* Create a style package in util
* Move style validators from style.py to the style/validators.py.
* Move style verifiers from style.py to the style/verifiers.py.
* Move utility functions (sort_includes, region handling,
file_types) into the style package
* Move generic code from style.py to style/style.py.
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Curtis Dunham <curtis.dunham@arm.com>
Reviewed-by: Steve Reinhardt <steve.reinhardt@amd.com>
--HG--
rename : util/style.py => util/hgstyle.py
rename : util/sort_includes.py => util/style/sort_includes.py
extra : rebase_source :
ad6cf9b9a18c48350dfc7b7c77bea6c5344fb53c
Andreas Sandberg [Wed, 30 Mar 2016 14:30:05 +0000 (15:30 +0100)]
style: Change include sorter to yield one line at a time
The include sorter class normally yields one string per line and
relies on the caller to merge lines into a block of text separated by
newlines. However, there are cases when this isn't true. This makes
diffing using Python's difflib hard. This changeset updates the
include sorter to never do this and always yield one line at a time.
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Curtis Dunham <curtis.dunham@arm.com>
Reviewed-by: Steve Reinhardt <steve.reinhardt@amd.com>
--HG--
extra : rebase_source :
154c9c7e1ebdd77e09fe5f28d0cfddc9e6c6b1eb
Andreas Sandberg [Wed, 30 Mar 2016 14:29:42 +0000 (15:29 +0100)]
scons, style: Rename style.py to hgstyle.py
The Mercurial style checker extensions are currently stored in
style.py. This is not ideal since they won't work with other version
control systems. This changeset renames style.py to hgstyle.py and
adds upgrade code to scons that automatically updates the hooks in
hgrc.
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-by: Curtis Dunham <curtis.dunham@arm.com>
Reviewed-by: Nathanael Premillieu <nathananel.premillieu@arm.com>
Reviewed-by: Steve Reinhardt <steve.reinhardt@amd.com>
--HG--
rename : util/style.py => util/hgstyle.py
extra : rebase_source :
ee8107ef245901371b368b7c2046ecdd89e3ff4c
Andreas Sandberg [Wed, 30 Mar 2016 14:29:02 +0000 (15:29 +0100)]
style: Remove unsupported style.py commands
Remove the unsupported style.py subcommands (fixwhite, chkwhite),
which leaves the chkformat command as the only remaining
command. Since the script now only supports one command, remove the
sub-command support altogether.
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-by: Curtis Dunham <curtis.dunham@arm.com>
Reviewed-by: Nathanael Premillieu <nathananel.premillieu@arm.com>
--HG--
extra : rebase_source :
548081a5f5358064bffd941b51dd895cff1e2df8
Andreas Sandberg [Wed, 30 Mar 2016 09:52:25 +0000 (10:52 +0100)]
kvm: Add an option to force context sync on kvm entry/exit
This changeset adds an option to force the kvm-based CPUs to always
synchronize the gem5 thread context representation on entry/exit into
the kernel. This is very useful for debugging. Unfortunately, it is
also the only way to get reliable register contents when using remote
gdb functionality. The long-term solution for the latter would be to
implement a kvm-specific thread context.
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Curtis Dunham <curtis.dunham@arm.com>
Reviewed-by: Alexandru Dutu <alexandru.dutu@amd.com>
Andreas Sandberg [Tue, 29 Mar 2016 15:36:42 +0000 (16:36 +0100)]
copyright: Update copyright in sort_includes.py
The following changes introduced substantial changes to sort_includes.py:
- hg:
84b4d6af0ecc - util: Fix state leakage in ...
- hg:
e2f9644a7738 - style: Update the style checker to handle new ...
Since the file didn't include a copyright header at the time, I never
added the correct ARM copyright notice. This changeset adds the
correct copyright notice.
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Nathan Binkert [Tue, 29 Mar 2016 04:42:46 +0000 (21:42 -0700)]
copyright: add copyright missing from files I created
Andreas Sandberg [Thu, 24 Mar 2016 11:11:34 +0000 (11:11 +0000)]
style: Strip newline when checking lines
The style checker incorrectly includes newlines when checking lines of
code, which effectively decreases the column limit by 1. This
changeset strips the newline character from before calling line
checkers.
Change-Id: I0a8c7707ece57d782d11cc86db4b8064db291ce0
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Andreas Sandberg [Mon, 21 Mar 2016 15:54:58 +0000 (15:54 +0000)]
arm: Refactor the TLB test interface
Refactor the TLB and page table walker test interface to use a dynamic
registration mechanism. Instead of patching a couple of empty methods
to wire up a TLB tester, this change allows such testers to register
themselves using the setTestInterface() method.
jkalamat [Mon, 21 Mar 2016 15:26:23 +0000 (11:26 -0400)]
gpu-compute: remove unused variable from scoreboard check stage
appease clang by removing the unused private member variable,
'numGlbMemPipes', from the scoreboard check stage
Andreas Hansson [Sun, 20 Mar 2016 10:38:34 +0000 (06:38 -0400)]
cpu: warn if TrafficGen is suppressing a large numer of packets
Add a basic warning for every 10000 packet that is suppressed to alert
the user.
Brandon Potter [Thu, 17 Mar 2016 17:34:27 +0000 (10:34 -0700)]
base: add symbol support for dynamic libraries
Libraries are loaded into the process address space using the
mmap system call. Conveniently, this happens to be a good
time to update the process symbol table with the library's
incoming symbols so we handle the table update from within the
system call.
This works just like an application's normal symbols. The only
difference between a dynamic library and a main executable is
when the symbol table update occurs. The symbol table update for
an executable happens at program load time and is finished before
the process ever begins executing. Since dynamic linking happens
at runtime, the symbol loading happens after the library is
first loaded into the process address space. The library binary
is examined at this time for a symbol section and that section
is parsed for symbol types with specific bindings (global,
local, weak). Subsequently, these symbols are added to the table
and are available for use by gem5 for things like trace
generation.
Checkpointing should work just as it did previously. The address
space (and therefore the library) will be recorded and the symbol
table will be entirely recorded. (It's not possible to do anything
clever like checkpoint a program and then load the program back
with different libraries with LD_LIBRARY_PATH, because the
library becomes part of the address space after being loaded.)
Brandon Potter [Thu, 17 Mar 2016 17:33:02 +0000 (10:33 -0700)]
base: style cleanup for ObjectFile and ElfObject
Steve Reinhardt [Thu, 17 Mar 2016 17:32:53 +0000 (10:32 -0700)]
stats: update stats for ld.so support
Additional auxv entries leads to more instructions in start-up
while walking the list, along with different cache conflicts
wrt stack entries.
Brandon Potter [Thu, 17 Mar 2016 17:31:03 +0000 (10:31 -0700)]
base: support dynamic loading of Linux ELF objects in SE mode
Steve Reinhardt [Thu, 17 Mar 2016 17:30:58 +0000 (10:30 -0700)]
stats: update stats for mmap changes
Brandon Potter [Thu, 17 Mar 2016 17:30:33 +0000 (10:30 -0700)]
syscall_emul: update x86 mmap base address
Steve Reinhardt [Thu, 17 Mar 2016 17:29:32 +0000 (10:29 -0700)]
syscall_emul: move mmapGrowsDown() to LiveProcess
The mmapGrowsDown() method was a static method on the OperatingSystem
class (and derived classes), which worked OK for the templated syscall
emulation methods, but made it hard to access elsewhere. This patch
moves the method to be a virtual function on the LiveProcess method,
where it can be overridden for specific platforms (for now, Alpha).
This patch also changes the value of mmapGrowsDown() from being false
by default and true only on X86Linux32 to being true by default and
false only on Alpha, which seems closer to reality (though in reality
most people use ASLR and this doesn't really matter anymore).
In the process, also got rid of the unused mmap_start field on
LiveProcess and OperatingSystem mmapGrowsUp variable.
Brandon Potter [Thu, 17 Mar 2016 17:25:53 +0000 (10:25 -0700)]
syscall_emul: fix bugs for mmap2 system call and x86-32 syscalls
Steve Reinhardt [Thu, 17 Mar 2016 17:25:11 +0000 (10:25 -0700)]
stats: update stats for mmap() change.
SE O3 runs see an additional reg read per mmap() call.
Brandon Potter [Thu, 17 Mar 2016 17:24:17 +0000 (10:24 -0700)]
syscall_emul: extend mmap system call to support file backed mmaps
For O3, which has a stat that counts reg reads, there is an additional
reg read per mmap() call since there's an arg we no longer ignore.
Otherwise, stats should not be affected.
Brandon Potter [Thu, 17 Mar 2016 17:22:39 +0000 (10:22 -0700)]
syscall_emul: add many Linux kernel flags
Brandon Potter [Thu, 17 Mar 2016 17:22:39 +0000 (10:22 -0700)]
syscall_emul: rename OpenFlagTransTable struct
The structure definition only had the open system call flag set in mind when
it was named, so we rename it here with the intention of using it to define
additional tables to translate flags for other system calls in the future.
Alexandru Dutu [Thu, 17 Mar 2016 17:22:39 +0000 (10:22 -0700)]
syscall_emul: add extra debug support for syscalls
Breaks the debug output from system calls into two levels: Base and Verbose.
A macro is added specifically for system calls which allows developers to
easily add new debug messages in a consistent manner. The macro also contains
a field to print thread IDs along with the CPU ID.
Brandon Potter [Thu, 17 Mar 2016 17:22:39 +0000 (10:22 -0700)]
syscall_emul, style: refactor lseek
Brandon Potter [Thu, 17 Mar 2016 17:22:39 +0000 (10:22 -0700)]
syscall_emul, style: fix newline issue inside assert
Andreas Hansson [Thu, 17 Mar 2016 13:51:22 +0000 (09:51 -0400)]
mem: Adjust cache queue reserve to more conservative values
The cache queue reserve is there as an overflow to give us enough
headroom based on when we block the cache, and how many transactions
we may already have accepted before actually blocking. The previous
values were probably chosen to be "big enough", when we actually know
that we check the MSHRs after every single allocation, and for the
write buffers we know that we implicitly may need one entry for every
outstanding MSHR.
* * *
mem: Adjust cache queue reserve to more conservative values
The cache queue reserve is there as an overflow to give us enough
headroom based on when we block the cache, and how many transactions
we may already have accepted before actually blocking. The previous
values were probably chosen to be "big enough", when we actually know
that we check the MSHRs after every single allocation, and for the
write buffers we know that we implicitly may need one entry for every
outstanding MSHR.
Andreas Hansson [Thu, 17 Mar 2016 13:51:21 +0000 (09:51 -0400)]
stats: Bump stats to match cache changes
Update stats to match current behaviour. As a result of the earlier
conflict check we are seeing a few prefetch requests being ignored
before being sent as upward snoops.
Andreas Hansson [Thu, 17 Mar 2016 13:51:18 +0000 (09:51 -0400)]
mem: Create a separate class for the cache write buffer
This patch breaks out the cache write buffer into a separate class,
without affecting any stats. The goal of the patch is to avoid
encumbering the much-simpler write queue with the complex MSHR
handling. In a follow on patch this simplification allows us to
implement write combining.
The WriteQueue gets its own class, but shares a common ancestor, the
generic Queue, with the MSHRQueue.
Steve Reinhardt [Wed, 16 Mar 2016 20:03:49 +0000 (13:03 -0700)]
stats: overdue updates to long regressions
Andreas Sandberg [Wed, 16 Mar 2016 17:20:00 +0000 (17:20 +0000)]
misc: Add a gitignore file based on the current hgignore
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Gabor Dozsa [Wed, 16 Mar 2016 16:23:42 +0000 (16:23 +0000)]
misc: Fix argument handling for m5 initparam util
Nathanael Premillieu [Wed, 16 Mar 2016 16:08:24 +0000 (16:08 +0000)]
arm: Fix disasm printing
Fix the printDataInst function to properly print the immediate value.
Steve Reinhardt [Mon, 14 Mar 2016 00:47:33 +0000 (17:47 -0700)]
scons: fix building in non-standard locations
It's apparently not widely known that our scons scripts allow you to
put the build directory wherever you want; not only does it not have
to be immediately under the root of your repo, it doesn't even have
to be underneath the root at all. (For example, sometimes it's useful
to build on a local disk if your repo is on a slow NFS mount.)
I point this out because this functionality has been broken for close
to two years but no one seems to have noticed yet. This patch fixes
an assumption that crept in in changeset
be0e1724eb39 (May 09 2014)
that the build dir would be immediately under the top level of the
repo, preventing builds anywhere else.
Steve Reinhardt [Thu, 18 Feb 2016 15:42:03 +0000 (10:42 -0500)]
stats: update gpu-ruby-GPU_RfO stats
Output changed way back in this cset:
changeset: 11345:
b6a66a90e0a1
user: John Kalamatianos <john.kalamatianos@amd.com>
summary: gpu: fix bugs with MemFence, Flat Instrs and Resource utilization
Andreas Hansson [Tue, 8 Mar 2016 22:51:02 +0000 (17:51 -0500)]
configs: Add a lat_mem_rd style test script
This patch adds a config script that broadly replicates the behaviour
of lat_mem_rd. The test is based on traffic generators, and as such we
simply randomise addresses in increasingly large ranges, and play them
back using the trace functionality of the traffic generator.
The test script is accompanied by a post-processing and visualisation
script. At the moment no configurability is added to tweak the memory
hierarchy, but a follow on patch could easily extend the
functionality.
Andreas Hansson [Tue, 8 Mar 2016 22:50:58 +0000 (17:50 -0500)]
syscall_emul: Fix erroneous use of delete
clang correctly points out an erroneous use of delete.
David Guillen Fandos [Wed, 17 Jun 2015 15:49:40 +0000 (16:49 +0100)]
sim: Add voltage() function to clocked_object
Adding voltage function which returns the current voltage
for a given clocked object. It's handy for power models and
similar stuff that need to retrieve voltage. Function
frequency() is already there, so I see no reason for not having
this one too.
Rekai Gonzalez Alberquilla [Tue, 5 May 2015 15:47:24 +0000 (16:47 +0100)]
cpu: Change literal integer constants to meaningful labels
fu_pool and inst_queue were using -1 for "no such FU" and -2 for "all those
FUs are busy at the moment" when requesting for a FU and replying. This
patch introduces new constants NoCapableFU and NoFreeFU respectively.
In addition, the condition (idx == -2 || idx != -1) is equivalent to
(idx != -1), so this patch also simplifies that.
--HG--
extra : rebase_source :
4833717b9d1e09d7594d1f34f882e13fc4b86846
Andreas Hansson [Sat, 5 Mar 2016 01:14:10 +0000 (20:14 -0500)]
base: Fix gpu-compute output stream creation
Match changes in output stream.
Andreas Sandberg [Fri, 27 Nov 2015 14:52:10 +0000 (14:52 +0000)]
kvm: Shutdown KVM and disconnect performance counters on fork
We can't/shouldn't use KVM after a fork since the child and parent
probably point to the same VM. Knowing the exact effects of this is
hard, but they are likely to be messy. We also disconnect the
performance counters attached to the guest. This works around what
seems to be a kernel bug where spurious SIGIOs get delivered to the
forked child process.
Signed-off-by: Andreas Sandberg <andreas@sandberg.pp.se>
[sascha.bischoff@arm.com: Rebased patches onto a newer gem5 version]
Signed-off-by: Sascha Bischoff <sascha.bischoff@arm.com>
[andreas.sandberg@arm.com: Fatal if entering KVM in child process ]
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Andreas Sandberg [Thu, 26 Nov 2015 10:11:57 +0000 (10:11 +0000)]
sim: Add support for forking
This changeset adds forking capabilities to the gem5 python scripts. A fork
method is added to simulate.py. This method is responsible for forking the
simulator itself, and will direct all output files to a new output directory
based on the fork sequence number. The default name of the output directory is
the same as the parent with the suffix ".fN" added where N is the fork sequence
number. The fork method provides the option to specify if the system should be
drained prior to forking, or not. By default the system is drained to ensure
that there are no in-flight transactions.
When forking the simulator, the fork method returns the PID of the child
process, or returns 0 if running in the child. This is in line with the standard
Python forking interface.
Signed-off-by: Andreas Sandberg <andreas@sandberg.pp.se>
[sascha.bischoff@arm.com: Rebased patches onto a newer gem5 version]
Signed-off-by: Sascha Bischoff <sascha.bischoff@arm.com>
[andreas.sandberg@arm.com: Updated to comply with modern draining semantics ]
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Andreas Sandberg [Thu, 26 Nov 2015 10:11:52 +0000 (10:11 +0000)]
dev: Add post-fork handling for disk images
This changeset adds support for notifying the disk images that the simulator has
been forked. We need to disable the saving of the CoW disk image from the child
process, and we need to make sure that systems which use a raw disk image are
not allowed to fork to avoid two or more gem5 processes writing to the same disk
image.
Signed-off-by: Andreas Sandberg <andreas@sandberg.pp.se>
[sascha.bischoff@arm.com: Rebased patches onto a newer gem5 version]
Signed-off-by: Sascha Bischoff <sascha.bischoff@arm.com>
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Andreas Sandberg [Thu, 26 Nov 2015 10:03:43 +0000 (10:03 +0000)]
sim: Add support for notifying Drainable objects of a fork
When forking a gem5 process, some objects need to clean up resources
(mainly file descriptions) shared between the child and the parent of
the fork. This changeset adds the notifyFork() method to Drainable,
which is called in the child process.
Signed-off-by: Andreas Sandberg <andreas@sandberg.pp.se>
[sascha.bischoff@arm.com: Rebased patches onto a newer gem5 version]
Signed-off-by: Sascha Bischoff <sascha.bischoff@arm.com>
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Andreas Sandberg [Fri, 27 Nov 2015 14:41:59 +0000 (14:41 +0000)]
base: Add support for changing output directories
This changeset adds support for changing the simulator output
directory. This can be useful when the simulation goes through several
stages (e.g., a warming phase, a simulation phase, and a verification
phase) since it allows the output from each stage to be located in a
different directory. Relocation is done by calling core.setOutputDir()
from Python or simout.setOutputDirectory() from C++.
This change affects several parts of the design of the gem5's output
subsystem. First, files returned by an OutputDirectory instance (e.g.,
simout) are of the type OutputStream instead of a std::ostream. This
allows us to do some more book keeping and control re-opening of files
when the output directory is changed. Second, new subdirectories are
OutputDirectory instances, which should be used to create files in
that sub-directory.
Signed-off-by: Andreas Sandberg <andreas@sandberg.pp.se>
[sascha.bischoff@arm.com: Rebased patches onto a newer gem5 version]
Signed-off-by: Sascha Bischoff <sascha.bischoff@arm.com>
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Prakash Ramrakhyani [Tue, 1 Mar 2016 01:13:15 +0000 (19:13 -0600)]
util: update Java JNI interface to m5ops
Synchronize with
ab19693da "pseudo inst,util: Add optional key to initparam pseudo instruction"
Stephan Diestelhorst [Mon, 10 Aug 2015 10:25:52 +0000 (11:25 +0100)]
mem, cpu: Add assertions to snoop invalidation logic
This patch adds assertions that enforce that only invalidating snoops
will ever reach into the logic that tracks in-order load completion and
also invalidation of LL/SC (and MONITOR / MWAIT) monitors. Also adds
some comments to MSHR::replaceUpgrades().
Krishnendra Nathella [Sun, 19 Jul 2015 20:03:30 +0000 (15:03 -0500)]
cpu: Fix LLSC atomic CPU wakeup
Writes to locked memory addresses (LLSC) did not wake up the locking
CPU. This can lead to deadlocks on multi-core runs. In AtomicSimpleCPU,
recvAtomicSnoop was checking if the incoming packet was an invalidation
(isInvalidate) and only then handled a locked snoop. But, writes are
seen instead of invalidates when running without caches (fast-forward
configurations). As as simple fix, now handleLockedSnoop is also called
even if the incoming snoop packet are from writes.
Mitch Hayenga [Tue, 1 Mar 2016 01:13:13 +0000 (19:13 -0600)]
arm: Squash after returning from exceptions in v7
Properly done for the ERET instruction in v8, but not for v7.
Many control register changes are only visible after explicit
instruction synchronization barriers or exception entry/exit.
This means mode changing instructions should squash any
younger in-flight speculative instructions.