configure.ac: Reorder arguments in radeon_llvm_check

Use the same order as llvm_check_version_for.

Signed-off-by: Tobias Droste <tdroste@gmx.de>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>

configure.ac: Move radv check to the Vulkan section

This moves the LLVM check for radv to the corresponding driver section.
No functional change.

Signed-off-by: Tobias Droste <tdroste@gmx.de>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>

configure.ac: Move LLVM ac_subst closer to usage

This moves llvm_set_environment_variables to its final destination
and moves all the LLVM AC_SUBST() below the function call.
No functional change.

Signed-off-by: Tobias Droste <tdroste@gmx.de>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>

configure.ac: Move oCL LLVM checks to the oCL section

The LLVM checks can be anywhere below line 1161 now.
Move the openCL LLVM checks to the section with the other openCL checks.
No functional change.

Signed-off-by: Tobias Droste <tdroste@gmx.de>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
[Emil Velikov: s/ipos/ipo/, drop "yes" argument from llvm_add_component]
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>

configure.ac: Move llvm_set_environment_variables higher.

This moves the function to get the LLVM environment variables higher
in the file. It still needs to be below the "--enable-opencl" because
it uses $enable_opencl.
It can be called without condition now as it only throws errors if
openCL is enabled.

v5:
HAVE_MESA_LLVM is only used for gallium. Rename it to HAVE_GALLIUM_LLVM.
In order to only link LLVM when it is needed, HAVE_GALLIUM_LLVM is only
set if "$enable-gallium-llvm" is yes.

Signed-off-by: Tobias Droste <tdroste@gmx.de>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>

configure.ac: Remove swr_llvm_check()

No need for an additional function here.
Use the same style for LLVM checks as the other drivers
(e.g. r300, llvmpipe) that don't need a load of other checks.
Instead of open conding the LLVM version check, use the
function used by other drivers.

"enable_gallium_llvm" is checked by gallium_require_llvm().

Signed-off-by: Tobias Droste <tdroste@gmx.de>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>

configure.ac: Check gallium LLVM version in gallium_require_llvm

This moves the LLVM version check to the helper function
gallium_require_llvm() and uses the llvm_check_version_for() helper
instead of open conding the LLVM version check.

gallium_require_llvm is functionally the same as before, because
"enable_gallium_llvm" is only set to "yes" if the host cpu is x86:

if test "x$enable_gallium_llvm" = xauto; then
    case "$host_cpu" in
    i*86|x86_64|amd64) enable_gallium_llvm=yes;;
    esac
fi

This function is also only called now when needed.
Before this patch llvmpipe would call this as soon as LLVM is
installed. Now it only gets called by llvmpipe if gallium
LLVM is actually enabled (i.e. only on x86).

Both reasons mentioned above remove the need to check host cpu
in the gallium_require_llvm function.

Signed-off-by: Tobias Droste <tdroste@gmx.de>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>

configure.ac: Use short names for r600 und r300

There are no non gallium r300 and r600 drivers anymore.
No need to explicilty mention gallium here.
Just cosmetics, no functional change.

Signed-off-by: Tobias Droste <tdroste@gmx.de>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>

configure.ac: Remove useless oCL LLVM check

This is handled by "llvm_check_version_for" for openCL.

Signed-off-by: Tobias Droste <tdroste@gmx.de>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>

configure.ac: Move llvm-config searching outside the function

There's no harm in always searching llvm-config.
This way it's available as soon as possible for all functions.

Signed-off-by: Tobias Droste <tdroste@gmx.de>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>

configure.ac: Move LLVM functions to the top

This just moves code around so that all LLVM related stuff is at the
top of the file in the correct order.
No functional change.

Signed-off-by: Tobias Droste <tdroste@gmx.de>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>

configure.ac: Move LLVM version check to the top

A function with the LLVM version checked is moved to the top.
The function is called where the old code was.
No functional change.

Signed-off-by: Tobias Droste <tdroste@gmx.de>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
[Emil Velikov: s/ipos/ipo/, drop "yes" argument from llvm_add_component]
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>

configure.ac: Use new helper function for LLVM

Use the new helper function to add LLVM targets and components.
The components are added one by one to later find out which component
is missing in case there is one.

Signed-off-by: Tobias Droste <tdroste@gmx.de>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
[Emil Velikov: s/ipos/ipo/, drop "yes" argument from llvm_add_component]
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>

configure.ac: Use new llvm_add_default_components

Signed-off-by: Tobias Droste <tdroste@gmx.de>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>

configure.ac: Add helper function for targets/components

Add functions to add and check targets/components.
Not used in this patch.

Signed-off-by: Tobias Droste <tdroste@gmx.de>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>

configure.ac: Don't search llvm-config if it's known

This way LLVM_CONFIG can bet set from an env variable if it's outside
the $llvm_prefix.

This is not a must, but it helps testing.

Signed-off-by: Tobias Droste <tdroste@gmx.de>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>

st/va: fix gop size for rate control

The gop_size in rate control is the budget window for internal rate
control calculation, and shouldn't always equal to idr period. Define
a coefficient to let budget window contains a number of idr period for
proper rate control calculation. Adjust the number of i/p frame remaining
accordingly.

Fixes: https://bugs.freedesktop.org/show_bug.cgi?id=98005
Signed-off-by: Boyuan Zhang <boyuan.zhang@amd.com>
Acked-by: Christian König <christian.koenig@amd.com>

st/va: force to submit two consecutive single jobs

The gop_size in rate control is the budget window for internal rate
control calculation, and shouldn't always equal to idr period. Define
a coefficient to let budget window contains a number of idr period for
proper rate control calculation. Adjust the number of i/p frame remaining
accordingly.

v2: fixed regression issues introduced by previous version

Fixes: https://bugs.freedesktop.org/show_bug.cgi?id=98005
Signed-off-by: Boyuan Zhang <boyuan.zhang@amd.com>
Acked-by: Christian König <christian.koenig@amd.com>

st/vdpau: fix compiler warning in vlVdpVideoMixerRender

Signed-off-by: Nayan Deshmukh <nayan26deshmukh@gmail.com>
Reviewed-by: Christian König <christian.koenig@amd.com>

i965: Release aux buffer when disabling ccs

Otherwise subsequent render cycles keep on using compression
and/or fast clear.

Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

ac/nir: Only use the first component for SSBO atomics.

Signed-off-by: Bas Nieuwenhuizen <basni@google.com>
Reviewed-by: Dave Airlie <airlied@redhat.com>

radv: fix another regression since shadow fixes.

This fixes:
dEQP-VK.glsl.texture_gather.basic.2d.depth32f.*

Cc: "13.0" <mesa-stable@lists.freedesktop.org>
Signed-off-by: Dave Airlie <airlied@redhat.com>

spirv: Builtin Layer is an input for fragment shaders

This change makes it so we emit a load_input intrinsic when Layer
is read in a fragment shader.

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>

swr: Fix active_queries count

The active_query count was incorrect for query types that don't require
a begin_query.  Removed the unnecessary assert.

Reviewed-by: Tim Rowley <timothy.o.rowley@intel.com>

swr: Fix type to match parameters of std::max()

Include propagation of comparisons further down.

Reviewed-by: Tim Rowley <timothy.o.rowley@intel.com>

swr: [rasterizer jitter] include cstdarg in builder_misc.cpp

Fixes build problem with llvm-svn.

v2: use cstdarg instead of stdarg.h

Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>

nir: Get rid of nir_constant_data

This has bothered me for about as long as NIR has been around.  Why do we
have two different unions for constants?  No good reason other than one of
them is a direct port from GLSL IR.

Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>

Revert "st/mesa: get Version from gl_program rather than gl_shader_program"

This reverts commit 6bf63b011992dbbc899a28bde5692070dbcf965a.

A patch that adds a reference to gl_shader_program_data to gl_program
needs to land befor this one.

st/mesa: get Version from gl_program rather than gl_shader_program

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

st/mesa/glsl: move Version to gl_shader_program_data

This is mostly just used during linking however the st uses it
when updating textures.

In order to store gl_program in the CurrentProgram array
rather than gl_shader_program we need to move this field to
the shared gl_shader_program_data struct.

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

freedreno: no-op render when we need a fence

If app tries to create a fence but there is no rendering to submit, we
need a dummy/no-op submit.  Use a string-marker for the purpose.. mostly
since it avoids needing to realize that the packet format changes in
later gen's (so one less place to fixup for a5xx).

Signed-off-by: Rob Clark <robdclark@gmail.com>

freedreno: native fence fd support

Signed-off-by: Rob Clark <robdclark@gmail.com>

freedreno: some fence cleanup

Prep-work for next patch, mostly move to tracking last_fence as a
pipe_fence_handle (created now only in fd_gmem_render_tiles()), and a
bit of superficial renaming.

Signed-off-by: Rob Clark <robdclark@gmail.com>

gallium: support for native fence fd's

This enables gallium support for EGL_ANDROID_native_fence_sync, for
drivers which support PIPE_CAP_NATIVE_FENCE_FD.

Signed-off-by: Rob Clark <robclark@freedesktop.org>

gallium: wire up server_wait_sync

This will be needed for explicit synchronization with devices outside
the gpu, ie. EGL_ANDROID_native_fence_sync.

Signed-off-by: Rob Clark <robclark@freedesktop.org>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>

egl: add EGL_ANDROID_native_fence_sync

With fixes from Chad squashed in, plus fixes for issues that Rafael
found while writing piglit tests.

Signed-off-by: Rob Clark <robclark@freedesktop.org>
Tested-by: Rafael Antognolli <rafael.antognolli@intel.com>
Reviewed-by: Chad Versace <chadversary@chromium.org>
Tested-by: Chad Versace <chadversary@chromium.org>

dri: extend fence extension to support native fd fences

Required to implement EGL_ANDROID_native_fence_sync.

Signed-off-by: Rob Clark <robclark@freedesktop.org>
Tested-by: Rafael Antognolli <rafael.antognolli@intel.com>
Reviewed-by: Chad Versace <chadversary@chromium.org>
Tested-by: Chad Versace <chadversary@chromium.org>

egl: un-fallthrough sync attr parsing

Doesn't work so well when you start having more than one possible
attrib.  Prep-work for next patch.

Signed-off-by: Rob Clark <robdclark@gmail.com>
Tested-by: Rafael Antognolli <rafael.antognolli@intel.com>
Reviewed-by: Chad Versace <chadversary@chromium.org>
Tested-by: Chad Versace <chadversary@chromium.org>

egl: initialize SyncCondition after attr parsing

Reduce the noise in the next patch.  For EGL_SYNC_NATIVE_FENCE_ANDROID
the sync condition is conditional on EGL_SYNC_NATIVE_FENCE_FD_ANDROID
attribute.

Signed-off-by: Rob Clark <robclark@freedesktop.org>
Tested-by: Rafael Antognolli <rafael.antognolli@intel.com>
Reviewed-by: Chad Versace <chadversary@chromium.org>
Tested-by: Chad Versace <chadversary@chromium.org>

tgsi: store writes_primid when scanning tgsi

Reviewed-by: Marek Olšák <marek.olsak@amd.com>

mesa: only verify that enabled arrays have backing buffers

We were previously also verifying that no backing buffers were available
when an array wasn't enabled. This is has no basis in the spec, and it
causes GLupeN64 to fail as a result.

Fixes: c2e146f487 ("mesa: error out in indirect draw when vertex bindings mismatch")
Cc: mesa-stable@lists.freedesktop.org
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Timothy Arceri <timothy.arceri@collabora.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>

vc4: Avoid false scheduling dependencies for LOAD_IMMs.

Noticed in shaders with branching, where we ended up scheduling delay
slots near the start of a block for the uniforms reset setup.

total instructions in shared programs: 93970 -> 93951 (-0.02%)
instructions in affected programs:     3117 -> 3098 (-0.61%)

3DMMES performance +0.423087% +/- 0.133521% (n=9,10)

vc4: Try to schedule QIR instructions between writing to and reading math.

This helps us get the delay slots between SFU writes and reads filled.

total instructions in shared programs: 94494 -> 93970 (-0.55%)
instructions in affected programs:     59206 -> 58682 (-0.89%)

3DMMES performance +1.89967% +/- 0.157611% (n=10,9)

vc4: Improve interleaving of texture coordinates vs results.

The latency_between was trying to handle the delay between the coordinate
write ("before") and the corresponding sample read ("after"), but we were
handing in the two instructions swapped.

This meant that we tried to fit things between a tex_s and its *preceding*
tex_result.  This made us only interleave normal texture coordinates by
accident, and pessimized UBO reads by pushing the tex_result collection
earlier until there was nothing but it (and then its preceding coordinate
setup) left.

In addition to latency reduction, things end up packing better (probably
due to reduced live ranges of the texture results):

total instructions in shared programs: 98121 -> 94775 (-3.41%)
instructions in affected programs:     91196 -> 87850 (-3.67%)

3DMMES performance +1.15569% +/- 0.124714% (n=8,10)

vc4: Fix stray "." on no-op MUL packs.

This happened when the PM bit was set for R4 unpacks, where the MUL pack
was NOP.

vc4: Allow merging instructions with SF set where the other writes NOP.

I'm not sure how I managed to write the SF merge code
(7d8b79f398f18ed7bb48a74b1b82950e2f08abad) without allowing merges with
NOPs.  *Everything* we try to merge with will have a NOP on one or the
other side of the instruction, and that's why that commit showed no
benefit.

total instructions in shared programs: 99347 -> 95128 (-4.25%)
instructions in affected programs:     91906 -> 87687 (-4.59%)

3DMMES performance +2.57105% +/- 0.135276% (n=6,8)

vc4: In a loop break/continue, jump if everyone has taken the path.

This should be a win for most loops, which tend to have uniform control
flow.

More importantly, it exposes important information to live variables: that
the break/continue here means that our jump target may have access to
values that were live on our input.  Previously, we were just setting the
exec mask and letting control flow fall through, so an intervening def
between the break and the end of the loop would appear to live variables
as if it screened off the variable, when it didn't actually.

Fixes a regression in glsl-vs-loop-redundant-condition.shader_test when a
perturbing of register allocation caused a live variable to get stomped.

Cc: 13.0 <mesa-stable@lists.freedesktop.org>

anv: expose support for VK_KHR_sampler_mirror_clamp_to_edge

This is already supported in genX_state.c, expose the extension string.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>

anv/cmd_buffer: Actually use the stencil dimension

In an attempt to fix 3DSTATE_DEPTH_BUFFER for stencil-only cases, I
accidentally kept setting the SurfaceType to 2D in the stencil-only case
thanks to a copy+paste error.

Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>

swr: add streamout buffer offset into pBuffer pointer

The buffer_size does not take the offset into account. Just add the
offset into the pointer which lines up the structures much better.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Tim Rowley <timothy.o.rowley@intel.com>

swr: fix assertion for max number of so targets

The number has to be less than or equal to the max, not just less than.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Tim Rowley <timothy.o.rowley@intel.com>

swr: properly report max number of SO components

The components count the number of individual values, not the number of
slots.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Tim Rowley <timothy.o.rowley@intel.com>

swr: turn off queries around blits

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Tim Rowley <timothy.o.rowley@intel.com>

swr: don't advertise stream pause/resume

There is no support for resuming streamout. Furthermore, this also
controls glDrawTransformFeedback functionality which requires the same
ability to query how many primitives were sent out of TF.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Tim Rowley <timothy.o.rowley@intel.com>

swr: fix range computation for instanced client-side arrays

We need to take the instance divisor and number of instances into
account for instanced client-side arrays, rather than the vertex
parameters.

Loosely based on the comparable nvc0 logic.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>

swr: [rasterizer memory] assert when trying to convert an unknown format

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Tim Rowley <timothy.o.rowley@intel.com>

swr: remove warning about multi-layer surfaces

We now support clearing these, and actually rendering to multiple layers
would require GS support, which will fail in much more spectacular ways
for now. Once that is hooked up, there won't be anything else to do
here.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Tim Rowley <timothy.o.rowley@intel.com>

swr: [rasterizer core] don't attempt to load another RTAI when storing

Since we don't pass a renderTargetArrayIndex in, and the current hot
tile may be for a different index, we may end up loading the RTAI=0 into
the hot tile for no reason.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Tim Rowley <timothy.o.rowley@intel.com>

radeonsi: document a CP DMA bug that doesn't need a workaround yet

This one is easy to miss, because it's not documented in any internal doc.

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

radeonsi: apply the double EVENT_WRITE_EOP workaround to VI as well

Internal docs don't mention it, but they also don't mention that the bug
has been fixed (like other CI bugs fixed in VI).

Vulkan does this too.

v2: also update r600_gfx_write_fence_dwords

Cc: 13.0 <mesa-stable@lists.freedesktop.org>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com> (v1)

radeonsi: add a tess+GS hang workaround for VI dGPUs

ported from Vulkan

Cc: 13.0 <mesa-stable@lists.freedesktop.org>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

radeonsi: don't apply the Z export bug workaround to Hainan

not needed

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

radeonsi: apply a tessellation bug workaround for SI

Cc: 13.0 <mesa-stable@lists.freedesktop.org>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

radeonsi: apply a TC L1 write corruption workaround for SI

Cc: 13.0 <mesa-stable@lists.freedesktop.org>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

radeonsi: apply a multi-wave workgroup SPI bug workaround to affected CIK chips

All codepaths are handled except for clover.

Cc: 13.0 <mesa-stable@lists.freedesktop.org>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

radeonsi: consolidate max-work-group-size computation

The next commit will need this.

Cc: 13.0 <mesa-stable@lists.freedesktop.org>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

mesa: reset linked_stages bitmask when re-linking

34953f8907fdd added this bitmask but it wasn't being reset when
a program was relinked. If a stage was removed from the new
program then it could case a crash as we expect the linked shader
for that stage to not be null.

Fixes crashes in:
ESEXT-CTS.tessellation_shader.single.xfb_captures_data_from_correct_stage
ES31-CTS.core.tessellation_shader.single.xfb_captures_data_from_correct_stage

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Dave Airlie <airlied@redhat.com>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=98917

freedreno/a5xx: fix negative branches

Looks like immed branch offset size increased again.. making what we
think is a small negative number look to hw like a huge positive number.
And things go badly when shader tries to jump to hyperspace.

Signed-off-by: Rob Clark <robdclark@gmail.com>

freedreno: fix android build with a5xx

Android doesn't build all the files that normal linux/autotools build
does (mainly standalond ir3_compiler).. but possibly we should pull
C_SOURCES + aNxx_SOURCES into a single variable picked up by both
Android.mk and Makefile.am?  (Suggested by Rob H.)

Signed-off-by: Rob Clark <robdclark@gmail.com>

freedreno/a5xx: fix discard

Signed-off-by: Rob Clark <robdclark@gmail.com>

anv: Prefer in-tree headers to out-of-tree headers

Set the include paths to consider in-tree headers before out-of-tree
headers.

Avoids the build failing due to stale headers being present in
$prefix. Previosuly 'make -ki install' or something similar was required
to update the out-of-tree headers to allow the build to succeed.

Also avoids having to rebuild the entire thing after every 'make
install'.

Cc: Rob Clark <robdclark@gmail.com>
Cc: Jason Ekstrand <jason.ekstrand@intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Chad Versace <chadversary@chromium.org>

freedreno/a5xx: initial support

Signed-off-by: Rob Clark <robdclark@gmail.com>

freedreno: update generated headers

Pull in a5xx

Signed-off-by: Rob Clark <robdclark@gmail.com>

freedreno: make gmem tile size alignment configurable

a5xx seems to prefer 64 pixel alignment, in at least some cases.  Make
this configurable per generation.

Signed-off-by: Rob Clark <robdclark@gmail.com>

freedreno/ir3: don't offset inloc by 8

On a3xx/a4xx, the SP_VS_VPC_DST_REG.OUTLOCn is offset by 8, so we used
to add this offset into fs->inputs[n].inloc.  But a5xx drops this extra
offset-by-8.  So instead make inloc zero based and add the offset when
we emit OUTLOCn values (for the gen's that need the offset).

Signed-off-by: Rob Clark <robdclark@gmail.com>

freedreno/a3xx: use new shader linkage helper

Signed-off-by: Rob Clark <robdclark@gmail.com>

freedreno/a4xx: use new shader linkage helper

Signed-off-by: Rob Clark <robdclark@gmail.com>

freedreno/ir3: add new helper for shader linkage

Helps simplify things on a5xx, where pos/psize get added to the vs-out
map.  And anyways, simplifies a3xx and a4xx.

Signed-off-by: Rob Clark <robdclark@gmail.com>

st/mesa: skip lower_output_reads when possible

Reviewed-by: Marek Olšák <marek.olsak@amd.com>

st/glsl_to_tgsi: swizzle PROGRAM_OUTPUTs correctly in src_register translation

This is required for reading directly from fragment shader stencil and depth
outputs.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>

gallium: add PIPE_CAP_TGSI_CAN_READ_OUTPUTS

Drivers that support this benefit by saving one lowering pass in the
GLSL-to-TGSI conversion.

radeonsi already supports this because all outputs are stored in temporary
variables before the export (except for TCS outputs, which have always
been readable in TGSI anyway due to their special semantics).

Reviewed-by: Marek Olšák <marek.olsak@amd.com>

ac/nir: Fix out of bounds array access.

With nir_intrinsic_ssbo_atomic_comp_swap we run out of params.

Signed-off-by: Bas Nieuwenhuizen <basni@google.com>
Reviewed-by: Dave Airlie <airlied@redhat.com>

aubinator: Add support for enum types

Signed-off-by: Kristian H. Kristensen <hoegsberg@gmail.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>

intel/genxml: Fix ksp for INTERFACE_DESCRIPTOR_DATA

This one was split across two dwords as "Kernel Start Pointer" and
"Kernel Start Pointer High", which looks like it works when the driver
only accesses "Kernel Start Pointer". This breaks, of course, with BO
offsets > 4G.

Signed-off-by: Kristian H. Kristensen <hoegsberg@gmail.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>

intel/genxml: Use enum 3D_Logic_Op_Function where applicable

Signed-off-by: Kristian H. Kristensen <hoegsberg@gmail.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>

intel/genxml: Use blend function and factor enums where applicable

Signed-off-by: Kristian H. Kristensen <hoegsberg@gmail.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>

intel/genxml: Use enum 3D_Vertex_Component_Control where applicable

Signed-off-by: Kristian H. Kristensen <hoegsberg@gmail.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>

intel/genxml: Use enum 3D_Stencil_Operation where applicable

Signed-off-by: Kristian H. Kristensen <hoegsberg@gmail.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>

intel/genxml: Use enum SURFACE_FORMAT where applicable

Signed-off-by: Kristian H. Kristensen <hoegsberg@gmail.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>

intel/genxml: Use enum 3D_Prim_Topo_Type where applicable

Signed-off-by: Kristian H. Kristensen <hoegsberg@gmail.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>

intel/genxml: Use 3D_Compare_Function for gen8+ test functions

When the state fields where shuffled around for gen8, the compare
function enums were downgraded to just uints. Change them to enum
3D_Compare_Function.

Signed-off-by: Kristian H. Kristensen <hoegsberg@gmail.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>

intel/genxml: Emit genxml enums as C enums

The previous commits got rid of any clashes between #defines and enum
values and we can now emit the genxml enums as debugger friendly C
enums.

Signed-off-by: Kristian H. Kristensen <hoegsberg@gmail.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>

intel/genxml: Remove duplicate COMPAREFUNCTION values

These values were defined both as an enum and as inline values. Remove
the inline values and reference the 3D_Compare_Function enum instead.

Signed-off-by: Kristian H. Kristensen <hoegsberg@gmail.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>

intel/genxml: Allow referencing enums in type attributes

This lets us reference enums in the type attribute of a field.

Signed-off-by: Kristian H. Kristensen <hoegsberg@gmail.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>

anv: Emit cherryview SF state without including gen9_pack.h

Cleaner this way and we avoid including gen9_pack.h when we compile with
gen8_pack.h. We also avoid the if (cherryview) condition for non-gen8
gens that don't need it.

Signed-off-by: Kristian H. Kristensen <hoegsberg@gmail.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>

anv: Don't include two different pack headers

The batch chain logic only needs the pre-gen8 size of
MI_BATCH_BUFFER_START, which seems like something we can make a special
case for. The other two gen7 references, MI_BATCH_BUFFER_END and
MI_NOOP, are the same on all gens.

Signed-off-by: Kristian H. Kristensen <hoegsberg@gmail.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>

intel/genxml: Move enums above structs

We'll need to define them before we can reference them in structs and
instructions. Enums have no dependencies, so move them first in the
file.

Signed-off-by: Kristian H. Kristensen <hoegsberg@gmail.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>

genxml: Add values for Barycentric Interpolation Mode

Signed-off-by: Kristian H. Kristensen <hoegsberg@gmail.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>

anv: remove per-sample shading from TODO

This was done some time ago.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>

anv: clean up VkPhysicalDeviceFeatures list

Remove duplicate .alphaToOne, add missing .shaderResourceMinLod, and
reorder a few entries to match their vulkan.h order. All the sparse
features are still left out entirely.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>