swr: [rasterizer core] Add experimental support for hyper-threaded front-end

Acked-by: Brian Paul <brianp@vmware.com>

swr: [rasterizer] Avoid segv in thread creation on machines with non-consecutive NUMA topology.

Acked-by: Brian Paul <brianp@vmware.com>

swr: [rasterizer core] Replace all naked OSALIGN macro uses with OSALIGNSIMD / OSALIGNLINE

Future proofing

Acked-by: Brian Paul <brianp@vmware.com>

swr: [rasterizer] Ensure correct alignment of stack variables used as vectors

Acked-by: Brian Paul <brianp@vmware.com>

swr: [rasterizer core] Quantize depth to depth buffer precision prior to depth test/write.

Fixes z-fighting issues.

Acked-by: Brian Paul <brianp@vmware.com>

swr: [rasterizer common] win32 build fixups

Acked-by: Brian Paul <brianp@vmware.com>

swr: [rasterizer core] Affinitize thread scratch space to numa node of worker

Acked-by: Brian Paul <brianp@vmware.com>

swr: [rasterizer] Misc fixes identified by static code analysis

No perf loss detected

Acked-by: Brian Paul <brianp@vmware.com>

st/mesa: fix memleak in glDrawPixels cache code

If the glDrawPixels size changed, we leaked the previously cached
texture, if there was one.  This patch fixes the reference counting,
adds a refcount assertion check, and better handles potential malloc()
failures.

Tested with a modified version of the drawpix Mesa demo which changed
the image size for each glDrawPixels call.

Cc: "11.2" <mesa-stable@lists.freedesktop.org>
Reviewed-by: José Fonseca <jfonseca@vmware.com>
Reviewed-by: Charmaine Lee <charmainel@vmware.com>

gallium: Use STATIC_ASSERT whenever possible.

Reviewed-by: Eric Engestrom <eric.engestrom@imgtec.com>
Reviewed-by: Roland Scheidegger <sroland@vmware.com>

softpipe: Use STATIC_ASSERT whenever possible.

Reviewed-by: Eric Engestrom <eric.engestrom@imgtec.com>
Reviewed-by: Roland Scheidegger <sroland@vmware.com>

svga: Use STATIC_ASSERT whenever possible.

Reviewed-by: Eric Engestrom <eric.engestrom@imgtec.com>
Reviewed-by: Roland Scheidegger <sroland@vmware.com>

mesa: Use STATIC_ASSERT whenever possible.

Reviewed-by: Eric Engestrom <eric.engestrom@imgtec.com>
Reviewed-by: Roland Scheidegger <sroland@vmware.com>

r600g: use common scissor and viewport code

It's the same as radeonsi. This adds guard band support to r600g.

Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Grigori Goronzy <greg@chown.ath.cx>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

gallium/radeon: add R600/Evergreen/Cayman support to common viewport code

Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Grigori Goronzy <greg@chown.ath.cx>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

radeonsi: move scissor and viewport states into gallium/radeon

Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Grigori Goronzy <greg@chown.ath.cx>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

radeonsi: use guard band clipping

Guard band clipping speeds up rasterization for primitives that are
partially off-screen.  This change in particular results in small
framerate improvements in a wide range of games.

Started by Grigori Goronzy <greg@chown.ath.cx>.

Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Grigori Goronzy <greg@chown.ath.cx>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

radeonsi: compute scissor from viewport in set_viewport_states

and clamp it right before emitting. This is a prerequisite for computing
the guard band.

Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Grigori Goronzy <greg@chown.ath.cx>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

gallium/radeon: set GTT WC on tiled textures

Just for consistency. This should have no effect, because OpenGL textures
always go to VRAM.

Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>

gallium/radeon: relax requirements on VRAM placements on APUs

This makes Tonga with vramlimit=128 2x faster in Heaven.

Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>

winsys/amdgpu: remove hack for low VRAM configuration

A better solution will be used.

Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>

r600g: disable aniso filtering for non-mipmap textures on EG

this is the default behavior of the closed driver when running on VI

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

r600g: clean up aniso state translation

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

radeonsi: disable aniso filtering for non-mipmap textures on SI-CI

The closed driver does this, but it looks at base_level and last_level
and uses a conditional assignment, which LLVM can't generate on SGPRs.

That led me to invent this solution that abuses the image descriptor.

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

radeonsi: clean up aniso state translation

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

radeonsi: enable some sampler fields to match the closed driver

copied from the Vulkan driver

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

gallium/radeon: fix maximum texture anisotropy setup

We were overdoing it for non-power-of-two values.

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

gallium/radeon: never choose a linear tiling for DB surfaces

Just for consistency. This is actually not a problem, because both addrlib
and radeon check and fix this.

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

gallium/radeon: removing dead code for sharing stencil buffers

This is a remnant of the times when the DDX was allocating depth-stencil
buffers for windows. Now, st/dri allocates them and doesn't share them.

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

radeonsi: allow clearing buffers >= 4 GB

Only CMASK and DCC clears can use this, because only textures can be so
large.

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

gallium/radeon: allow allocating textures >= 4 GB

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

winsys/radeon: fix printing allocation failures

print as unsigned instead of signed

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

winsys/amdgpu: add support for 64-bit buffer sizes

v2: fail in radeon_winsys_bo_create if size > 32 bits

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

pb_buffer: switch pb_buffer::size to 64 bits

being able to allocate more than 4 GB may be useful

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

gallium/radeon: remove R600_QUERY_HW_FLAG_TIMER

not used anymore

Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

gallium/radeon: merge timer and non-timer query lists

All of them are paused only between IBs.

Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

r600g: don't manually stop queries for blitter

r600_set_active_query_state does it better.

Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

r600g: add pausing pipeline & streamout queries into set_active_query_state

Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

r600g: implement set_active_query_state for pausing occlusion queries

Use ZPASS_INCREMENT_DISABLE everywhere.

Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

r600g: simplify r600_set_occlusion_query_state

The caller does the same checking.

Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

gallium/radeon: move pipeline stat context flags to common code

Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

r600g: fix typo in r600 register definitions

Acked-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>

gallium/radeon: unify checking streamout enable state

Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

radeonsi: fix mask checking when emitting scissors and viewports

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Reviewed-by: Grigori Goronzy <greg@chown.ath.cx>

radeonsi: implement and rely on set_active_query_state

Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

gallium: pause queries for all meta ops

Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

gallium: add pipe_context::set_active_query_state for pausing queries

Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

radeonsi: Synchronize a streamout write after read hazard.

Signed-off-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>

nv30: Add missing PIPE_SHADER_CAP_INTEGERS to get_shader_param()

Add missing PIPE_SHADER_CAP_INTEGERS for frag shaders to
nv30_screen_get_shader_param().

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>

dri/i965: extend GLES3 sRGB workaround to cover all formats

It is incorrect to assume BGRA byte order for the GLES3 sRGB workaround.

v2: use _mesa_get_srgb_format_linear to handle all formats

Signed-off-by: Haixia Shi <hshi@chromium.org>
Reviewed-by: Stéphane Marchesin <marcheu@chromium.org>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

i965: Add autogenerated 'brw_nir_trig_workarounds.c' to gitignore

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

glsl: Update hash table comments in constant propagation

Signed-off-by: Rhys Kidd <rhyskidd@gmail.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

softpipe: add SSBO/shader atomics support.

This adds support for the features requires for ARB_shader_storage_buffer_object
and ARB_shader_atomic_counters, ARB_shader_atomic_counter_ops.

[airlied: some cleanups applied]
Reviewed-by: Brian Paul <brianp@vmware.com>
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>

draw: add support for passing buffers to vs/gs shaders.

Like the image code, but for shader buffers this time.

Reviewed-by: Brian Paul <brianp@vmware.com>
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>

tgsi: add support for buffer/atomic operations to tgsi_exec.

This adds support for doing load/store/atomic operations on
buffer objects.

Reviewed-by: Brian Paul <brianp@vmware.com>
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>

tgsi: set nonhelpermask for vertex shaders

For atomic operations we really need to avoid executing unnecessary shaders, so for some
tests that just draw a single point we only want one vertex to get processed not 4,

this fixes a number of the atomic counters tests.

Reviewed-by: Brian Paul <brianp@vmware.com>
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>

nir: Fix typo in comment

Trivial.

Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>

nir: Merge redudant integer clamping.

Dolphin uses them a lot. Range tracking would be better in the long term,
but this two lines works fine for now.

Signed-off-by: Markus Wick <markus@selfnet.de>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>

i965: Port INTEL_PRECISE_TRIG=1 to NIR.

This makes the extra multiply visible to NIR's algebraic optimizations
(for constant reassociation) as well as constant folding.  This means
that when the result of sin/cos are multiplied by an constant, we can
eliminate the extra multiply altogether, reducing the cost of the
workaround.

It also means we only have to implement it one place, rather than in
both backends.

This makes INTEL_PRECISE_TRIG=1 cost nothing on GPUTest/Volplosion,
which has a ton of sin() calls, but always multiplies them by an
immediate constant.  The extra multiply gets folded away.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eduardo Lima Mitev <elima@igalia.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Matt Turner <mattst88@gmail.com>

i965: Pass brw_compiler into brw_preprocess_nir() instead of is_scalar.

I want to be able to read other fields.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Reviewed-by: Eduardo Lima Mitev <elima@igalia.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Matt Turner <mattst88@gmail.com>

nir: Silence unused "options" warning in algebraic passes.

Some passes may not refer to options->..., at which point the compiler
will warn about an unused variable.  Just cast to void unconditionally
to shut it up.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eduardo Lima Mitev <elima@igalia.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Matt Turner <mattst88@gmail.com>

nir: Do basic constant reassociation.

Many shaders contain expression trees of the form:

    const_1 * (value * const_2)

Reorganizing these to

    (const_1 * const_2) * value

will allow constant folding to combine the constants.  Sometimes, these
constants are 2 and 0.5, so we can remove a multiply altogether.  Other
times, it can create more immediate constants, which can actually hurt.

Finding a good balance here is tricky.  While much more could be done,
this simple patch seems to have a lot of positive benefit while having
a low downside.

shader-db results on Broadwell:

total instructions in shared programs: 8963768 -> 8961369 (-0.03%)
instructions in affected programs: 438318 -> 435919 (-0.55%)
helped: 1502
HURT: 245

total cycles in shared programs: 71527354 -> 71421516 (-0.15%)
cycles in affected programs: 11541788 -> 11435950 (-0.92%)
helped: 3445
HURT: 1224

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eduardo Lima Mitev <elima@igalia.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Matt Turner <mattst88@gmail.com>

radeon/uvd: alignment fix for decode message buffer

Signed-off-by: Boyuan Zhang <boyuan.zhang@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>

st/mesa: replace _mesa_sysval_to_semantic table with function

Instead of using an array indexed by SYSTEM_VALUE_x, just use a
switch statement.  This fixes a regression caused by inserting new
SYSTEM_VALUE_ enums but not updating the mapping to TGSI semantics.

v2: fix a few switch statement mistakes for compute-related enums

Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>

nir/lower_system_values: Add support for several computed values

Reviewed-by: Rob Clark <robdclark@gmail.com>

glsl/shader_enums: Add the other two compute builtins

These weren't added before because they are actually calculated values that
are computed from other inputs.  However, in order to handle them in
nir_lower_system_values, it's nice for them to have a cannonical locaiton.

Reviewed-by: Rob Clark <robdclark@gmail.com>

glsl/shader_enums: Add an enum for Vulkan InstanceIndex

In Vulkan, you have InstanceIndex which begins at the base instance value
rather than the zero-based InstanceID of GL.

Reviewed-by: Rob Clark <robdclark@gmail.com>

mesa: add missing header to the tarball

Signed-off-by: Emil Velikov <emil.velikov@collabora.com>

drivers/softpipe: add missing header to the tarball

Signed-off-by: Emil Velikov <emil.velikov@collabora.com>

mesa: automake: update and reuse X86_SSE41_FILES list

Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
Acked-by: Jason Ekstrand <jason@jlekstrand.net>

compiler: android: flesh out nir into separate makefile

Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
Acked-by: Jason Ekstrand <jason@jlekstrand.net>

compiler: automake: flesh out NIR into separate makefile.

Analogous to previous commit - improved readability at the expense of
an extra file.

Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
Acked-by: Jason Ekstrand <jason@jlekstrand.net>

compiler: automake: split out glsl into separate makefile

Preserve the functionality while keeping the files smaller and
more readable.

v2: Do not include Makefile.sources from the GLSL makefile (silences
automake warnings)

Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>
Acked-by: Jason Ekstrand <jason@jlekstrand.net> (v1)

compiler: remove {glsl,nir}/Makefile.sources

No longer used as of last commit.

v2: Rebase.

Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>
Acked-by: Jason Ekstrand <jason@jlekstrand.net> (v1)

configure.ac: update the path of the generated files

... in order to determine if we need bison/flex. Failing to locate the
files will lead to mandating bison/flex even when building from a
release tarball.

CC: "11.2" <mesa-stable@lists.freedesktop.org>
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
Acked-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Matt Turner <mattst88@gmail.com>

glsl: move the android build scripts a level up

Analogous to previous commit.

Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
Acked-by: Jason Ekstrand <jason@jlekstrand.net>

glsl: move the scons build script a level up

It will allow us to remove the duplicate glsl/Makefile.sources.

Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
Acked-by: Jason Ekstrand <jason@jlekstrand.net>

Part revert "gallium/auxiliary: don't build NIR sources with MSVC2008 flags"

This reverts commit 41c7912d04111a7e3b75a438c5cbbd7edc0fee25 but leaves
out the pragma [that inspired the original commit].

Building mesa requires MSVC2013 or later, thus we no longer need this.

v2: Use correct include path (src/glsl/nir -> src/compiler/nir)

Conflicts:
src/gallium/auxiliary/Makefile.am

Acked-by: Jason Ekstrand <jason@jlekstrand.net> (v1)

GL3: ARB_shader_image_load_store/size is done for radeonsi also in GLES

Trivial.

docs: fix Coverity URL

tgsi/doc: fix spelling error

Signed-off-by: Oded Gabbay <oded.gabbay@gmail.com>
Reviewed-by: Rob Clark <robdclark@gmail.com>

nir: add a pass for lowering (un)pack_double_2x32

v2: Undo unintended change to the signature of
    nir_normalize_cubemap_coords (Iago).

v3: Move to compiler/nir (Iago)

v4: Remove Authors from copyright header (Michael Schellenberger)

v5 (Sam):
- Use nir_channel() and nir_ssa_for_alu_src() helpers (Jason)
- Inline lower_double_pack_instr() code into lower_double_pack_block()
  (Jason).
- Initialize nir_builder at lower_double_pack_impl() (Jason).

Signed-off-by: Iago Toral Quiroga <itoral@igalia.com>
Signed-off-by: Samuel Iglesias Gonsálvez <siglesias@igalia.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>

nir: add split versions of (un)pack_double_2x32

v2 (Sam):
- Use uint64 instead of float64 for sources and destinations. (Connor)

Signed-off-by: Samuel Iglesias Gonsálvez <siglesias@igalia.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>

nir: don't try to scalarize unpack_double_2x32

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>

nir: add support for (un)pack_double_2x32

v2 (Sam):
- Use uint64 instead of float64 for sources and destinations. (Connor)

Signed-off-by: Samuel Iglesias Gonsálvez <siglesias@igalia.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>

nir: add i2d and u2d opcodes

v2:
- Assert supports_int and don't fallback to nir_fmov (Jason)

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>

nir: add d2i, d2u, d2b opcodes

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>

nir: add support for d2f and f2d

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>

nir/glsl_to_nir: set bit_size on ssbo_load result

v2 (Sam):
- Add missing bit_size assignment when ssbo_load destination is a boolean.

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>

nir/glsl_to_nir: add bit-size info to add_instr()

Signed-off-by: Samuel Iglesias Gonsálvez <siglesias@igalia.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>

nir/split_var_copies: handle doubles

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>

nir/instr_set: handle 64-bit bit-sizes

v2: Revert spurious change in nir_opt_cse.c (Iago)

Signed-off-by: Iago Toral Quiroga <itoral@igalia.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>

nir: handle doubles in nir_deref_get_const_initializer_load()

v2 (Sam):
- Use proper bitsize value when calling to nir_load_const_instr_create()
  (Jason).

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>

nir/print: add support for printing doubles and bitsize

v2:
- Squash the printing doubles related patches into one patch (Sam).

v3:
- Print using PRIx64 format: long is 32-bit on some 32-bit platforms but long
long is basically always 64-bit (Jason).

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>

nir/glsl_to_nir: support doubles

v2:
- Don't set sized types to the destination of texture related opcodes.
  (Jason)

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>

nir/lower_load_const_to_scalar: support doubles and multiple bit sizes

v2 (Sam):
- Add assert to detect bitsizes differents than 32 and 64 (Jason).

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>

nir/lower_to_source_mods: Handle different bit sizes

v2 (Sam):
- Use helper to get base type from nir_alu_type.

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>

nir: add bit_size info to nir_load_const_instr_create()

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>

nir/lower_vec: adapt to different bit sizes

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>

nir: add bit_size info to nir_ssa_undef_instr_create()

v2:
- Make the users to give the right bit_sizes as arguments (Jason).

Signed-off-by: Samuel Iglesias Gonsálvez <siglesias@igalia.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>