mesa.git
8 years agoi965/fs: Define logical framebuffer write opcode.
Francisco Jerez [Mon, 27 Jul 2015 13:14:36 +0000 (16:14 +0300)]
i965/fs: Define logical framebuffer write opcode.

The logical variant is largely equivalent to the original opcode but
instead of taking a single payload source it expects its arguments
that make up the payload separately as individual sources, like:

 fb_write_logical null, color0, color1, src0_alpha,
                        src_depth, dst_depth, sample_mask, num_components

This patch defines the opcode and usual instruction boilerplate,
including a placeholder lowering function provided mainly as
self-documentation.

Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
8 years agoi965/fs: Implement pass to lower instructions of unsupported SIMD width.
Francisco Jerez [Mon, 13 Jul 2015 18:15:31 +0000 (21:15 +0300)]
i965/fs: Implement pass to lower instructions of unsupported SIMD width.

This lowering pass implements an algorithm to expand SIMDN
instructions into a sequence of SIMDM instructions in cases where the
hardware doesn't support the original execution size natively for some
particular instruction.  The most important use-cases are:

 - Lowering send message instructions that don't support SIMD16
   natively into SIMD8 (several texturing, framebuffer write and typed
   surface operations).

 - Lowering messages that don't support SIMD8 natively into SIMD16
   (*cough*gen4*cough*).

 - 64-bit precision operations (e.g. FP64 and 64-bit integer
   multiplication).

 - SIMD32.

The algorithm works by splitting the sources of the original
instruction into chunks of width appropriate for the lowered
instructions, and then interleaving the results component-wise into
the destination of the original instruction.  The pass is controlled
by the get_lowered_simd_width() function that currently just returns
the original execution size making the whole pass a no-op for the
moment until some user is introduced.

Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
v2: Reverse order of the source transformations and split_inst emit
    call to make the code a bit easier to understand.

8 years agoi965/fs: Fix return value of fs_inst::regs_read() for BAD_FILE.
Francisco Jerez [Thu, 16 Jul 2015 12:58:56 +0000 (15:58 +0300)]
i965/fs: Fix return value of fs_inst::regs_read() for BAD_FILE.

Typically BAD_FILE sources are used to mark a source as not present
what implies that no registers are read.  This will become much more
frequent with logical send opcodes which have a large number of
sources, many of them optionally used and marked as BAD_FILE when they
aren't applicable.  It will prove to be useful to be able to rely on
the value of regs_read() regardless of whether a source is present or
not.

Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
8 years agoi965/fs: Add builder emit method taking a variable number of source registers.
Francisco Jerez [Tue, 14 Jul 2015 16:32:03 +0000 (19:32 +0300)]
i965/fs: Add builder emit method taking a variable number of source registers.

And start using it in fs_builder::LOAD_PAYLOAD().  This will be used
to emit logical send message opcodes which have an unusually large
number of arguments.

Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
8 years agoi965/fs: Add stub lowering pass for logical send-message opcodes.
Francisco Jerez [Mon, 13 Jul 2015 14:44:58 +0000 (17:44 +0300)]
i965/fs: Add stub lowering pass for logical send-message opcodes.

This pass will house ad-hoc lowering code for several send
message-like virtual opcodes that will represent their logically
independent arguments as separate instruction sources rather than as a
single payload blob.  This pass will basically just take the separate
arguments that are supposed to be part of the payload and concatenate
them to construct a message in the form required by the hardware.
Virtual instructions in separate-source form will eventually allow
some simplification of the visitor code and make several
transformations easier like lowering SIMD16 instructions to SIMD8
algorithmically in cases where the hardware doesn't support the former
natively.

Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
8 years agoi965/fs: Factor out source components calculation to a separate method.
Francisco Jerez [Tue, 21 Jul 2015 14:28:39 +0000 (17:28 +0300)]
i965/fs: Factor out source components calculation to a separate method.

This cleans up fs_inst::regs_read() slightly by disentangling the
calculation of "components" from the handling of message payload
arguments.  This will also simplify the SIMD lowering and logical send
message lowering passes, because it will avoid expressions like
'regs_read * REG_SIZE / component_size' which are not only ugly, they
may be inaccurate because regs_read rounds up the result to the
closest register multiple so they could give incorrect results when
the component size is lower than one register (e.g. uniforms).  This
didn't seem to be a problem right now because all such expressions
happen to be dealing with per-channel GRFs only currently, but that's
by no means obvious so better be safe than sorry.

v2: Split PIXEL_X/Y and LINTERP into separate case blocks.

Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
8 years agoi965/fs: Simplify instruction rewrite loop in the register coalesce pass.
Francisco Jerez [Tue, 28 Jul 2015 09:07:56 +0000 (12:07 +0300)]
i965/fs: Simplify instruction rewrite loop in the register coalesce pass.

For some reason the loop that rewrites all occurrences of the
coalesced register was iterating over all possible offsets until it
would find one that compares equal to the offset of a source or
destination of any instruction in the program.  Since the mapping
between old and new offsets is already available in the regs_to_offset
array and we know that the whole register has been coalesced we can
just look it up.

Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
8 years agoi965/fs: Fix rewrite of the second half of 16-wide coalesced registers.
Francisco Jerez [Mon, 13 Jul 2015 11:20:32 +0000 (14:20 +0300)]
i965/fs: Fix rewrite of the second half of 16-wide coalesced registers.

The register coalesce pass wasn't rewriting the destination and
sources of instructions that accessed the second half of a coalesced
register previously copied with a 16-wide MOV instruction.  E.g.:

| ADD (16) vgrf0:f, vgrf0:f, 1.0:f
| MOV (16) vgrf1:f, vgrf0:f
| MOV (8)  vgrf2:f, vgrf0+1:f { sechalf }

would get incorrectly register-coalesced into:

| ADD (16) vgrf1:f, vgrf1:f, 1.0:f
| MOV (8)  vgrf2:f, vgrf0+1:f { sechalf }

The reason is that the mov[i] pointer was being left equal to NULL for
every other register.  The fact that we've made it to the rewrite loop
implies that the whole register will be coalesced, so it doesn't seem
right not to update something that uses it depending on whether mov[i]
is NULL or not.  Fixes an amount of texturing and image_load_store
piglit tests on my SIMD-lowering branch.

Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
8 years agoi965/fs: Detect multi-register MOVs correctly in register_coalesce.
Francisco Jerez [Tue, 28 Jul 2015 08:25:59 +0000 (11:25 +0300)]
i965/fs: Detect multi-register MOVs correctly in register_coalesce.

register_coalesce() was considering the exec_size of the MOV
instruction alone to decide whether the register at offset+1 of the
source VGRF was being copied to inst->dst.reg_offset+1 of the
destination VGRF, which is only a valid assumption if the move has a
32-bit execution type.  Use regs_read() instead to find out the number
of registers copied by the instruction.

Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
8 years agoradeon: add support for streams to the common streamout code. (v2)
Dave Airlie [Thu, 9 Jul 2015 06:34:59 +0000 (16:34 +1000)]
radeon: add support for streams to the common streamout code. (v2)

This adds to the common radeon streamout code, support
for multiple streams.

It updates radeonsi/r600 to set the enabled mask up.

v2: update for changes in previous patch.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
8 years agoradeon: move streamout buffer config to streamout enable function. (v2)
Dave Airlie [Sun, 26 Jul 2015 00:27:17 +0000 (01:27 +0100)]
radeon: move streamout buffer config to streamout enable function. (v2)

This will be used here later.

v2: update atom sizes
add check for old vs new enabled mask

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
8 years agodocs: consolidate nvc0 status
Fabio Pedretti [Tue, 28 Jul 2015 18:53:25 +0000 (20:53 +0200)]
docs: consolidate nvc0 status

8 years agomesa/es3.1: enable GL_ARB_explicit_uniform_location for GLES 3.1
Marta Lofstedt [Thu, 23 Jul 2015 14:38:38 +0000 (16:38 +0200)]
mesa/es3.1: enable GL_ARB_explicit_uniform_location for GLES 3.1

Signed-off-by: Marta Lofstedt <marta.lofstedt@intel.com>
Reviewed-by: Samuel Iglesias Gonsálvez <siglesias@igalia.com>
8 years agomesa/es3.1: enable GL_ARB_compute_shader for GLES 3.1
Marta Lofstedt [Wed, 29 Jul 2015 07:10:40 +0000 (10:10 +0300)]
mesa/es3.1: enable GL_ARB_compute_shader for GLES 3.1

Signed-off-by: Marta Lofstedt <marta.lofstedt@intel.com>
Reviewed-by: Samuel Iglesias Gonsálvez <siglesias@igalia.com>
8 years agomesa/es3.1: enable GL_ARB_texture_gather for GLES 3.1
Marta Lofstedt [Mon, 27 Jul 2015 13:22:51 +0000 (15:22 +0200)]
mesa/es3.1: enable GL_ARB_texture_gather for GLES 3.1

Signed-off-by: Marta Lofstedt <marta.lofstedt@intel.com>
Reviewed-by: Samuel Iglesias Gonsálvez <siglesias@igalia.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
8 years agomesa/es3.1: enable GL_ARB_texture_multisample for GLES 3.1
Marta Lofstedt [Mon, 27 Jul 2015 13:22:50 +0000 (15:22 +0200)]
mesa/es3.1: enable GL_ARB_texture_multisample for GLES 3.1

Signed-off-by: Marta Lofstedt <marta.lofstedt@intel.com>
Reviewed-by: Samuel Iglesias Gonsálvez <siglesias@igalia.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
8 years agomesa/es3.1: enable GL_ARB_shader_atomic_counters for GLES 3.1
Marta Lofstedt [Thu, 23 Jul 2015 14:38:34 +0000 (16:38 +0200)]
mesa/es3.1: enable GL_ARB_shader_atomic_counters for GLES 3.1

Signed-off-by: Marta Lofstedt <marta.lofstedt@intel.com>
Reviewed-by: Samuel Iglesias Gonsálvez <siglesias@igalia.com>
8 years agomesa/es3.1: enable GL_ARB_shader_image_load_store for GLES 3.1
Marta Lofstedt [Mon, 27 Jul 2015 13:22:49 +0000 (15:22 +0200)]
mesa/es3.1: enable GL_ARB_shader_image_load_store for GLES 3.1

Signed-off-by: Marta Lofstedt <marta.lofstedt@intel.com>
Reviewed-by: Samuel Iglesias Gonsálvez <siglesias@igalia.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
8 years agomesa/es3.1: Add ES 3.1 handling to get.c and get_hash_generator.py
Marta Lofstedt [Thu, 23 Jul 2015 14:38:32 +0000 (16:38 +0200)]
mesa/es3.1: Add ES 3.1 handling to get.c and get_hash_generator.py

Signed-off-by: Marta Lofstedt <marta.lofstedt@linux.intel.com>
Reviewed-by: Samuel Iglesias Gonsálvez <siglesias@igalia.com>
8 years agomesa: Return INVALID_ENUM in glClearBufferiv() when buffer is not color or stencil
Eduardo Lima Mitev [Tue, 10 Feb 2015 15:40:40 +0000 (16:40 +0100)]
mesa: Return INVALID_ENUM in glClearBufferiv() when buffer is not color or stencil

Page 497 of the PDF, section '17.4.3.1 Clearing Individual Buffers' of the
OpenGL 4.5 spec states:

    "An INVALID_ENUM error is generated by ClearBufferiv and
     ClearNamedFramebufferiv if buffer is not COLOR or STENCIL."

Fixes 1 dEQP test:
* dEQP-GLES3.functional.negative_api.buffer.clear_bufferiv

Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
8 years agoi965: Use real stage in "Unsupported form of variable indexing" warning.
Kenneth Graunke [Wed, 29 Jul 2015 01:45:32 +0000 (18:45 -0700)]
i965: Use real stage in "Unsupported form of variable indexing" warning.

Other stages can be miserably slow too!

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
8 years agoglsl: Fix a bug where LHS swizzles of swizzles were too small.
Kenneth Graunke [Thu, 23 Jul 2015 03:08:23 +0000 (20:08 -0700)]
glsl: Fix a bug where LHS swizzles of swizzles were too small.

A simple shader such as

   vec4 color;
   color.xy.x = 1.0;

would cause ir_assignment::set_lhs() to generate bogus IR:

   (swiz xy (swiz x (constant float (1.0))))

We were setting the number of components of each new RHS swizzle based
on the highest channel used in the LHS swizzle.  So, .xy.y would
generate (swiz xy (swiz xx ...)), while .xy.x would break.

Our existing Piglit test happened to use .xzy.z, which worked, since
'z' is the third component, resulting in an xxx swizzle.

This patch sets the number of swizzle components based on the size of
the LHS swizzle's inner value, so we always have the correct number
at each step.

Fixes new Piglit tests glsl-vs-swizzle-swizzle-lhs-[23].
Fixes ir_validate assertions in in Metro 2033 Redux.

v2: Move num_components updating completely out of update_rhs_swizzle
    (suggested by Timothy Arceri).  Simplify.

Cc: mesa-stable@lists.freedesktop.org
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Timothy Arceri <t_arceri@yahoo.com.au>
8 years agoglsl: verify location when dual source blending
Tapani Pälli [Fri, 3 Jul 2015 07:19:23 +0000 (10:19 +0300)]
glsl: verify location when dual source blending

Same check is made for glBindFragDataLocationIndexed but it was missing
when using layout qualifiers.

Fixes following Piglit test:
arb_blend_func_extended-output-location

Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Timothy Arceri <t_arceri@yahoo.com.au>
8 years agoglsl: move max_index calc to assign_attribute_or_color_locations
Tapani Pälli [Mon, 27 Jul 2015 10:29:20 +0000 (13:29 +0300)]
glsl: move max_index calc to assign_attribute_or_color_locations

Change function to get all gl_constants for inspection, this is used
by follow-up patch.

v2: rebase, update function documentation

Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Timothy Arceri <t_arceri@yahoo.com.au>
8 years agovc4: Skip re-emitting the shader_rec if it's unchanged.
Eric Anholt [Tue, 28 Jul 2015 18:00:58 +0000 (11:00 -0700)]
vc4: Skip re-emitting the shader_rec if it's unchanged.

It's a bunch of work for us to emit it (and its uniforms), more work for
the kernel to validate it, and additional work for the CLE to read
it. Improves es2gears framerate by about 50%.

Signed-off-by: Eric Anholt <eric@anholt.net>
8 years agovc4: Drop unused vpm_offset value.
Eric Anholt [Wed, 29 Jul 2015 02:59:45 +0000 (19:59 -0700)]
vc4: Drop unused vpm_offset value.

It's been dead since we started doing VS/CS attr offset setup during
shader compile.

8 years agovc4: Simplify vc4_use_bo and make sure it's not a shader.
Eric Anholt [Tue, 28 Jul 2015 17:20:10 +0000 (10:20 -0700)]
vc4: Simplify vc4_use_bo and make sure it's not a shader.

Since the conversion to keeping validated shaders around for the BO's
lifetime, we haven't been checking that rendering doesn't happen to
shaders.  Make vc4_use_bo check that always, and just don't use it for the
VC4_MODE_SHADER case (so now modes are unused)

8 years agovc4: Keep the validated shader around for the simulator execution.
Eric Anholt [Tue, 28 Jul 2015 17:11:08 +0000 (10:11 -0700)]
vc4: Keep the validated shader around for the simulator execution.

This more closely matches the kernel behavior on shader validation now.

8 years agovc4: Make the object be the return value from vc4_use_bo().
Eric Anholt [Tue, 28 Jul 2015 16:51:37 +0000 (09:51 -0700)]
vc4: Make the object be the return value from vc4_use_bo().

Drops 40 bytes of code from validation.

8 years agovc4: Ensure that the bin CL is properly capped by increment/flush.
Eric Anholt [Tue, 28 Jul 2015 07:29:31 +0000 (00:29 -0700)]
vc4: Ensure that the bin CL is properly capped by increment/flush.

We don't want anything to appear after we've kicked off the render (and
thus job flush), since that might then get written out to the tile
allocation state.

Signed-off-by: Eric Anholt <eric@anholt.net>
8 years agovc4: Drop NV shader reloc validation.
Eric Anholt [Tue, 28 Jul 2015 07:05:33 +0000 (00:05 -0700)]
vc4: Drop NV shader reloc validation.

It wasn't validating enough, and we don't need the packet.

8 years agovc4: Fix raster surface shadow updates under DRI2.
Eric Anholt [Tue, 28 Jul 2015 06:23:57 +0000 (23:23 -0700)]
vc4: Fix raster surface shadow updates under DRI2.

Glamor asks GBM for the handle of the BO, then flinks it itself.  We
were marking the bo non-private in the flink and dmabuf (DRI3) paths,
but not the GEM handle path.  As a result, non-pageflipping DRI2
swapbuffers (EGL apps, in particular) were never updating the texture.

8 years agovc4: Fix bus errors on dumping CL on hardware.
Eric Anholt [Tue, 28 Jul 2015 06:15:39 +0000 (23:15 -0700)]
vc4: Fix bus errors on dumping CL on hardware.

The kernel can't fixup unaligned float traps for us, so deref as a
uint32_t first.

8 years agometa/copy_image: Stash off the scissor
Jason Ekstrand [Fri, 24 Jul 2015 00:26:56 +0000 (17:26 -0700)]
meta/copy_image: Stash off the scissor

The meta CopyImageSubData path uses BlitFramebuffers to do the actual copy.
The only thing that can affect BlitFramebuffers other than the currently
bound framebuffers is the scissor so we need to save that off and reset it.
If we don't do this, applications that use a scissor together with
CopyImageSubData will get accidentally scissored copies.

Tested-by: Markus Wick <markus at selfnet.de>
Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com>
8 years agoradeon: add streamout status 1-3 queries.
Dave Airlie [Thu, 9 Jul 2015 06:33:59 +0000 (16:33 +1000)]
radeon: add streamout status 1-3 queries.

This adds support for queries against the non-0 vertex streams.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
8 years agost/mesa: remove st_context::missing textures and get_passthrough_fs
Marek Olšák [Tue, 28 Jul 2015 18:41:16 +0000 (20:41 +0200)]
st/mesa: remove st_context::missing textures and get_passthrough_fs

Reviewed-by: Brian Paul <brianp@vmware.com>
8 years agost/mesa: remove st_finalize_textures atom
Marek Olšák [Sat, 25 Jul 2015 15:26:10 +0000 (17:26 +0200)]
st/mesa: remove st_finalize_textures atom

It only checks fragment textures and ignores other shaders, which makes it
incomplete, and textures are already finalized in update_single_texture.

There are no piglit regressions.

Reviewed-by: Brian Paul <brianp@vmware.com>
8 years agost/mesa: add shader dumping for shader-db
Marek Olšák [Sat, 25 Jul 2015 18:25:18 +0000 (20:25 +0200)]
st/mesa: add shader dumping for shader-db

Reviewed-by: Brian Paul <brianp@vmware.com>
8 years agost/mesa: fix GLSL 1.30 texture shadow functions with the GL_ALPHA depth mode (v2)
Marek Olšák [Thu, 23 Jul 2015 19:57:19 +0000 (21:57 +0200)]
st/mesa: fix GLSL 1.30 texture shadow functions with the GL_ALPHA depth mode (v2)

Fixes piglit:
    spec@glsl-1.30@execution@fs-texture-sampler2dshadow-10
    spec@glsl-1.30@execution@fs-texture-sampler2dshadow-11

v2: use st_shader_stage_to_ptarget

Reviewed-by: Brian Paul <brianp@vmware.com>
8 years agor600,radeonsi: GL_ARB_conditional_render_inverted
Edward O'Callaghan [Mon, 27 Jul 2015 01:01:47 +0000 (11:01 +1000)]
r600,radeonsi: GL_ARB_conditional_render_inverted

By using 'Tobias Klausmann' piglit test-suite patch. We obtain
a full 12/12 passes using this patch. By 'faking' to claim
support for this extension we obtain 7 fails and 5 passes.

Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Tested-by: Furkan Alaca <falaca@gmail.com>
Signed-off-by: Marek Olšák <marek.olsak@amd.com>
8 years agoradeonsi: add support for interpolateAt functions (v2)
Dave Airlie [Fri, 17 Jul 2015 03:44:18 +0000 (04:44 +0100)]
radeonsi: add support for interpolateAt functions (v2)

This is part of ARB_gpu_shader5, and this passes
all the piglit tests currently available.

v2: use macros from the fine derivs commit.
add comments.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
8 years agoi965: Support importing R8 and GR88 dma_bufs
Chad Versace [Tue, 23 Jun 2015 22:48:40 +0000 (15:48 -0700)]
i965: Support importing R8 and GR88 dma_bufs

EGL_EXT_image_dma_buf_import now supports those formats.

Tests:
  - Tested by Piglit ext_image_dma_buf_import-transcode-nv12-as-r8-gr88.
  - Tested by Peter in Kodi/XBMC to obtain 60fps NV12 transcode at 4K.

Tested-by: Peter Frühberger <peter.fruehberger@gmail.com>
Signed-off-by: Chad Versace <chad.versace@intel.com>
8 years agoegl: Add support for DRM_FORMAT_R8, RG88, and GR88
Chad Versace [Tue, 23 Jun 2015 22:48:17 +0000 (15:48 -0700)]
egl: Add support for DRM_FORMAT_R8, RG88, and GR88

The Kodi/XBMC developers want to transcode NV12 to RGB with OpenGL shaders,
importing the two source planes through EGL_EXT_image_dma_buf_import. That
requires importing the Y plane as an R8 EGLImage and the UV plane as either an
RG88 or GR88 EGLImage.

This patch teaches the driver-independent part of EGL about the new
formats. Real driver support is left for follow-up patches.

The new formats landed in airlied's kernel branch 'drm-next' on July 24.

Tested-by: Peter Frühberger <peter.fruehberger@gmail.com>
Signed-off-by: Chad Versace <chad.versace@intel.com>
8 years agonvc0/ir: trim out barrier sync for non-compute shaders
Ilia Mirkin [Tue, 28 Jul 2015 06:37:51 +0000 (02:37 -0400)]
nvc0/ir: trim out barrier sync for non-compute shaders

It seems like they're never necessary, and actively cause harm. This
fixes some of the barrier-related piglits.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
8 years agonvc0/ir: fix barrier emission
Ilia Mirkin [Tue, 28 Jul 2015 06:00:20 +0000 (02:00 -0400)]
nvc0/ir: fix barrier emission

immediate arguments require a flag to be set for each one

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
8 years agovc4: Add support for ARB_draw_elements_base_vertex.
Eric Anholt [Wed, 22 Jul 2015 19:14:40 +0000 (12:14 -0700)]
vc4: Add support for ARB_draw_elements_base_vertex.

Gallium exposes it unconditionally, so do our best to support it.  It
fails on the negative index cases, but those seem unlikely to be used in
the wild.

8 years agofreedreno/ir3: add transform-feedback support
Rob Clark [Sat, 25 Jul 2015 16:53:23 +0000 (12:53 -0400)]
freedreno/ir3: add transform-feedback support

Signed-off-by: Rob Clark <robclark@freedesktop.org>
8 years agofreedreno/ir3: track "keeps" in ir
Rob Clark [Sat, 25 Jul 2015 17:51:16 +0000 (13:51 -0400)]
freedreno/ir3: track "keeps" in ir

Previously we had a fixed array to track kills, since they don't
generate an SSA value, and then cheated by stuffing them in the
outputs array before sending things through depth/sched/etc.  But
store instructions will need similar treatment.  So convert this
over to a more general array of instructions that must be kept
and fix up the places that were previously relying on kills being
in the output array.

Signed-off-by: Rob Clark <robclark@freedesktop.org>
8 years agofreedreno/ir3: add support for store instructions
Rob Clark [Sat, 25 Jul 2015 17:48:07 +0000 (13:48 -0400)]
freedreno/ir3: add support for store instructions

For store instructions, the "dst" register is a read register, not a
written register.  (Ie. it is the address to store to.)  Lets not
confuse register allocation, scheduling, etc, with these details.
Instead just leave a dummy instr->regs[0], and take "dst" from
instr->regs[1] and srcs following.

Signed-off-by: Rob Clark <robclark@freedesktop.org>
8 years agofreedreno/ir3: cleanup driver-param stuff
Rob Clark [Sat, 25 Jul 2015 16:48:18 +0000 (12:48 -0400)]
freedreno/ir3: cleanup driver-param stuff

Add 'enum ir3_driver_param' to track driver-param slots, and a
create_driver_param() helper to avoid having the knowledge about
where driver params are placed in const regs spread throughout
the code as we add additional driver-params.

Signed-off-by: Rob Clark <robclark@freedesktop.org>
8 years agofreedreno: add transform-feedback state
Rob Clark [Sat, 25 Jul 2015 14:56:39 +0000 (10:56 -0400)]
freedreno: add transform-feedback state

Signed-off-by: Rob Clark <robclark@freedesktop.org>
8 years agofreedreno: add resource tracking support for written buffers
Rob Clark [Sun, 26 Jul 2015 17:30:26 +0000 (13:30 -0400)]
freedreno: add resource tracking support for written buffers

With stream-out (transform-feedback) we have the case where resources
are *written* by the gpu, which needs basically the same tracking to
figure out when rendering must be flushed.

Signed-off-by: Rob Clark <robclark@freedesktop.org>
8 years agofreedreno/a3xx+a4xx: add support for vtxcnt semantic
Rob Clark [Fri, 24 Jul 2015 21:07:23 +0000 (17:07 -0400)]
freedreno/a3xx+a4xx: add support for vtxcnt semantic

This will be used for stream-out (transform-feedback)

Signed-off-by: Rob Clark <robclark@freedesktop.org>
8 years agofreedreno/ir3: add stream-output support to cmdline compiler
Rob Clark [Fri, 24 Jul 2015 21:06:01 +0000 (17:06 -0400)]
freedreno/ir3: add stream-output support to cmdline compiler

A bit hard-coded configuration at the moment, but sufficient for now.

Signed-off-by: Rob Clark <robclark@freedesktop.org>
8 years agofreedreno/ir3: drop unused create_input() arg
Rob Clark [Fri, 24 Jul 2015 20:42:10 +0000 (16:42 -0400)]
freedreno/ir3: drop unused create_input() arg

Signed-off-by: Rob Clark <robclark@freedesktop.org>
8 years agofreedreno/ir3: move emit_const to ir3
Rob Clark [Fri, 24 Jul 2015 17:07:33 +0000 (13:07 -0400)]
freedreno/ir3: move emit_const to ir3

Details of the cmdstream packets are different between a3xx and a4xx,
but the logic about the layout of const registers is the same, as that
is dictated by the ir3 shader compiler.  So rather than duplicating
logic that is tightly coupled to ir3 between a3xx and a4xx, move this
into ir3 and use per-generation callbacks for to build the cmdstream
packets.

This should make it easier to pass additional const regs (such as for
transform feedback).  And it also keeps the layout internal to ir3 in
case we want to make the layout more dynamic some day.

Signed-off-by: Rob Clark <robclark@freedesktop.org>
8 years agofreedreno/ir3: bit of shader API refactoring
Rob Clark [Thu, 23 Jul 2015 19:51:13 +0000 (15:51 -0400)]
freedreno/ir3: bit of shader API refactoring

Since for transform-feedback, we'll need more than just the TGSI
tokens from the state object, just pass the entire state object to
ir3_shader_create().  This also cleans things up a bit for some
day in the future when we could take shader either as TGSI or
directly NIR (for ex, glsl2nir or spirv2nir paths).  In the same
spirit, drop extra args from ir3_compile_shader_nir() (since it
can anyways get what it needs from the ir3_shader_variant).

Signed-off-by: Rob Clark <robclark@freedesktop.org>
8 years agofreedreno/ir3: updated cat6 encoding
Rob Clark [Thu, 23 Jul 2015 19:31:13 +0000 (15:31 -0400)]
freedreno/ir3: updated cat6 encoding

Sync updated cat6 encoding from freedreno.git, needed to properly encode
store instructions.

Signed-off-by: Rob Clark <robclark@freedesktop.org>
8 years agoglsl: enable conservative depth, ssbo based on GLSL version
Ilia Mirkin [Sat, 25 Jul 2015 05:06:20 +0000 (01:06 -0400)]
glsl: enable conservative depth, ssbo based on GLSL version

Add in missed version checks in the GLSL parser

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Timothy Arceri <t_arceri@yahoo.com.au>
Reviewed-by: Samuel Iglesias Gonsálvez <siglesias@igalia.com>
8 years agodocs: add news item and link release notes for mesa 10.6.3
Emil Velikov [Sun, 26 Jul 2015 14:20:31 +0000 (15:20 +0100)]
docs: add news item and link release notes for mesa 10.6.3

Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>
8 years agodocs: Add checksums for mesa 10.6.3 tarballs
Emil Velikov [Sun, 26 Jul 2015 14:18:24 +0000 (15:18 +0100)]
docs: Add checksums for mesa 10.6.3 tarballs

Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>
(cherry picked from commit ccef8901de421eae5dcc8affa14218d46cc06593)

8 years agoAdd release notes for 10.6.3
Emil Velikov [Sun, 26 Jul 2015 13:38:58 +0000 (14:38 +0100)]
Add release notes for 10.6.3

Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>
(cherry picked from commit ddc976368fef367e464472ebcc2ac4fd89eb9fd8)

8 years agoradeonsi: add fine derivate control (v2.1)
Dave Airlie [Fri, 17 Jul 2015 04:35:30 +0000 (05:35 +0100)]
radeonsi: add fine derivate control (v2.1)

This adds support for fine derivatives and enables
ARB_derivative_control on radeonsi.

(just fell out of my working out interpolation)

v2: cleanup some bits, write a comment
v2.1: take Michel's comment from the mailing list

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
8 years agoradeonsi: fix GLSL textureGrad(samplerCube*) functions
Marek Olšák [Thu, 23 Jul 2015 22:54:08 +0000 (00:54 +0200)]
radeonsi: fix GLSL textureGrad(samplerCube*) functions

+4 piglits

Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
8 years agost/mesa: don't ignore texture buffer state changes
Marek Olšák [Fri, 24 Jul 2015 17:47:06 +0000 (19:47 +0200)]
st/mesa: don't ignore texture buffer state changes

Fixes piglit:
  spec@arb_texture_buffer_range@ranges-2

Cc: mesa-stable@lists.freedesktop.org
Reviewed-by: Brian Paul <brianp@vmware.com>
8 years agonvc0: fix geometry program revalidation of clipping params
Ilia Mirkin [Sat, 11 Jul 2015 16:47:03 +0000 (12:47 -0400)]
nvc0: fix geometry program revalidation of clipping params

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Cc: mesa-stable@lists.freedesktop.org
8 years agoradeonsi: ubo indexing support (v2)
Dave Airlie [Mon, 13 Jul 2015 08:12:18 +0000 (09:12 +0100)]
radeonsi: ubo indexing support (v2)

This is required as part of ARB_gpu_shader5.

no backend changes are required for this, or if
any are, it's the same ones as for samplers.

v2: use get_indirect_index (Marek)

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
8 years agoradeonsi: add support for indirect samplers (v2)
Dave Airlie [Sun, 12 Jul 2015 23:07:09 +0000 (00:07 +0100)]
radeonsi: add support for indirect samplers (v2)

This adds the frontend support, however the llvm
backend produces the wrong pattern, however
we can conditionalise enabling ARB_gpu_shader5
on whatever version of llvm we fix this in.

v2: drop unneeded sampler_indirect checks (Marek)

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
8 years agoradeonsi: split out interpolation input selection
Dave Airlie [Fri, 17 Jul 2015 03:43:09 +0000 (04:43 +0100)]
radeonsi: split out interpolation input selection

This is prep work for using it in the interpolation code
later.

Also add storage for the input interpolation mode so we
can pick it up later.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
8 years agoradeonsi: separate out load sample position
Dave Airlie [Thu, 16 Jul 2015 03:38:41 +0000 (04:38 +0100)]
radeonsi: separate out load sample position

This is prep work for reusing this in the interpolation
code later.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
8 years agoglsl: recognize ARB_shading_language_420pack to be enabled with 4.20+
Ilia Mirkin [Fri, 24 Jul 2015 21:06:22 +0000 (17:06 -0400)]
glsl: recognize ARB_shading_language_420pack to be enabled with 4.20+

The 420pack extension enables various GLSL rules that need to be applied
to any GLSL 4.20+ shader even if the extension is not explicitly
enabled.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Chris Forbes <chrisf@ijw.co.nz>
8 years agomesa: fix error checking for getting zero-sized texture images
Ilia Mirkin [Fri, 24 Jul 2015 00:18:57 +0000 (20:18 -0400)]
mesa: fix error checking for getting zero-sized texture images

Commit 17f714836 (mesa: rearrange texture error checking order) moved
the width/height/depth == 0 allowance before checking if the image was
there. This was in part due to depth having to be == 1 for 2D images and
width having to be == 1 for 1D images. Instead relax the height/depth
checks to also accept 0 as valid.

With this change,

  bin/arb_direct_state_access-get-textures

starts passing again.

Fixes: 17f714836 (mesa: rearrange texture error checking order)
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Brian Paul <brianp@vmware.com>
8 years agomesa: Fix typo in a comment
Anuj Phogat [Fri, 26 Jun 2015 22:39:40 +0000 (15:39 -0700)]
mesa: Fix typo in a comment

Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
8 years agometa: Use _mesa_need_rgb_to_luminance_conversion() in decompress_texture_image()
Anuj Phogat [Fri, 12 Jun 2015 21:58:46 +0000 (14:58 -0700)]
meta: Use _mesa_need_rgb_to_luminance_conversion() in decompress_texture_image()

Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
8 years agomesa: Change the signature of _mesa_need_rgb_to_luminance_conversion()
Anuj Phogat [Fri, 12 Jun 2015 21:42:57 +0000 (14:42 -0700)]
mesa: Change the signature of _mesa_need_rgb_to_luminance_conversion()

This allows us to handle cases when texImage->_BaseFormat doesn't match
_mesa_format_get_base_format(texImage->Format). _BaseFormat is what we
care about in this function.

Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
8 years agometa: Fix reading luminance texture as rgba in _mesa_meta_pbo_GetTexSubImage()
Anuj Phogat [Tue, 12 May 2015 12:46:04 +0000 (05:46 -0700)]
meta: Fix reading luminance texture as rgba in _mesa_meta_pbo_GetTexSubImage()

After recent addition of pbo testing in piglit test getteximage-luminance,
it fails on i965. This patch makes a sub test pass.

This patch adds a clear color operation to meta pbo path, which I think is
better than falling back to software path.

V2: Fix color mask for GL_LUMINANCE_ALPHA

Cc: <mesa-stable@lists.freedesktop.org>
Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
8 years agometa: Use _mesa_need_luminance_to_rgb_conversion() in decompress_texture_image()
Anuj Phogat [Fri, 12 Jun 2015 00:23:34 +0000 (17:23 -0700)]
meta: Use _mesa_need_luminance_to_rgb_conversion() in decompress_texture_image()

Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
8 years agomesa: Add a helper function _mesa_need_luminance_to_rgb_conversion()
Anuj Phogat [Thu, 11 Jun 2015 23:48:26 +0000 (16:48 -0700)]
mesa: Add a helper function _mesa_need_luminance_to_rgb_conversion()

Cc: <mesa-stable@lists.freedesktop.org>
Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
8 years agometa: Use _mesa_unpack_format_to_base_format() to handle integer formats
Anuj Phogat [Fri, 12 Jun 2015 19:11:01 +0000 (12:11 -0700)]
meta: Use _mesa_unpack_format_to_base_format() to handle integer formats

Replace a call to mesa_base_tex_format() that handles only internal
formats with a call to the new _mesa_unpack_format_to_base_format()
function that handles allowed unpack formats and does not care for
internal formats at all.

Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
8 years agomesa: Add a helper function _mesa_unpack_format_to_base_format()
Anuj Phogat [Fri, 12 Jun 2015 19:09:05 +0000 (12:09 -0700)]
mesa: Add a helper function _mesa_unpack_format_to_base_format()

Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
8 years agomesa: Set green, blue channels to zero only for formats with these components
Anuj Phogat [Thu, 11 Jun 2015 23:44:45 +0000 (16:44 -0700)]
mesa: Set green, blue channels to zero only for formats with these components

This is an optimization which avoids setting pixel transfer operations
when not required. _mesa_ReadPixels falls back to slower path if
transfer operations are set.

Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
8 years agometa: Don't do fragment color clamping in _mesa_meta_pbo_GetTexSubImage
Anuj Phogat [Wed, 6 May 2015 12:43:08 +0000 (05:43 -0700)]
meta: Don't do fragment color clamping in _mesa_meta_pbo_GetTexSubImage

_mesa_meta_pbo_GetTexSubImage() uses _mesa_meta_BlitFrameBuffer(),
which will do fragment clamping if enabled. But fragment clamping
doesn't affect ReadPixels and GetTexImage.

Without this patch, piglit test arb_color_buffer_float-clear fails,
when forced to use the meta pbo path.

v2: Apply this fix to both glReadPixels and glGetTexImage.

Cc: <mesa-stable@lists.freedesktop.org>
Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
8 years agometa: Abort meta pbo path if readpixels need signed-unsigned conversion
Anuj Phogat [Wed, 20 May 2015 17:22:45 +0000 (10:22 -0700)]
meta: Abort meta pbo path if readpixels need signed-unsigned conversion

Meta pbo path for ReadPixels rely on BlitFramebuffer which doesn't support
signed to unsigned integer conversions and vice versa.

Without this patch, piglit test fbo_integer_readpixels_sint_uint fails, when
forced to use the meta pbo path.

v2: Make need_signed_unsigned_int_conversion() a static function. (Iago)
    Bump up the comment and the commit message. (Jason)

Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Cc: <mesa-stable@lists.freedesktop.org>
Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
Reviewed-by: Iago Toral <itoral@igalia.com>
8 years agometa: Fix transfer operations check in meta pbo path for readpixels
Anuj Phogat [Wed, 20 May 2015 17:21:39 +0000 (10:21 -0700)]
meta: Fix transfer operations check in meta pbo path for readpixels

Currently used ctx->_ImageTransferState check is not sufficient
because it doesn't include the read color clamping enabled with
GL_CLAMP_READ_COLOR. So, use the helper function
_mesa_get_readpixels_transfer_ops().

Also, transfer operations don't affect glGetTexImage(). So, do
the check only for glReadPixles.

Without this patch, arb_color_buffer_float-readpixels test fails, when
forced to use meta pbo path.

V2: Add a comment and bump up the commit message.

Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Cc: <mesa-stable@lists.freedesktop.org>
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
8 years agomesa: Turn get_readpixels_transfer_ops() in to a global function
Anuj Phogat [Wed, 20 May 2015 00:44:52 +0000 (17:44 -0700)]
mesa: Turn get_readpixels_transfer_ops() in to a global function

This utility function is utilized in a later patch.

Cc: <mesa-stable@lists.freedesktop.org>
Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
8 years agoi965: Use updated kernel interface for accurate TIMESTAMP reads
Chris Wilson [Tue, 21 Jul 2015 10:12:57 +0000 (11:12 +0100)]
i965: Use updated kernel interface for accurate TIMESTAMP reads

I was mistaken, I thought we already had fixed this in the kernel a
couple of years ago. We had not, and the broken read (the hardware
shifts the register output on 64bit kernels, but not on 32bit kernels) is
now enshrined into the ABI. I also had the buggy architecture reversed,
believing it to be 32bit that had the shifted results. On the basis of
those mistakes, I wrote

commit c8d3ebaffc0d7d915c1c19d54dba61fd1e57b338
Author: Chris Wilson <chris@chris-wilson.co.uk>
Date:   Wed Apr 29 13:32:38 2015 +0100

    i965: Query whether we have kernel support for the TIMESTAMP register once

Now that we do have an extended register read interface for always
reporting the full 36bit TIMESTAMP (irrespective of whether the hardware
is buggy or not), make use of it and in the process fix my reversed
detection of the buggy reads for unpatched kernels.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Martin Peres <martin.peres@linux.intel.com>
Cc: Kenneth Graunke <kenneth@whitecape.org>
Cc: Michał Winiarski <michal.winiarski@intel.com>
Cc: Daniel Vetter <daniel@ffwll.ch>
Tested-and-acked-by: Chris Forbes <chrisf@ijw.co.nz>
Reviewed-by: Daniel Vetter <daniel@ffwll.ch>
8 years agoglsl/glcpp: fix SIGSEGV when checking error condition for macro redefinition
Samuel Iglesias Gonsalvez [Thu, 23 Jul 2015 08:38:36 +0000 (10:38 +0200)]
glsl/glcpp: fix SIGSEGV when checking error condition for macro redefinition

Commit a6e9cd14c does not take into account than node_{a,b}->next could be NULL
in some circumstances, such as in a shader containing this code:

  #define A 1 /* comment */
  #define A 1 /* comment */

This patch fixes the segmentation fault for cases like that.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=91290
Signed-off-by: Samuel Iglesias Gonsalvez <siglesias@igalia.com>
Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com>
Cc: mesa-stable@lists.freedesktop.org
8 years agonvc0/ir: per-patch vars are in a separate address space
Ilia Mirkin [Fri, 24 Jul 2015 04:21:28 +0000 (00:21 -0400)]
nvc0/ir: per-patch vars are in a separate address space

There's no need to attempt to avoid overlapping generic i/o with patch
i/o. By the same token, we can't merge patch and non-patch loads/stores.

This fixes at least the

  tes-both-input-array-*-index-rd

tessellation variable-indexing tests.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
8 years agonvc0/ir: kepler can't do indirect shader input/output loads directly
Ilia Mirkin [Fri, 24 Jul 2015 03:03:53 +0000 (23:03 -0400)]
nvc0/ir: kepler can't do indirect shader input/output loads directly

There's a special AL2P instruction (called AFETCH in nv50 ir) which
computes a "physical" value to be used with indirect addressing with ALD.

Fixes

  tcs-input-array-*-index-rd
  tcs-output-array-*-index-wr

varying-indexing tessellation tests on Kepler.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
8 years agoradeon: Silence GCC unused-but-set-variable warnings.
Vinson Lee [Wed, 22 Jul 2015 04:50:29 +0000 (21:50 -0700)]
radeon: Silence GCC unused-but-set-variable warnings.

radeon_fbo.c: In function 'radeon_map_renderbuffer_s8z24':
radeon_fbo.c:162:9: warning: variable 'ret' set but not used [-Wunused-but-set-variable]
     int ret;
         ^
radeon_fbo.c: In function 'radeon_map_renderbuffer_z16':
radeon_fbo.c:200:9: warning: variable 'ret' set but not used [-Wunused-but-set-variable]
     int ret;
         ^
radeon_fbo.c: In function 'radeon_map_renderbuffer':
radeon_fbo.c:242:8: warning: variable 'ret' set but not used [-Wunused-but-set-variable]
    int ret;
        ^
radeon_fbo.c: In function 'radeon_unmap_renderbuffer':
radeon_fbo.c:419:14: warning: variable 'ok' set but not used [-Wunused-but-set-variable]
    GLboolean ok;
              ^

Signed-off-by: Vinson Lee <vlee@freedesktop.org>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
8 years agodoxygen: Link GLvector4f struct members properly, avoiding invalid XML/HTML warning
Rhys Kidd [Thu, 23 Jul 2015 04:14:00 +0000 (22:14 -0600)]
doxygen: Link GLvector4f struct members properly, avoiding invalid XML/HTML warning

Signed-off-by: Rhys Kidd <rhyskidd@gmail.com>
Reviewed-by: Brian Paul <brianp@vmware.com>
8 years agodoxygen: Correct grammatical typo in math/m_vector.h
Rhys Kidd [Thu, 23 Jul 2015 04:14:00 +0000 (22:14 -0600)]
doxygen: Correct grammatical typo in math/m_vector.h

Signed-off-by: Rhys Kidd <rhyskidd@gmail.com>
Reviewed-by: Brian Paul <brianp@vmware.com>
8 years agomesa: minor clean-ups in shaderapi.c
Brian Paul [Thu, 23 Jul 2015 16:04:13 +0000 (10:04 -0600)]
mesa: minor clean-ups in shaderapi.c

80-column wrapping.  Move break statements.  Indentation fixes.

8 years agomesa: fix _mesa_error() compiler warnings in shaderapi.c
Brian Paul [Thu, 23 Jul 2015 13:47:25 +0000 (07:47 -0600)]
mesa: fix _mesa_error() compiler warnings in shaderapi.c

Fix many instances of:
main/shaderapi.c: In function '_mesa_GetSubroutineUniformLocation':
main/shaderapi.c:2176:7: warning: format not a string literal and no format arguments [-Wformat-security]
       _mesa_error(ctx, GL_INVALID_OPERATION, api_name);
       ^

Ideally, many of these error messages should be improved to indicate
which argument is incorrect as we do in other parts of Mesa.

Reviewed-by: Kai Wasserbäch <kai@dev.carbon-project.org>
Tested-by: Kai Wasserbäch <kai@dev.carbon-project.org>
8 years agost/mesa: remove unused 'samp' function parameters
Brian Paul [Thu, 23 Jul 2015 13:43:11 +0000 (07:43 -0600)]
st/mesa: remove unused 'samp' function parameters

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
8 years agost/mesa: add comments on a few sampler view functions
Brian Paul [Thu, 23 Jul 2015 13:41:09 +0000 (07:41 -0600)]
st/mesa: add comments on a few sampler view functions

Trivial.

8 years agomesa: do more thorough target checking in compressed_subtexture_target_check()
Brian Paul [Wed, 22 Jul 2015 13:53:01 +0000 (07:53 -0600)]
mesa: do more thorough target checking in compressed_subtexture_target_check()

When we're error-checking the target, we also need to check if the
corresponding extension is supported.

Reviewed-by: Roland Scheidegger <sroland@vmware.com>
8 years agomesa: another target fix in compressed_subtexture_target_check()
Brian Paul [Wed, 22 Jul 2015 13:42:12 +0000 (07:42 -0600)]
mesa: another target fix in compressed_subtexture_target_check()

The previous fix added GL_TEXTURE_CUBE_MAP_ARRAY but we also need
to support GL_TEXTURE_CUBE_MAP (via DSA).

So in the end, GL_TEXTURE_3D is the only (legal) target for
glCompressedTex*SubImage3D() which needs additional compression
format checking.  GL_TEXTURE_2D_ARRAY, GL_TEXTURE_CUBE_MAP_ARRAY
and GL_TEXTURE_CUBE_MAP are basically 2D images which support all
compressed formats.

Reviewed-by: Roland Scheidegger <sroland@vmware.com>
8 years agomesa: simplify format check in compressed_subtexture_target_check()
Brian Paul [Wed, 22 Jul 2015 13:32:36 +0000 (07:32 -0600)]
mesa: simplify format check in compressed_subtexture_target_check()

Lose the invalidformat local variable.

Reviewed-by: Roland Scheidegger <sroland@vmware.com>
8 years agomesa: initialize variables to silence compiler warnings
Brian Paul [Wed, 22 Jul 2015 00:42:41 +0000 (18:42 -0600)]
mesa: initialize variables to silence compiler warnings

Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com>