Michael Neuling [Thu, 2 Jul 2020 04:11:16 +0000 (14:11 +1000)]
Add uart16550 files from fusesoc
These are needed for synthesis that doesn't use fusesoc natively.
These were pulled in via 'fusesoc fetch ::uart16550:1.5.5-r1'
Signed-off-by: Michael Neuling <mikey@neuling.org>
Michael Neuling [Mon, 22 Jun 2020 03:09:09 +0000 (13:09 +1000)]
Build to tmp file so nextpnr errors don't confuse make
nextpnr will leave an output file around even when it errors out, so
build to a tmp file and move it when we succeed so we don't confuse
make.
Signed-off-by: Michael Neuling <mikey@neuling.org>
Michael Neuling [Mon, 22 Jun 2020 03:09:09 +0000 (13:09 +1000)]
Fix building with yosys/nextpnr
Add --no-formal so that asserts are removed by yosys as nextpnr
doesn't like them.
This was suggested by @tgingold here:
https://github.com/YosysHQ/yosys/issues/2068#issuecomment-
644545863
Signed-off-by: Michael Neuling <mikey@neuling.org>
Michael Neuling [Mon, 22 Jun 2020 03:11:03 +0000 (13:11 +1000)]
Add yosys builds files to gitignore
Signed-off-by: Michael Neuling <mikey@neuling.org>
Michael Neuling [Tue, 23 Jun 2020 07:07:12 +0000 (17:07 +1000)]
Send line feed if we get a carriage return in hello world.
Signed-off-by: Michael Neuling <mikey@neuling.org>
Michael Neuling [Tue, 30 Jun 2020 05:47:36 +0000 (15:47 +1000)]
Merge pull request #216 from paulusmack/cfar
Timing and speed improvements, implement CFAR register
Paul Mackerras [Tue, 30 Jun 2020 05:01:06 +0000 (15:01 +1000)]
Merge pull request #206 from Jbalkind/icachecleanup
Icache constants cleanup
Paul Mackerras [Fri, 19 Jun 2020 10:00:16 +0000 (20:00 +1000)]
execute1: Do forwarding of the CR result to the next instruction
This adds a path to allow the CR result of one instruction to be
forwarded to the next instruction, so that sequences such as
cmp; bc can avoid having a 1-cycle bubble.
Forwarding is not available for dot-form (Rc=1) instructions,
since the CR result for them is calculated in writeback. The
decode.output_cr field is used to identify those instructions
that compute the CR result in execute1.
For some reason, the multiply instructions incorrectly had
output_cr = 1 in the decode tables. This fixes that.
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
Paul Mackerras [Fri, 19 Jun 2020 08:00:37 +0000 (18:00 +1000)]
execute1: Add latch to redirect path
This latches the redirect signal inside execute1, so that it is sent
a cycle later to fetch1 (and to decode/icache as flush). This breaks
a long combinatorial chain from the branch and interrupt detection
in execute1 through the redirect/flush signals all the way back to
fetch1, icache and decode.
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
Paul Mackerras [Fri, 19 Jun 2020 07:13:06 +0000 (17:13 +1000)]
logical: Only do output inversion for OP_AND, OP_OR and OP_XOR
It's not needed for the other ops (popcnt, parity, etc.) and the
logical unit shows up as a critical path from time to time.
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
Paul Mackerras [Mon, 15 Jun 2020 07:45:55 +0000 (17:45 +1000)]
core: Implement CFAR register
This implements the CFAR SPR as a slow SPR stored in 'ctrl'. Taken
branches and rfid update it to the address of the branch or rfid
instruction.
To simplify the logic, this makes rfid use the branch logic to
generate its redirect (requiring SRR0 to come in to execute1 on
the B input and SRR1 on the A input), and the masking of the bottom
2 bits of NIA is moved to fetch1.
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
Michael Neuling [Mon, 29 Jun 2020 02:19:06 +0000 (12:19 +1000)]
Merge pull request #213 from ozbenh/uart16550
Add support for standard 16550 style UART
Michael Neuling [Mon, 29 Jun 2020 02:18:44 +0000 (12:18 +1000)]
Merge pull request #212 from ozbenh/liteeth
liteeth: Hook up LiteX LiteEth ethernet controller
Michael Neuling [Mon, 29 Jun 2020 00:24:49 +0000 (10:24 +1000)]
Merge pull request #214 from shingarov/fix-ld-target
Fix ld error in elf maketarget
Boris Shingarov [Thu, 25 Jun 2020 09:31:45 +0000 (05:31 -0400)]
Fix ld error in elf maketarget
The sdram_init ELF fails to link:
powerpc64le-linux-gnu-ld -static -nostdlib -T sdram_init.lds \
--gc-sections -o sdram_init.elf head.o main.o sdram.o console.o \
libc.o sdram_init.lds
powerpc64le-linux-gnu-ld: error: linker script file 'sdram_init.lds'
appears multiple times
make: *** [Makefile:70: sdram_init.elf] Error 1
This is because sdram_init.lds is one of the prerequisites, and thus is
contained in $^. However, it is also explicitly specified as part of
LDFLAGS, as the argument to -T.
Signed-off-by: Boris Shingarov <shingarov@labware.com>
Benjamin Herrenschmidt [Fri, 19 Jun 2020 11:18:33 +0000 (21:18 +1000)]
tests: Add updated micropython build with 16550 support
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Benjamin Herrenschmidt [Fri, 19 Jun 2020 10:27:31 +0000 (20:27 +1000)]
sim_console: Fix polling to check for POLLIN
Under some circumstances we get POLLHUP which we incorrectly
treat as having a character in the buffer.
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Benjamin Herrenschmidt [Thu, 18 Jun 2020 07:14:55 +0000 (17:14 +1000)]
uart: Make 16550 the default
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Benjamin Herrenschmidt [Tue, 23 Jun 2020 05:44:37 +0000 (15:44 +1000)]
syscon: Add flag to indicate the timebase frequency
This adds a flag (currently not set) to indicate that the core is using
the architected timebase frequency of 512Mhz. When not set, the core is
using the proc frequency for the timebase.
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Benjamin Herrenschmidt [Thu, 18 Jun 2020 07:14:41 +0000 (17:14 +1000)]
console: Add support for the 16550 UART
And rebuild various binaries
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Benjamin Herrenschmidt [Thu, 18 Jun 2020 04:00:28 +0000 (14:00 +1000)]
uart: Add a simulation model for the 16550 compatible UART
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Benjamin Herrenschmidt [Thu, 18 Jun 2020 01:18:30 +0000 (11:18 +1000)]
uart: Rename sim_uart.vhdl to sim_pp_uart.vhdl
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Benjamin Herrenschmidt [Thu, 18 Jun 2020 01:06:33 +0000 (11:06 +1000)]
console: Cleanup console API
Use a more generic console_init() instead of potato_uart_init(),
and do the same for interrupt control. There should be no
change in behaviour.
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Benjamin Herrenschmidt [Tue, 16 Jun 2020 12:42:15 +0000 (22:42 +1000)]
uart: Import and hook up opencore 16550 compatible UART
This imports via fusesoc a 16550 compatible (ie "standard") UART,
and wires it up optionally in the SoC instead of the potato one.
This also adds support for a second UART (which is always a
16550) to Arty, wired to JC "bottom" port.
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Benjamin Herrenschmidt [Thu, 18 Jun 2020 09:41:00 +0000 (19:41 +1000)]
ex1: Add SPR_TBU support
It's used by the boot wrapper in Linux and possibly some userspace
programs.
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Benjamin Herrenschmidt [Sat, 13 Jun 2020 00:04:31 +0000 (10:04 +1000)]
liteeth: Hook up LiteX LiteEth ethernet controller
Currently only generated for Arty.
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Michael Neuling [Tue, 23 Jun 2020 06:58:06 +0000 (16:58 +1000)]
Merge pull request #211 from shenki/spi-constraint
spi: Fix dat_i_l constraints
Joel Stanley [Mon, 22 Jun 2020 09:03:14 +0000 (18:33 +0930)]
spi: Fix dat_i_l constraints
No cells matched 'get_cells -hierarchical -filter {NAME =~*/spi_rxtx/dat_i_l*}'. [build/microwatt_0/src/microwatt_0/fpga/arty_a7.xdc:42]
The signal is in it's own process so the net name ends up being
spi_rxtx/input_delay_1.dat_i_l_reg.
After this change the log shows:
Applied set_property IOB = TRUE for soc0/\spiflash_gen.spiflash /spi_rxtx/\input_delay_1.dat_i_l_reg . (constraint file fpga/arty_a7.xdc, line 42).
Applied set_property IOB = TRUE for soc0/\spiflash_gen.spiflash /spi_rxtx/\input_delay_1.dat_i_l_reg . (constraint file fpga/arty_a7.xdc, line 42).
Applied set_property IOB = TRUE for soc0/\spiflash_gen.spiflash /spi_rxtx/\input_delay_1.dat_i_l_reg . (constraint file fpga/arty_a7.xdc, line 42).
Applied set_property IOB = TRUE for soc0/\spiflash_gen.spiflash /spi_rxtx/\input_delay_1.dat_i_l_reg . (constraint file fpga/arty_a7.xdc, line 42).
Signed-off-by: Joel Stanley <joel@jms.id.au>
Michael Neuling [Tue, 23 Jun 2020 04:32:42 +0000 (14:32 +1000)]
Merge pull request #210 from ozbenh/xics
xics: Cleanups and add a simple ICS for use by Linux
Benjamin Herrenschmidt [Mon, 22 Jun 2020 13:38:34 +0000 (23:38 +1000)]
xics: Add support for reduced priority field size
This makes the ICS support less than the 8 architected bits
and sets the soc to use 3 bits by default.
All the supported bits set translates to "masked" (and will read
back at 0xff), any small value is used as-is.
Linux doesn't use priorities above 5, so this is a way to save
silicon. The number of supported priority bits is exposed to the
OS via the config register.
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Benjamin Herrenschmidt [Wed, 17 Jun 2020 12:11:58 +0000 (22:11 +1000)]
xics: Add simple ICS
Move the external interrupt generation to a separate module
"ICS" (source controller) which a register per source containing
currently only the priority control.
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Benjamin Herrenschmidt [Wed, 17 Jun 2020 12:07:33 +0000 (22:07 +1000)]
xics/icp: MFRR starts at 0xff not 0x00
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Benjamin Herrenschmidt [Wed, 17 Jun 2020 12:06:28 +0000 (22:06 +1000)]
tests/xics: Ensure no compiler optimisations in delay()
In case it would be tempted to "read ahead" the delay function
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Benjamin Herrenschmidt [Wed, 17 Jun 2020 11:51:16 +0000 (21:51 +1000)]
xics: ICP should be big endian !
That's how Linux expects it. This also simplifies the
register access implementation since the bit fields now
align properly regardless of the access size.
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Benjamin Herrenschmidt [Wed, 17 Jun 2020 04:00:04 +0000 (14:00 +1000)]
tests: Fix Makefile.test to not allow host includes
xics was including the host limits.h for example
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Michael Neuling [Fri, 19 Jun 2020 01:50:47 +0000 (11:50 +1000)]
Merge pull request #208 from paulusmack/faster
Make the core go faster
Several major improvements in here:
- Simple branch predictor
- Reduced latency for mispredicted branches and interrupts by removing fetch2 stage
- Cache improvements
o Request critical dword first on refill
o Handle hits while refilling, including on line being refilled
o Sizes doubled for both D and I
- Loadstore improvements: can now do one load or store every two cycles in most cases
- Optimized 2-cycle multiplier for Xilinx 7-series parts using DSP slices
- Timing improvements, including:
o Stash buffer in decode1
o Reduced width of execute1 result mux
o Improved SPR decode in decode1
o Some non-critical operation take a cycle longer so we can break some long combinatorial chains
- Core logging: logs 256 bits of info every cycle into a ring buffer, to help with debugging and performance analysis
This increases the LUT usage for the "synth" + A35 target from 9182 to 10297 = 12%.
Paul Mackerras [Wed, 17 Jun 2020 21:26:01 +0000 (07:26 +1000)]
Merge pull request #207 from ozbenh/misc
Random cleanups of the SoC interfaces
Paul Mackerras [Tue, 16 Jun 2020 06:59:54 +0000 (16:59 +1000)]
fpga: Add a xilinx_specific fileset to microwatt.core
At present this just has the Xilinx-specific multiplier code, but
might in future have other things.
This also adds the xilinx_specific fileset to the synth target.
Without that it was failing because there was no multiplier.
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
Paul Mackerras [Tue, 16 Jun 2020 01:37:25 +0000 (11:37 +1000)]
Make LOG_LENGTH configurable per FPGA variant
This plumbs the LOG_LENGTH parameter (which controls how many entries
the core log RAM has) up to the top level so that it can be set on
the fusesoc command line and have different default values on
different FPGAs.
It now defaults to 512 entries generally and on the Artix-7 35 parts,
and 2048 on the larger Artix-7 FPGAs. It can be set to 0 if desired.
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
Paul Mackerras [Mon, 15 Jun 2020 06:59:08 +0000 (16:59 +1000)]
execute1: Reduce width of the result mux to help timing
This reduces the number of different things that are assigned to
the result variable.
- The computations for the popcnt, prty, cmpb and exts instruction
families are moved into the logical unit.
- The result of mfspr from the slow SPRs is computed in 'spr_val'
before being assigned to 'result'.
- Writes to LR as a result of a blr or bclr instruction are done
through the exc_write path to writeback.
This eases timing considerably.
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
Paul Mackerras [Mon, 15 Jun 2020 05:43:05 +0000 (15:43 +1000)]
core: Implement a simple branch predictor
This implements a simple branch predictor in the decode1 stage. If it
sees that the instruction is b or bc and the branch is predicted to be
taken, it sends a flush and redirect upstream (to icache and fetch1)
to redirect fetching to the branch target. The prediction is sent
downstream with the branch instruction, and execute1 now only sends
a flush/redirect upstream if the prediction was wrong. Unconditional
branches are always predicted to be taken, and conditional branches
are predicted to be taken if and only if the offset is negative.
Branches that take the branch address from a register (bclr, bcctr)
are predicted not taken, as we don't have any way to predict the
branch address.
Since we can now have a mflr being executed immediately after a bl
or bcl, we now track the update to LR in the hazard tracker, using
the second write register field that is used to track RA updates for
update-form loads and stores.
For those branches that update LR but don't write any other result
(i.e. that don't decrementer CTR), we now write back LR in the same
cycle as the instruction rather than taking a second cycle for the
LR writeback.
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
Paul Mackerras [Mon, 15 Jun 2020 00:02:14 +0000 (10:02 +1000)]
decode1: Improve timing for slow SPR decode path
This makes the logic that works out decode.unit and decode.sgl_pipe
for mtspr/mfspr to/from slow SPRs detect the fact that the
instruction is mtspr/mfspr based on a match with the instruction
word rather than looking at v.decode.insn_type. This improves timing
substantially, as the ROM lookup to get v.decode is relatively slow.
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
Paul Mackerras [Sun, 14 Jun 2020 23:28:03 +0000 (09:28 +1000)]
decode1: Add a stash buffer to the output
This means that the busy signal from execute1 (which can be driven
combinatorially from mmu or dcache) now stops at decode1 and doesn't
go on to icache or fetch1. This helps with timing.
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
Benjamin Herrenschmidt [Sat, 13 Jun 2020 12:29:54 +0000 (22:29 +1000)]
soc: Slight cleanup of IRQ assignments
Use a separate process to assign selected interrupts to the
interrupt array, and document them.
There's only one interrupt *for now* but that will change
and this way is clearer.
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Benjamin Herrenschmidt [Sat, 13 Jun 2020 12:05:39 +0000 (22:05 +1000)]
soc: Rename uart_dat8 to uart0_dat8
Just for consistency. Will come in handy if we ever add a second one
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Benjamin Herrenschmidt [Sat, 13 Jun 2020 12:04:45 +0000 (22:04 +1000)]
soc: Rename wb_dram_ctrl to wb_ext_io and rework decoding
This makes the control bus currently going out of "soc" towards
litedram more generic for external IO devices added by the
top-level rather than inside the SoC proper.
This is mostly renaming of signals and a small change on how the
address decoder operates, using a separate "cascaded" decode for
the external IOs.
We make the region 0xc8nn_nnnn be the "external IO" region for
now.
This will make it easier / cleaner to add more external devices.
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Jonathan Balkind [Sat, 13 Jun 2020 22:39:18 +0000 (18:39 -0400)]
Minor refactor of icache to make less dependent on wishbone
Signed-off-by: Jonathan Balkind <jbalkind@princeton.edu>
Paul Mackerras [Sat, 13 Jun 2020 13:00:13 +0000 (23:00 +1000)]
dcache: Reduce back-to-back store latency from 3 cycles to 2
This uses the machinery we already had for comparing the real address
of a new request with the tag of a previous request (r1.reload_tag)
to get better timing on comparing the address of a second store with
the one in progress. The comparison is now on the set size rather
than the page size, but since set size can't be larger than the page
size (and usually will equal the page size), that is OK.
The same comparison can also be used to tell when we can satisfy
a load miss during a cache line refill.
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
Benjamin Herrenschmidt [Sat, 13 Jun 2020 12:19:33 +0000 (22:19 +1000)]
soc: Don't require dram wishbones signals to be wired by toplevel
Currently, when not using litedram, the top level still has to hook
up "dummy" wishbones to the main dram and control dram busses coming
out of the SoC and provide ack signals.
Instead, make the SoC generate the acks internally when not using
litedram and use defaults to make the wiring entirely optional.
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Benjamin Herrenschmidt [Sat, 13 Jun 2020 11:57:01 +0000 (21:57 +1000)]
soc: Add defaults for some input signals
That way the top-level's don't need to assign them
Also remove generics that are set to the default anyways
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Benjamin Herrenschmidt [Sat, 13 Jun 2020 11:51:31 +0000 (21:51 +1000)]
soc: Remove unused RESET_LOW generic
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Paul Mackerras [Sat, 13 Jun 2020 10:27:50 +0000 (20:27 +1000)]
mmu: Take an extra cycle to do TLB invalidations
This makes the TLB invalidations that occur as a result of a tlbie,
slbia or mtspr instruction take one more cycle. This breaks some
long combinatorial chains from decode2 to dcache and icache and
thus eases timing.
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
Paul Mackerras [Thu, 11 Jun 2020 04:23:50 +0000 (14:23 +1000)]
dcache: Reduce latencies and improve timing
This implements various improvements to the dcache with the aim of
making it go faster.
- We can now execute operations that don't need to access main memory
(cacheable loads that hit in the cache and TLB operations) as soon
as any previous operation has completed, without waiting for the
state machine to become idle.
- Cache line refills start with the doubleword that is needed to
satisfy the load that initiated them.
- Cacheable loads that miss return their data and complete as soon as
the requested doubleword comes back from memory; they don't wait for
the refill to finish.
- We now have per-doubleword valid bits for the cache line being
refilled, meaning that if a load comes in for a line that is in the
process of being refilled, we can return the data and complete it
within a couple of cycles of the doubleword coming in from memory.
- There is now a bypass path for data being written to the cache RAM
so that we can do a store hit followed immediately by a load hit to
the same doubleword. This also makes the data from a refill
available to load hits one cycle earlier than it would be otherwise.
- Stores complete in the cycle where their wishbone operation is
initiated, without waiting for the wishbone cycle to complete.
- During the wishbone cycle for a store, if another store comes in
that is to the same page, and we don't have a stall from the
wishbone, we can send out the write for the second store in the same
wishbone cycle and without going through the IDLE state first. We
limit it to 7 outstanding writes that have not yet been
acknowledged.
- The cache tag RAM is now read on a clock edge rather than being
combinatorial for reading. Its width is rounded up to a multiple of
8 bits per way so that byte enables can be used for writing
individual tags.
- The cache tag RAM is now written a cycle later than previously, in
order to ease timing.
- Data for a store hit is now written one cycle later than
previously. This eases timing since we don't have to get through
the tag matching and on to the write enable within a single cycle.
The 2-stage bypass path means we can still handle a load hit on
either of the two cycles after the store and return the correct
data. (A load hit 3 or more cycles later will get the correct data
from the BRAM.)
- Operations can sit in r0 while there is an uncompleted operation in
r1. Once the operation in r1 is completed, the operation in r0
spends one cycle in r0 for TLB/cache tag lookup and then gets put
into r1.req. This can happen before r1 gets to the IDLE state.
Some operations can then be completed before r1 gets to the IDLE
state - a load miss to the cache line being refilled, or a store to
the same page as a previous store.
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
Paul Mackerras [Tue, 12 May 2020 06:28:42 +0000 (16:28 +1000)]
decode: Work out ispr1/ispr2 in parallel with decode ROM lookup
This makes the logic that calculates which SPRs are being accessed
work in parallel with the instruction decode ROM lookup instead of
being dependent on the opcode found in the decode ROM. The reason
for doing that is that the path from icache through the decode ROM
to the ispr1/ispr2 fields has become a critical path.
Thus we are now using only a very partial decode of the instruction
word in the logic for isp1/isp2, and we therefore can no longer rely
on them being zero in all cases where no SPR is being accessed.
Instead, decode2 now ignores ispr1/ispr2 in all cases except when the
relevant decode.input_reg_a/b or decode.output_reg_a is set to SPR.
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
Paul Mackerras [Fri, 5 Jun 2020 04:22:02 +0000 (14:22 +1000)]
loadstore1: Reduce busy cycles
This reduces the number of cycles where loadstore1 asserts its busy
output, leading to increased throughput of loads and stores. Loads
that hit in the cache can now be executed at the rate of one every two
cycles. Stores take 4 cycles assuming the wishbone slave responds
with an ack the cycle after we assert strobe.
To achieve this, the state machine code is split into two parts, one
for when we have an existing instruction in progress, and one for
starting a new instruction. We can now combinatorially clear busy and
start a new instruction in the same cycle that we get a done signal
from the dcache; in other words we are completing one instruction and
potentially writing back results in the same cycle that we start a new
instruction and send its address and data to the dcache.
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
Paul Mackerras [Fri, 5 Jun 2020 03:29:34 +0000 (13:29 +1000)]
loadstore1: Complete mfspr/mtspr a cycle later
This makes mfspr and mtspr complete (and mfspr write back) on the
cycle after the instruction is received from execute1, rather than
on the same cycle. This makes them match all other instructions
that execute in one cycle. Because these instructions are marked
as single-issue, there wasn't the possibility of having two
instructions complete on the same cycle (which we can't cope with),
but it is better to fix this.
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
Paul Mackerras [Thu, 4 Jun 2020 10:58:32 +0000 (20:58 +1000)]
core: Use a busy signal rather than a stall
This changes the instruction dependency tracking so that we can
generate a "busy" signal from execute1 and loadstore1 which comes
along one cycle later than the current "stall" signal. This will
enable us to signal busy cycles only when we need to from loadstore1.
The "busy" signal from execute1/loadstore1 indicates "I didn't take
the thing you gave me on this cycle", as distinct from the previous
stall signal which meant "I took that but don't give me anything
next cycle". That means that decode2 proactively gives execute1
a new instruction as soon as it has taken the previous one (assuming
there is a valid instruction available from decode1), and that then
sits in decode2's output until execute1 can take it. So instructions
are issued by decode2 somewhat earlier than they used to be.
Decode2 now only signals a stall upstream when its output buffer is
full, meaning that we can fill up bubbles in the upstream pipe while a
long instruction is executing. This gives a small boost in
performance.
This also adds dependency tracking for rA updates by update-form
load/store instructions.
The GPR and CR hazard detection machinery now has one extra stage,
which may not be strictly necessary. Some of the code now really
only applies to PIPELINE_DEPTH=1.
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
Paul Mackerras [Thu, 28 May 2020 23:38:05 +0000 (09:38 +1000)]
icache: Improve latencies when reloading cache lines
The icache can now detect a hit on a line being refilled from memory,
as we have an array of individual valid bits per row for the line
that is currently being loaded. This enables the request that
initiated the refill to be satisfied earlier, and also enables
following requests to the same cache line to be satisfied before the
line is completely refilled. Furthermore, the refill now starts
at the row that is needed. This should reduce the latency for an
icache miss.
We now get a 'sequential' indication from fetch1, and use that to know
when we can deliver an instruction word using the other half of the
64-bit doubleword that was read last cycle. This doesn't make much
difference at the moment, but it frees up cycles where we could test
whether the next line is present in the cache so that we could
prefetch it if not.
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
Paul Mackerras [Thu, 21 May 2020 07:50:54 +0000 (17:50 +1000)]
multiply: Use DSP48 slices for multiplication on Xilinx FPGAs
This adds a custom implementation of the multiplier which uses 16
DSP48E1 slices to do a 64x64 bit multiplication in 2 cycles.
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
Paul Mackerras [Thu, 21 May 2020 03:42:46 +0000 (13:42 +1000)]
multiply: Move selection of result bits into execute1
This puts the logic that selects which bits of the multiplier result
get written into the destination GPR into execute1, moved out from
multiply.
The multiplier is now expected to do an unsigned multiplication of
64-bit operands, optionally negate the result, detect 32-bit
or 64-bit signed overflow of the result, and return a full 128-bit
result.
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
Paul Mackerras [Wed, 3 Jun 2020 01:26:33 +0000 (11:26 +1000)]
core: Double the dcache and icache sizes
This makes the dcache and icache both be 8kB. This still only uses
one BRAM per way per cache on the Artix-7, since the BRAMs were only
half-used previously.
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
Paul Mackerras [Sun, 10 May 2020 08:18:03 +0000 (18:18 +1000)]
core: Remove fetch2 pipeline stage
The fetch2 stage existed primarily to provide a stash buffer for the
output of icache when a stall occurred. However, we can get the same
effect -- of having the input to decode1 stay unchanged on a stall
cycle -- by using the read enable of the BRAMs in icache, and by
adding logic to keep the outputs unchanged on a clock cycle when
stall_in = 1. This reduces branch and interrupt latency by one
cycle.
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
Paul Mackerras [Thu, 14 May 2020 03:25:48 +0000 (13:25 +1000)]
Add core logging
This logs 256 bits of data per cycle to a ring buffer in BRAM. The
data collected can be read out through 2 new SPRs or through the
debug interface.
The new SPRs are LOG_ADDR (724) and LOG_DATA (725). LOG_ADDR contains
the buffer write pointer in the upper 32 bits (in units of entries,
i.e. 32 bytes) and the read pointer in the lower 32 bits (in units of
doublewords, i.e. 8 bytes). Reading LOG_DATA gives the doubleword
from the buffer at the read pointer and increments the read pointer.
Setting bit 31 of LOG_ADDR inhibits the trace log system from writing
to the log buffer, so the contents are stable and can be read.
There are two new debug addresses which function similarly to the
LOG_ADDR and LOG_DATA SPRs. The log is frozen while either or both of
the LOG_ADDR SPR bit 31 or the debug LOG_ADDR register bit 31 are set.
The buffer defaults to 2048 entries, i.e. 64kB. The size is set by
the LOG_LENGTH generic on the core_debug module. Software can
determine the length of the buffer because the length is ORed into the
buffer write pointer in the upper 32 bits of LOG_ADDR. Hence the
length of the buffer can be calculated as 1 << (31 - clz(LOG_ADDR)).
There is a program to format the log entries in a somewhat readable
fashion in scripts/fmt_log/fmt_log.c. The log_entry struct in that
file describes the layout of the bits in the log entries.
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
Paul Mackerras [Sat, 13 Jun 2020 09:59:17 +0000 (19:59 +1000)]
scripts/mw_debug: Make progress counts display on one line
This outputs a carriage return rather than a newline after the
display of the progress count during the load and save operations.
This makes the output more compact and better looking.
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
Paul Mackerras [Thu, 11 Jun 2020 04:57:30 +0000 (14:57 +1000)]
tests/xics: Fix assumption that interrupts happen immediately
Currently the test writes to the XICS and then checks that the
expected interrupt has happened. This turns into a stbcix
instruction followed immediately by a load from the variable that
indicates whether an interrupt has happened. It is possible for
it to take a few cycles for the store to reach the XICS and the
interrupt request signal to come back to the core, particularly
with improvements to the load/store unit and dcache.
This therefore adds a delay between storing to the XICS and
checking for the occurrence of an interrupt, so as to give the
signals time to propagate. The delay loop does an arbitrary 10
iterations, and each iteration does two loads and one store to
(cacheable) memory.
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
Paul Mackerras [Sat, 13 Jun 2020 07:22:56 +0000 (17:22 +1000)]
register_file: Report value being written before asserting it's not X
If a bug causes an indeterminate value to be written to a GPR, an
assert causes simulation to abort. Move the assert after the report
of the GPR index and value so that we get to know what the bad value
is before the simulation terminates.
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
Paul Mackerras [Sat, 13 Jun 2020 02:36:16 +0000 (12:36 +1000)]
Merge pull request #205 from ozbenh/timing
Timing improvements
Paul Mackerras [Sat, 13 Jun 2020 02:27:40 +0000 (12:27 +1000)]
Merge pull request #204 from ozbenh/spi
Add an SPI master flash controller
Benjamin Herrenschmidt [Fri, 12 Jun 2020 11:48:01 +0000 (21:48 +1000)]
syscon: Remove combinational loop on ack and stall
Those hurt timings. Instead latch the wishbone response for one cycle
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Benjamin Herrenschmidt [Fri, 12 Jun 2020 11:47:06 +0000 (21:47 +1000)]
bram: Remove combinational loop on stall
It hurts timing and is pointless
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Benjamin Herrenschmidt [Fri, 12 Jun 2020 11:46:37 +0000 (21:46 +1000)]
uart: Remove combinational loops on ack and stall signal
They hurt timing forcing signals to come from the master and back
again in one cycle. Stall isn't sampled by the master unless there
is an active cycle so masking it with cyc is pointless. Masking acks
is somewhat pointless too as we don't handle early dropping of cyc
in any of our slaves properly anyways.
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Benjamin Herrenschmidt [Wed, 10 Jun 2020 03:35:18 +0000 (13:35 +1000)]
spi: Add booting from flash to litedram init
It will look for an ELF binary at the flash offset specified
for the board (currently 0x300000 on Arty but that could be
changed).
Note: litedram is regenerated in order to rebuild the init code,
which was done using a newer version of litedram from LiteX.
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Benjamin Herrenschmidt [Wed, 10 Jun 2020 03:35:10 +0000 (13:35 +1000)]
spi: Add simulation support
This require the s25fl128s.vhd flash model and FMF libraries,
which will be built when passed to the Makefile via the
FLASH_MODEL_PATH argument. Otherwise a dummy module is used
which ties MISO to '1'.
The model isn't included as I'm not sure its licence (GPL) is
at this point, but it can be obtained from
https://github.com/ozbenh/microspi
FLASH_MODEL_PATH=<path to microspi>/model
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Dan Horák [Fri, 12 Jun 2020 22:46:28 +0000 (00:46 +0200)]
flash-arty: update error message (#203)
Signed-off-by: Dan Horák <dan@danny.cz>
Benjamin Herrenschmidt [Fri, 12 Jun 2020 22:44:43 +0000 (08:44 +1000)]
dmi: Add ASYNC_REG attribute on synchronizers (#200)
This tells Vivado to keep them close among other things
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Benjamin Herrenschmidt [Fri, 12 Jun 2020 22:43:47 +0000 (08:43 +1000)]
icache: Latch PLRU victim output (#199)
This stores the output of the PLRU big mux and clears the
tags and valid bits on the next cycle.
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Paul Mackerras [Fri, 12 Jun 2020 22:01:55 +0000 (08:01 +1000)]
Merge pull request #198 from ozbenh/litedram
Litedram: Timing improvements
Benjamin Herrenschmidt [Fri, 5 Jun 2020 01:32:08 +0000 (11:32 +1000)]
spi: Add SPI Flash controller
This adds an SPI flash controller which supports direct
memory-mapped access to the flash along with a manual
mode to send commands.
The direct mode can be set via generic to default to single
wire or quad mode. The controller supports normal, dual and quad
accesses with configurable commands, clock divider, dummy clocks
etc...
The SPI clock can be an even divider of sys_clk starting at 2
(so max 50Mhz with our typical Arty designs).
A flash offset is carried via generics to syscon to tell SW about
which portion of the flash is reserved for the FPGA bitfile. There
is currently no plumbing to make the CPU reset past that address (TBD).
Note: Operating at 50Mhz has proven unreliable without adding some
delay to the sampling of the input data. I'm working in improving
this, in the meantime, I'm leaving the default set at 25 Mhz.
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Benjamin Herrenschmidt [Thu, 11 Jun 2020 10:18:24 +0000 (20:18 +1000)]
litedram: L2 use latched refill_index
Not a huge difference since wb_req is itself a latch but
may as well
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Benjamin Herrenschmidt [Wed, 10 Jun 2020 13:45:42 +0000 (23:45 +1000)]
litedram: Pipeline store acks in L2
There is a long timing path to generate the ack signal from
the L2 cache as it's fully combinational for stores, including
signals coming from litedram.
Instead, pipeline the store acks. This will introduce a cycle
latency but should improve timing. Also the core will eventually
be smart enough not to wait for store acks to complete them anyway.
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Benjamin Herrenschmidt [Wed, 10 Jun 2020 09:06:02 +0000 (19:06 +1000)]
arty/nexys-video: Update XDC
The DRAM related pins have some small changes in LiteX, so resync
and add the false path information as well.
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Benjamin Herrenschmidt [Wed, 10 Jun 2020 06:47:18 +0000 (16:47 +1000)]
litedram: Add stash buffer to the L2 cache wishbone interface
This breaks the long stall signal coming back to the processor
and helps improve overall timing.
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Benjamin Herrenschmidt [Wed, 10 Jun 2020 08:00:12 +0000 (18:00 +1000)]
litedram: Defer clearing of tags & valids to improve timing
Currently, there's a huge mux gathering the output of all the PLRUs
to select the victim way on cache miss. This is fed combinationally
into the clearing of the valid and tags.
In order to help timing, let's store it instead and perform the
clearing on the next cycle. The L2 doesn't respond to requests
when not in IDLE state so this should have no negative effects.
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Benjamin Herrenschmidt [Wed, 10 Jun 2020 07:58:27 +0000 (17:58 +1000)]
litedram: Improve dram_tb error output
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Anton Blanchard [Fri, 12 Jun 2020 00:25:09 +0000 (10:25 +1000)]
Merge pull request #201 from mikey/github-actions
Move from travis to github workflows
Michael Neuling [Tue, 9 Jun 2020 23:57:15 +0000 (09:57 +1000)]
Move from travis to github workflow
Github workflow gives us longer run times and faster startup.
Major kudos for this goes to @eine for the initial version and for
pushing us in this direction.
Signed-off-by: Michael Neuling <mikey@neuling.org>
Paul Mackerras [Wed, 10 Jun 2020 09:37:01 +0000 (19:37 +1000)]
Merge pull request #194 from ozbenh/misc
Fix syscon registers usage and add "save" function to mw_debug
Benjamin Herrenschmidt [Wed, 10 Jun 2020 03:14:00 +0000 (13:14 +1000)]
gitignore: Add more exlusions
litedram build directory used by the generator and the
verilator obj_dir can be taken out
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Benjamin Herrenschmidt [Tue, 9 Jun 2020 22:36:44 +0000 (08:36 +1000)]
litedram: Fix DRAM init mem using too many address bits
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Benjamin Herrenschmidt [Fri, 5 Jun 2020 12:28:30 +0000 (22:28 +1000)]
litedram: Remove remnants of riscv-inits
We still had some wires bringing an extra serial port out of
litedram for the built-in riscv processor. This is all gone now
so take them out.
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Benjamin Herrenschmidt [Thu, 4 Jun 2020 10:25:57 +0000 (20:25 +1000)]
mw_debug: Add "save" function to save memory to a file
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Benjamin Herrenschmidt [Thu, 4 Jun 2020 01:56:47 +0000 (11:56 +1000)]
sw: Properly mask syscon register fields
Some fields might get extended with extra bits, use the appropriate
masks when reading the values.
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Michael Neuling [Tue, 9 Jun 2020 23:54:35 +0000 (09:54 +1000)]
Merge pull request #196 from ozbenh/makefile-lib-fix
Makefile: Improve unisim library generation
Michael Neuling [Tue, 9 Jun 2020 23:22:50 +0000 (09:22 +1000)]
Merge pull request #195 from shenki/nexys-video
Nexys video
Benjamin Herrenschmidt [Tue, 9 Jun 2020 22:31:49 +0000 (08:31 +1000)]
Makefile: Improve unisim library generation
The rewrite of the Makefile to use "ghdl -c" somewhat broke building
the unisim library as ghdl doesn't yet support putting files in
separate libraries from a single command line invocation.
The workaround at the time was to put the entire project in "unisim"
which is ... weird and will break if we try to add another library
such as fmf.
This fixes it by generating the library separately using "ghdl -i"
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Joel Stanley [Tue, 9 Jun 2020 01:52:57 +0000 (11:22 +0930)]
flash-arty: Re-add support for running from any path
The changes in
d3c274d01ec1 ("flash-arty: Add support for specifying the file type")
added a local jtagspi.cfg, which meant openocd must be run from the root
of the microwatt directory.
This puts the content into the xilinx-xc7.cfg so the script can be used
from any path again.
Signed-off-by: Joel Stanley <joel@jms.id.au>
Joel Stanley [Tue, 9 Jun 2020 00:42:42 +0000 (10:12 +0930)]
flash-arty: Support Nexys Video's a200
Not an Arty but Anton tests on this board.
Signed-off-by: Joel Stanley <joel@jms.id.au>
Michael Neuling [Fri, 5 Jun 2020 10:17:01 +0000 (20:17 +1000)]
Merge pull request #193 from paulusmack/master
Minor improvements and reformatting
Paul Mackerras [Fri, 5 Jun 2020 08:02:33 +0000 (18:02 +1000)]
Merge pull request #182 from mikey/travis
Travis and testing improvements
Benjamin Herrenschmidt [Fri, 5 Jun 2020 06:23:23 +0000 (16:23 +1000)]
icache: Fix icbi potentially clobbering the icache (#192)
icbi currently just resets the icache. This has some nasty side
effects such as also clearing the TLB, but also the wishbone interface.
That means that any ongoing cycle will be dropped.
However, most of our slaves don't handle that well and will continue
sending acks for already issued requests.
Under some circumstances we can thus restart an icache load and get
spurious ack/data from the wishbone left over from the "cancelled"
sequence.
This has broken booting Linux for me.
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>