Florent Kermarrec [Fri, 4 Oct 2019 08:00:45 +0000 (10:00 +0200)]
litex_setup: add litejesd204b
enjoy-digital [Tue, 1 Oct 2019 19:40:56 +0000 (21:40 +0200)]
Merge pull request #270 from gsomlo/gls-csr-upper
soc/integration: ensure CSR constants are in uppercase
Florent Kermarrec [Tue, 1 Oct 2019 19:30:14 +0000 (21:30 +0200)]
soc/cores/icap: simplify ICAPBitstream (untested)
Florent Kermarrec [Tue, 1 Oct 2019 19:04:49 +0000 (21:04 +0200)]
soc/cores/icap: rename ICAP to ICAPBistream and revert old ICAP
enjoy-digital [Tue, 1 Oct 2019 18:55:28 +0000 (20:55 +0200)]
Merge pull request #269 from antmicro/rework_icap
soc: cores: support sending custom bitstream to ICAP
Gabriel Somlo [Tue, 1 Oct 2019 16:14:33 +0000 (12:14 -0400)]
soc/integration: ensure CSR constants are in uppercase
Fixup over commit
8be5824e.
Signed-off-by: Gabriel Somlo <gsomlo@gmail.com>
Jan Kowalewski [Tue, 17 Sep 2019 19:35:53 +0000 (21:35 +0200)]
soc: cores: support sending custom bitstream to ICAP
This adds FIFO that can be used to send any
sequence of commands to the ICAP controller.
Florent Kermarrec [Mon, 30 Sep 2019 21:31:34 +0000 (23:31 +0200)]
soc/interconnect: rename stream_packet to packet & cleanup (with retro-compat)
Florent Kermarrec [Mon, 30 Sep 2019 21:18:39 +0000 (23:18 +0200)]
soc/interconnect/stream: add separators, mode Actor modules just after Endpoint
Florent Kermarrec [Mon, 30 Sep 2019 14:00:11 +0000 (16:00 +0200)]
soc_zynq: update get_csr_header
Florent Kermarrec [Mon, 30 Sep 2019 09:32:07 +0000 (11:32 +0200)]
soc/integration: move cpu_interface retro-compatibility to litex/__init__
Florent Kermarrec [Mon, 30 Sep 2019 08:59:36 +0000 (10:59 +0200)]
soc/integration: use dicts for constants/mem_regions/csr_regions to cleanup/simplify iterations on theses
Florent Kermarrec [Mon, 30 Sep 2019 06:30:45 +0000 (08:30 +0200)]
cpu: remove initial SERV support (we'll work in a branch to experiment with it)
Florent Kermarrec [Mon, 30 Sep 2019 06:26:38 +0000 (08:26 +0200)]
soc_core: fix cpu_type=None case and add test for it
Florent Kermarrec [Sun, 29 Sep 2019 15:33:16 +0000 (17:33 +0200)]
soc_sdram: remove axi usecase, this was only useful to do some preliminary axi tests.
Proper AXI support will be added in the future for SoCs.
Florent Kermarrec [Sun, 29 Sep 2019 15:31:37 +0000 (17:31 +0200)]
soc_core: cleanup/re-align
Florent Kermarrec [Sun, 29 Sep 2019 15:23:01 +0000 (17:23 +0200)]
soc/integration: rename cpu_interface to export (with retro-compat), re-arrange a bit, add separators
Florent Kermarrec [Sun, 29 Sep 2019 15:12:15 +0000 (17:12 +0200)]
test/test_targets: update cpu-type to mor1kx
Florent Kermarrec [Sun, 29 Sep 2019 15:04:21 +0000 (17:04 +0200)]
soc/cores: uniformize (continue)
Florent Kermarrec [Sun, 29 Sep 2019 14:10:44 +0000 (16:10 +0200)]
soc/cores/gpio: uniformize with others cores
Florent Kermarrec [Sun, 29 Sep 2019 14:08:39 +0000 (16:08 +0200)]
soc/cores: rename frequency_meter to freqmeter and uniformize with others cores
Florent Kermarrec [Sun, 29 Sep 2019 14:02:04 +0000 (16:02 +0200)]
soc/cores/ecc: improve readibility, uniformize with others cores
Florent Kermarrec [Sun, 29 Sep 2019 13:58:22 +0000 (15:58 +0200)]
soc/cores/clocks: improve readibility
Florent Kermarrec [Sun, 29 Sep 2019 13:47:10 +0000 (15:47 +0200)]
soc_core: use cpu.data_width to compute csr_alignment (and remove Rocket workaround)
Florent Kermarrec [Sun, 29 Sep 2019 13:41:18 +0000 (15:41 +0200)]
soc/cores/cpus: improve ident/align, uniformize between cpus
Florent Kermarrec [Sun, 29 Sep 2019 13:05:29 +0000 (15:05 +0200)]
soc/cores/cpu: add CPU class and make all CPU inheritate from it
Also rename reserved_interrupts to interrupts (empty dict is no reserved interrupts)
Florent Kermarrec [Sun, 29 Sep 2019 12:38:07 +0000 (14:38 +0200)]
soc_sdram: move ControllerInjector to LiteDRAM (LiteDRAMCore)
Florent Kermarrec [Sun, 29 Sep 2019 12:22:26 +0000 (14:22 +0200)]
soc/integration: add common.py and move helpers from soc_core to it
Florent Kermarrec [Sat, 28 Sep 2019 17:04:38 +0000 (19:04 +0200)]
soc_core: avoid manual listing of support CPUs, just use CPU.keys()
Florent Kermarrec [Sat, 28 Sep 2019 17:01:41 +0000 (19:01 +0200)]
soc_core: remove add_cpu_or_bridge retro-compatibility (most of the designs have been updated since the change)
Florent Kermarrec [Sat, 28 Sep 2019 16:59:30 +0000 (18:59 +0200)]
integration/soc_core: remove csr_map_update (no longer used)
Florent Kermarrec [Sat, 28 Sep 2019 12:13:39 +0000 (14:13 +0200)]
soc_core/cpu: move memory map override to CPUs, select reset_address after eventual memory map has override been done
Florent Kermarrec [Sat, 28 Sep 2019 10:35:41 +0000 (12:35 +0200)]
soc/cores/cpu: add set_reset_address method and use it instead of passing reset_address as a parameter
Florent Kermarrec [Sat, 28 Sep 2019 10:09:55 +0000 (12:09 +0200)]
soc/cores/cpu: do instance in do_finalize for all cpus (allow updating parameters until the design is generated)
Florent Kermarrec [Fri, 27 Sep 2019 22:55:08 +0000 (00:55 +0200)]
cores/cpu: define CPUS and simplify instance
Florent Kermarrec [Fri, 27 Sep 2019 22:42:00 +0000 (00:42 +0200)]
soc_core/serv: use UART_POLLING (no interrupt support)
Florent Kermarrec [Fri, 27 Sep 2019 22:41:28 +0000 (00:41 +0200)]
add SERV submodule
Florent Kermarrec [Fri, 27 Sep 2019 22:35:26 +0000 (00:35 +0200)]
software/libbase/uart: add polling mode
Florent Kermarrec [Fri, 27 Sep 2019 22:17:00 +0000 (00:17 +0200)]
add SERV CPU initial support (not working)
Florent Kermarrec [Wed, 25 Sep 2019 12:09:44 +0000 (14:09 +0200)]
targets/ulx3s: revert to cl=2
Florent Kermarrec [Wed, 25 Sep 2019 12:07:28 +0000 (14:07 +0200)]
boards/netv2: switch to MVP, add spiflashx4 and hdmi in/out
Florent Kermarrec [Tue, 24 Sep 2019 15:55:29 +0000 (17:55 +0200)]
wishbone2csr: refactor using FSM, reduce latency (make it asynchronous) and set csr.adr only when access is done (allow use of CSR/CSRBase we signal)
Making it asynchronous does not seem to deteriorate timing or resource usage, if it's the case for some designs, we'll add a register parameter.
Florent Kermarrec [Tue, 24 Sep 2019 15:51:06 +0000 (17:51 +0200)]
csr: add we signal to CSR, CSRStatus
Doing actions on register read is generally not a good design practice (it's
better to do separate register write to trigger actions) but in some very
specific cases being able to know that register has been read can solve cases
that are difficult to do with the recommended practives and that can justify
doing an exception.
This commit add a we signal to CSR, CSRStatus and this allow the logic to know
when the CSR, CSRStatus is read.
Florent Kermarrec [Tue, 24 Sep 2019 12:40:48 +0000 (14:40 +0200)]
build/xilinx/programmer: fix vivado_cmd
Florent Kermarrec [Tue, 24 Sep 2019 08:11:31 +0000 (10:11 +0200)]
soc/integration/doc: replace "== None" by "is None"
enjoy-digital [Tue, 24 Sep 2019 08:09:22 +0000 (10:09 +0200)]
Merge pull request #266 from xobs/add-moduledoc-autodoc
Add ModuleDoc and AutoDoc
Florent Kermarrec [Tue, 24 Sep 2019 06:49:00 +0000 (08:49 +0200)]
tools/litex_read_verilog: also delete yosys_v2j.ys
Benjamin Herrenschmidt [Tue, 24 Sep 2019 06:40:22 +0000 (08:40 +0200)]
soc_core/sdram: Don't blow up if _wb_sdram_ifs or _csr_masters are empty
For example a standalone controller with no exposed CSRs (probably not
a very useful configuration but I really don't like python backtraces)
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Sean Cross [Tue, 24 Sep 2019 06:34:41 +0000 (14:34 +0800)]
timer: inherit ModuleDoc
With the new ModuleDoc class, we can inherit `ModuleDoc` and
automatically get module-level documentation.
This patch also corrects a typo in `timer` that causes an error in
sphinx.
Signed-off-by: Sean Cross <sean@xobs.io>
Sean Cross [Tue, 24 Sep 2019 06:30:28 +0000 (14:30 +0800)]
integration: add ModuleDoc and AutoDoc
It is important to be able to document modules other than CSRs.
This patch adds ModuleDoc and AutoDoc, both of which can be used
together to document modules.
ModuleDoc can be used to transform the __doc__ string of a class into a
reference-manual section. Alternately, it can be used to add additional
sections to a module.
AutoDoc is used to gather all submodule ModuleDoc objects in order to
traverse the tree of documentation.
Signed-off-by: Sean Cross <sean@xobs.io>
enjoy-digital [Mon, 23 Sep 2019 21:19:45 +0000 (23:19 +0200)]
Merge pull request #264 from antmicro/mor1kx_linux
Enable to run Linux on mork1x
Florent Kermarrec [Mon, 23 Sep 2019 13:57:14 +0000 (15:57 +0200)]
soc_core: set csr to 0x00000000 when there is no wishbone
Florent Kermarrec [Mon, 23 Sep 2019 13:53:07 +0000 (15:53 +0200)]
soc_sdram: Don't add the L2 Cache when there's no wishbone bus
Filip Kokosinski [Thu, 19 Sep 2019 10:23:05 +0000 (12:23 +0200)]
soc_core: adapt memory map for mainline Linux with mor1kx
Mainline Linux expects it to be loaded at the physical address of 0x0.
Change the MAIN_RAM base address to 0x0 and update exception vector
during the booting process.
Filip Kokosinski [Mon, 23 Sep 2019 11:45:46 +0000 (13:45 +0200)]
boards/targets: increase integrated ROM size if EthernetSoC is used
Currently section '.rodata' of the LiteX BIOS doesn't fit in the 'rom'
region if mor1kx is used with EthernetSoC. Increase the integrated ROM
size from 0x8000 to 0x10000 in EthernetSoC.
Florent Kermarrec [Mon, 23 Sep 2019 10:53:37 +0000 (12:53 +0200)]
soc_core: revert wishbone2csr to __init__ but add with_wishbone parameter
Florent Kermarrec [Mon, 23 Sep 2019 08:15:27 +0000 (10:15 +0200)]
soc_sdram: change l2_size checks order
Florent Kermarrec [Mon, 23 Sep 2019 07:58:47 +0000 (09:58 +0200)]
soc_core: move CSR bridge to finalize (only generate it if there is a wishbone master), revert default parameter when cpu_type is None (we have systems with cpu_type=None but that are using these peripherals)
Florent Kermarrec [Mon, 23 Sep 2019 07:26:47 +0000 (09:26 +0200)]
integration/builder: avoid specific _generate_standalone_includes
Benjamin Herrenschmidt [Mon, 23 Sep 2019 06:39:25 +0000 (08:39 +0200)]
This will allow it to be built for microwatt out of tree
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Benjamin Herrenschmidt [Mon, 23 Sep 2019 06:33:35 +0000 (08:33 +0200)]
soc_core: When cpu_type is "None", let's not generate useless UART, timer, ROMs, wishbone to CSR bridge etc...
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Benjamin Herrenschmidt [Mon, 23 Sep 2019 06:30:01 +0000 (08:30 +0200)]
integration/builder: When the CPU is "None", we used to not generate any code.
With this change, we will now generate csr.h and sdram_phy.h, which
will be needed by the initialization code running on the host CPU.
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
enjoy-digital [Fri, 20 Sep 2019 06:28:19 +0000 (08:28 +0200)]
Merge pull request #263 from xobs/spi-flash-csrfield
spi_flash: document register fields
Sean Cross [Fri, 20 Sep 2019 04:11:59 +0000 (12:11 +0800)]
spi_flash: document register fields
Document the various fields present in the SPI flash bitbang interface.
This adds documentation for the Single and DualQuad modules.
Signed-off-by: Sean Cross <sean@xobs.io>
enjoy-digital [Fri, 20 Sep 2019 04:25:57 +0000 (06:25 +0200)]
Merge pull request #262 from jersey99/master
vivado just needs to be in the path for the programmer as well
Vamsi K Vytla [Fri, 20 Sep 2019 03:35:55 +0000 (20:35 -0700)]
vivado just needs to be in the path for the programmer as well
enjoy-digital [Thu, 19 Sep 2019 09:40:55 +0000 (11:40 +0200)]
Merge pull request #261 from xobs/event-documentation
csr_eventmanager: add `name` and `description` args
Sean Cross [Thu, 19 Sep 2019 09:23:03 +0000 (17:23 +0800)]
csr_eventmanager: add `name` and `description` args
Add `name` and `description` as optional arguments to the various
EventSource types. These default to `None`, so this should be a
backwards-compatible change.
Use the same trick as CSRs, where we default the `name` to be the
instantiated object name as read from the Migen `get_obj_var_name()`
call.
Signed-off-by: Sean Cross <sean@xobs.io>
Florent Kermarrec [Thu, 19 Sep 2019 07:18:16 +0000 (09:18 +0200)]
cores/timer: add general documentation on Timer implementation and behavior.
Florent Kermarrec [Thu, 19 Sep 2019 03:16:01 +0000 (05:16 +0200)]
soc_sdram: improve readibility and convert l2_size to minimal allowed if provided l2_size is lower
Florent Kermarrec [Wed, 18 Sep 2019 08:47:54 +0000 (10:47 +0200)]
csr: add description to CSRStorage/CSRStatus attributes (thanks xobs)
Florent Kermarrec [Wed, 18 Sep 2019 08:45:38 +0000 (10:45 +0200)]
soc/cores/timer: fix typo (thanks xobs)
Florent Kermarrec [Wed, 18 Sep 2019 08:14:47 +0000 (10:14 +0200)]
soc/cores/timer/doc: rewrite a little bit, avoid some redundancy, change ident.
enjoy-digital [Wed, 18 Sep 2019 07:36:53 +0000 (09:36 +0200)]
Merge pull request #259 from xobs/document-timer
timer: add documentation
Sean Cross [Wed, 18 Sep 2019 07:06:20 +0000 (15:06 +0800)]
timer: add documentation
Now that CSRs have documentation support, add documentation to the basic
`Timer` module.
Signed-off-by: Sean Cross <sean@xobs.io>
Florent Kermarrec [Mon, 16 Sep 2019 15:02:55 +0000 (17:02 +0200)]
soc/cores/spi: use new CSRField (no functional change)
Florent Kermarrec [Mon, 16 Sep 2019 14:56:00 +0000 (16:56 +0200)]
soc/cores/bitbang: use new CSRField (no functional change)
enjoy-digital [Mon, 16 Sep 2019 07:16:20 +0000 (09:16 +0200)]
Merge pull request #257 from enjoy-digital/csr_fields
soc/interconnect/csr: add CSRField/documentation support, do some simplification on CSRStorage
Florent Kermarrec [Mon, 16 Sep 2019 06:48:05 +0000 (08:48 +0200)]
csr: update copyrights
Florent Kermarrec [Mon, 16 Sep 2019 06:45:29 +0000 (08:45 +0200)]
csr: more documentation
Florent Kermarrec [Mon, 16 Sep 2019 06:38:26 +0000 (08:38 +0200)]
csr/CSRStorage: remove storage_full (was only needed by alignment_bits)
Florent Kermarrec [Mon, 16 Sep 2019 06:36:25 +0000 (08:36 +0200)]
csr: use IntEnum for CSRAccess
Florent Kermarrec [Sun, 15 Sep 2019 17:47:48 +0000 (19:47 +0200)]
csr/CSRStorage: remove alignment_bits: complexify too much code for the few use-cases it's really useful
Florent Kermarrec [Sun, 15 Sep 2019 17:08:30 +0000 (19:08 +0200)]
csr/fields: document, add separators, 100 characters per line
Florent Kermarrec [Sat, 14 Sep 2019 19:57:23 +0000 (21:57 +0200)]
csr/fields: add access parameter
Florent Kermarrec [Sat, 14 Sep 2019 19:49:34 +0000 (21:49 +0200)]
csr/fields: add pulse mode support
Florent Kermarrec [Fri, 13 Sep 2019 18:01:31 +0000 (20:01 +0200)]
soc/interconnect/csr: add initial field support
Florent Kermarrec [Thu, 12 Sep 2019 15:07:56 +0000 (17:07 +0200)]
build/openocd: add set_qe parameter to flash
QE bit is not set on blank SPI flashes and need to be set when SPI X4 is enabled in the bistream to load the FPGA.
Florent Kermarrec [Thu, 12 Sep 2019 08:21:37 +0000 (10:21 +0200)]
tools/litex_term/upload: bufferize only chunks of the file instead of the entire file to speedup upload when used on embedded devices (RPI for example)
Florent Kermarrec [Wed, 11 Sep 2019 16:30:28 +0000 (18:30 +0200)]
soc/integration/cpu_interface: don't raise OSError if we are not going to compile software and compilation toolchain is not found
Florent Kermarrec [Tue, 10 Sep 2019 10:41:05 +0000 (12:41 +0200)]
soc/integration/builder: call do_exit with vns when build is done.
Florent Kermarrec [Mon, 9 Sep 2019 13:12:24 +0000 (15:12 +0200)]
Merge branch 'master' of github.com/enjoy-digital/litex
Florent Kermarrec [Mon, 9 Sep 2019 13:12:08 +0000 (15:12 +0200)]
soc/itnegration: update litedram
enjoy-digital [Mon, 9 Sep 2019 11:38:29 +0000 (13:38 +0200)]
Merge pull request #255 from sergachev/fix-crc32
fix crc32
Ilia Sergachev [Mon, 9 Sep 2019 11:19:43 +0000 (13:19 +0200)]
fix crc32
Florent Kermarrec [Mon, 9 Sep 2019 09:02:14 +0000 (11:02 +0200)]
interconnect/wishbone: add FlipFlop to allow UpConverter to be used
Note: a test should be added for Converter and DownConverter/UpConverter should be cleaned up
Florent Kermarrec [Fri, 6 Sep 2019 09:57:18 +0000 (11:57 +0200)]
build/openocd: add stream method for JTAG UART
Florent Kermarrec [Fri, 6 Sep 2019 09:56:42 +0000 (11:56 +0200)]
soc_core: add JTAG UART support (uart_name="jtag_uart)
Florent Kermarrec [Fri, 6 Sep 2019 09:55:41 +0000 (11:55 +0200)]
soc/cores/jtag: add Xilinx JTAG TAPs support and simple JTAG PHY (can be used for JTAG UART)
Florent Kermarrec [Thu, 5 Sep 2019 13:59:35 +0000 (15:59 +0200)]
soc_zynq: fix indent