Dan Horák [Thu, 23 Jan 2020 10:37:00 +0000 (11:37 +0100)]
make the sources volume mount SELinux friendly
Signed-off-by: Dan Horák <dan@danny.cz>
Anton Blanchard [Wed, 22 Jan 2020 04:15:48 +0000 (15:15 +1100)]
Merge pull request #146 from antonblanchard/vhpi-cleanup
Consolidate VHPI code
Anton Blanchard [Wed, 22 Jan 2020 03:50:45 +0000 (14:50 +1100)]
Consolidate VHPI code
We had many copies of the VHPI marshalling/unmarshalling code.
Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
Anton Blanchard [Wed, 22 Jan 2020 03:48:07 +0000 (14:48 +1100)]
Merge pull request #145 from antonblanchard/sim_console-fix
sim_console: Use cfmakeraw() and add option for ctrl-c to exit sim
Anton Blanchard [Wed, 22 Jan 2020 03:27:40 +0000 (14:27 +1100)]
sim_console: Use cfmakeraw() and add option for ctrl-c to exit sim
No need to open code a bunch of random termios flags, use cfmakeraw().
Most of the time we want ctrl-c to exit the current simulation, so
make that the default.
Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
Anton Blanchard [Tue, 21 Jan 2020 03:09:57 +0000 (14:09 +1100)]
Update Makefile.synth after Paul's patches
Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
Anton Blanchard [Tue, 21 Jan 2020 03:09:36 +0000 (14:09 +1100)]
Merge pull request #134 from paulusmack/master
Add bypass from execute1 output to input
Anton Blanchard [Tue, 21 Jan 2020 02:30:13 +0000 (13:30 +1100)]
Merge pull request #142 from antonblanchard/ghdl-synthesis-3
Initial support for ghdl synthesis
Anton Blanchard [Tue, 21 Jan 2020 02:28:43 +0000 (13:28 +1100)]
Merge pull request #144 from antonblanchard/update-README
Add some information about GHDL backend issues
Anton Blanchard [Tue, 21 Jan 2020 02:20:23 +0000 (13:20 +1100)]
Merge pull request #143 from antonblanchard/use-docker
Add an option to use Docker
Anton Blanchard [Tue, 21 Jan 2020 02:13:41 +0000 (13:13 +1100)]
Add some information about GHDL backend issues
A number of people have tripped up on GHDL backend issues. We
require either the LLVM or gcc backend, because the mcode backend
can't link against libraries which we use for simulated memory
and UART. Make that clearer, and point people at the Docker images
if they are having issues building ghdl.
Also point at the prebuilt micropython image.
Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
Anton Blanchard [Tue, 21 Jan 2020 02:03:50 +0000 (13:03 +1100)]
Add an option to use Docker
Some distros don't have a version of ghdl with the LLVM or GCC backend,
so add a Docker image as an alternative.
Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
Anton Blanchard [Fri, 17 Jan 2020 23:02:07 +0000 (10:02 +1100)]
Initial support for ghdl synthesis
A first pass at ghdl synthesis using yosys and nextpnr. It runs hello world
or micropython if the FPGA has enough block RAM (eg ECP5 85F). The hello
world testcase also loops UART rx to tx in software (ie not a hardware
loopback).
It uses Docker images, so no software needs to be installed. If you prefer
podman you can use that too. Edit Makefile.synth to configure your FPGA,
JTAG device etc.
To build:
make -f Makefile.synth
and to program:
make -f Makefile.synth prog
A few issues:
We need to add PLL support. Right now Microwatt runs at whatever the
external clock frequency is and the baud rate gets scaled by how far off
50MHz it is. This means on the ecp5-evn with a 12 MHz clock rate the baud
rate is a quite strange 27650 (115200 * 50 / 12). On my OrangeCrab with a
50MHz clock the UART is 115200.
It uses a large amount of resources, way more than it should. There are
still some ghdl/yosys issues to be sorted out.
Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
Anton Blanchard [Tue, 21 Jan 2020 00:41:41 +0000 (11:41 +1100)]
Merge pull request #140 from antonblanchard/rework-makefile
Fix Makefile dependency issue with files in vhdl/*
Anton Blanchard [Sun, 19 Jan 2020 23:50:45 +0000 (10:50 +1100)]
Fix Makefile dependency issue with files in vhdl/*
GHDL doesn't seem to have a way to specify the location of the object
file it writes, so right now they are all ending up in the root
directory. The Makefile rules did not reflect that, so make would
continually the files in fpga/*
Fix the rules to match what GHDL is doing.
Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
Anton Blanchard [Tue, 21 Jan 2020 00:11:30 +0000 (11:11 +1100)]
Merge pull request #141 from antonblanchard/update-dependencies.py
Improve dependencies.py and add a --synth option
Anton Blanchard [Mon, 20 Jan 2020 23:38:48 +0000 (10:38 +1100)]
Improve dependencies.py and add a --synth option
dependencies.py was pretty terrible at actually determining
dependencies. This improves it and also adds a --synth option.
Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
Anton Blanchard [Sun, 19 Jan 2020 11:44:32 +0000 (22:44 +1100)]
Merge pull request #136 from antonblanchard/uart-rx-metastability
Add a few FFs on the RX input to avoid metastability issues
Anton Blanchard [Sun, 19 Jan 2020 03:34:15 +0000 (14:34 +1100)]
Add a few FFs on the RX input to avoid metastability issues
Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
Anton Blanchard [Sun, 19 Jan 2020 11:02:56 +0000 (22:02 +1100)]
Merge pull request #139 from antonblanchard/reduce-mem
Reduce mem
Anton Blanchard [Sun, 19 Jan 2020 10:28:32 +0000 (21:28 +1100)]
Reduce simulated and default FPGA RAM to 384kB
Micropython has been able to fit into 384kB for ages, so lets reduce our
simulated RAM. This is useful for testing if micropython will run on an
ECP5 85k, which has enough BRAM for 384kB but not enough for 512kB.
Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
Anton Blanchard [Sun, 19 Jan 2020 10:18:05 +0000 (21:18 +1100)]
Add log2ceil and use it in bram code
We might want a non power of 2 amount of RAM in order to fit into an
FPGA, so create log2ceil and use it when calculating the number of
memory bits.
Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
Anton Blanchard [Sun, 19 Jan 2020 10:48:34 +0000 (21:48 +1100)]
Merge pull request #138 from antonblanchard/micropython-update
Update micropython
Anton Blanchard [Sun, 19 Jan 2020 09:22:09 +0000 (20:22 +1100)]
Update micropython
The current version of micropython in tests/micropython.bin is ancient.
Bug #135 points out that more recent versions are much smaller and they
also handle restart when ctrl+D is pressed.
Save all three versions of the file (elf, bin and hex) in micropython/
Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
Anton Blanchard [Sun, 19 Jan 2020 07:40:34 +0000 (18:40 +1100)]
Merge pull request #137 from antonblanchard/hello-world
hello_world updates
Anton Blanchard [Sun, 19 Jan 2020 05:15:22 +0000 (16:15 +1100)]
hello_world updates
Shrink hello_world a bit (from 12kB to 8kB).
Include the built images
Add 0x10 and 0x100 entry points
Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
Paul Mackerras [Tue, 14 Jan 2020 12:20:42 +0000 (23:20 +1100)]
decode1: Mark subfic as pipelined
This seems just to have been missed in commit
f291efa26690 ("decode1:
Mark ALU ops using carry as pipelined").
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
Paul Mackerras [Tue, 14 Jan 2020 10:55:33 +0000 (21:55 +1100)]
countzero: Add a register to help make timing
This adds a register in the middle of the countzero computation,
so that we now have two cycles to count leading or trailing zeroes
instead of just one. Execute1 now outputs a one-cycle stall signal
when it encounters a cntlz* or cnttz* instruction. With this,
the countzero path no longer fails timing on the Artix-7 at 100MHz.
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
Paul Mackerras [Mon, 13 Jan 2020 23:28:45 +0000 (10:28 +1100)]
Plumb loadstore1 input from execute1 not decode2
This allows us to use the bypass at the input of execute1 for the
address and data operands for loadstore1.
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
Paul Mackerras [Mon, 13 Jan 2020 02:23:42 +0000 (13:23 +1100)]
execute: Implement bypass from output of execute1 to input
This enables back-to-back execution of integer instructions where
the first instruction writes a GPR and the second reads the same
GPR. This is done with a set of multiplexers at the start of
execute1 which enable any of the three input operands to be taken
from the output of execute1 (i.e. r.e.write_data) rather than the
input from decode2 (i.e. e_in.read_data[123]).
This also requires changes to the hazard detection and handling.
Decode2 generates a signal indicating that the GPR being written
is available for bypass, which is true for instructions that are
executed in execute1 (rather than loadstore1/dcache). The
gpr_hazard module stores this "bypassable" bit, and if the same
GPR needs to be read by a subsequent instruction, it outputs a
"use_bypass" signal rather than generating a stall. The
use_bypass signal is then latched at the output of decode2 and
passed down to execute1 to control the input multiplexer.
At the moment there is no bypass on the inputs to loadstore1, but that
is OK because all load and store instructions are marked as
single-issue.
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
Paul Mackerras [Mon, 13 Jan 2020 07:13:09 +0000 (18:13 +1100)]
execute: Move popcnt and prty instructions into the logical unit
This implements logic in the logical entity to calculate the results
of the popcnt* and prty* instructions. We now have one insn_type_t
value for the 3 popcnt variants and one for the two prty variants,
using the length field of the decode_rom_t to distinguish between
them. The implementations in logical.vhdl using recursive
algorithms rather than the simple functions in ppc_fx_insns.vhdl.
This gives a saving of about 140 slice LUTs on the A7-100 and
improves timing slightly.
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
Paul Mackerras [Fri, 13 Dec 2019 04:48:54 +0000 (15:48 +1100)]
execute: Do comparisons using the main adder
This handles OP_CMP like a subtraction; the main adder computes
~RA + RB + 1, and the condition codes are computed from the results.
A direct comparison of the two input operands is used to calculate the
EQ bit of the condition result. The LT and GT bits are computed from
the MSB of the subtraction result, the carry out from the subtraction,
and the MSBs of the operands. For a 32-bit comparison, the 32-bit
carry and bit 31 of the result and input operands are used; for a
64-bit comparison, the 64-bit carry and bit 63 of the operands and
result are used.
It turns out to be more convenient to use the 'signed' field of
the decode table to distinguish signed from unsigned comparisons,
rather than the insn_type. Therefore this uses OP_CMP for both
cmp and cmpl, which also has the benefit of reducing the number
of values in insn_type_t.
Doing this saves over 200 slice LUTs on the Arty A7-100 and improves
timing slightly as well.
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
Paul Mackerras [Thu, 12 Dec 2019 04:25:45 +0000 (15:25 +1100)]
execute1: Move EXTS* instruction back into execute1
This moves the sign extension done by the extsb, extsh and extsw
instructions back into execute1. This means that we no longer need
any data formatting in writeback for results coming from execute1,
so this modifies writeback so the data formatter inputs come
directly from the loadstore unit output. The condition code
updates for RC=1 form instructions are now done on the value from
execute1 rather than the output of the data formatter, which should
help timing.
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
Paul Mackerras [Thu, 12 Dec 2019 00:21:25 +0000 (11:21 +1100)]
execute1: Remember dest GPR, RC, OE, XER for slow operations
For multiply and divide operations, execute1 now records the
destination GPR number, RC and OE from the instruction, and the
XER value. This means that the multiply and divide units don't
need to record those values and then send them back to execute1.
This makes the interface to those units a bit simpler. They
simply report an overflow signal along with the result value, and
execute1 takes care of updating XER if necessary.
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
Paul Mackerras [Wed, 11 Dec 2019 21:47:42 +0000 (08:47 +1100)]
Make divider hang off the side of execute1
With this, the divider is a unit that execute1 sends operands to and
which sends its results back to execute1, which then send them to
writeback. Execute1 now sends a stall signal when it gets a divide
or modulus instruction until it gets a valid signal back from the
divider. Divide and modulus instructions are no longer marked as
single-issue.
The data formatting step that used to be done in decode2 for div
and mod instructions is now done in execute1. We also do the
absolute value operation in that same cycle instead of taking an
extra cycle inside the divider for signed operations with a
negative operand.
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
Paul Mackerras [Tue, 10 Dec 2019 09:52:21 +0000 (20:52 +1100)]
Make multiplier hang off the side of execute1
With this, the multiplier isn't a separate pipe that decode2 issues
instructions to, but rather is a unit that execute1 sends operands
to and which sends the result back to execute1, which then sends it
to writeback. Execute1 now sends a stall signal when it gets a
multiply instruction until it gets a valid signal back from the
multiplier.
This all means that we no longer need to mark the multiply
instructions as single-issue.
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
Anton Blanchard [Sat, 11 Jan 2020 11:40:44 +0000 (22:40 +1100)]
Merge pull request #133 from antonblanchard/ghdl-synth
Ghdl synth
Anton Blanchard [Sat, 11 Jan 2020 11:07:42 +0000 (22:07 +1100)]
Merge pull request #132 from antonblanchard/bin2hex-move
Move bin2hex.py to scripts/
Anton Blanchard [Sat, 11 Jan 2020 10:31:48 +0000 (21:31 +1100)]
Move bin2hex.py to scripts/
Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
Anton Blanchard [Sat, 11 Jan 2020 06:13:23 +0000 (17:13 +1100)]
Fix a ghdlsynth issue in fast_spr_num
I've submitted a bug report for this, but we can work around it easily
for now.
Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
Anton Blanchard [Sat, 11 Jan 2020 03:49:06 +0000 (14:49 +1100)]
Fix a ghdlsynth issue in icache
ghdlsynth doesn't like the debug statement, so wrap it in a generate.
Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
Anton Blanchard [Sat, 11 Jan 2020 03:43:50 +0000 (14:43 +1100)]
Removed unused core_terminated signal
Right now it's unused. We can add it back when we add an LED to signify
the core has terminated.
Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
Anton Blanchard [Sat, 11 Jan 2020 03:34:25 +0000 (14:34 +1100)]
Fix some ghdlsynth issues with fpga_bram
Use to_integer() instead of conv_integer().
Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
Anton Blanchard [Sat, 11 Jan 2020 03:29:39 +0000 (14:29 +1100)]
Fix ghdlsynth issue in register file
We need to drive sim_dump_done to keep ghdlsynth happy.
Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
Anton Blanchard [Sat, 11 Jan 2020 03:28:20 +0000 (14:28 +1100)]
Remove unused signal
Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
Anton Blanchard [Sat, 11 Jan 2020 03:20:35 +0000 (14:20 +1100)]
Fix a ghdysynth inferred latch error in writeback
Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
Anton Blanchard [Sat, 11 Jan 2020 02:24:14 +0000 (13:24 +1100)]
Fix a ghdysynth inferred latch error in execute
It should never happen in practise, but ghdlsynth is complaining about
an inferred latch here. Fix it
Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
Anton Blanchard [Sat, 11 Jan 2020 01:32:57 +0000 (12:32 +1100)]
Merge pull request #131 from antonblanchard/new-tests
Dump CTR, LR and CR on sim termination, and update our tests
Anton Blanchard [Sat, 11 Jan 2020 01:16:21 +0000 (12:16 +1100)]
Upper 32 bits of XER should read as 0s
From the architecture:
bits 0:31 and 35:43 are treated as reserved and return 0s when read
using mfxer
Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
Anton Blanchard [Wed, 11 Dec 2019 01:24:46 +0000 (12:24 +1100)]
Dump CTR, LR and CR on sim termination, and update our tests
Right now our test cases fold the SPRs into the GPRs. That makes
debugging fails more difficult than it needs to be, so print
out the CTR, LR and CR.
We still need to print the XER, but that is in two spots in microwatt
and will take some more work.
This also adds many instructions to the tests that we have added
lately including overflow instructions, CR logicals and mt/mfxer.
Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
Anton Blanchard [Fri, 10 Jan 2020 23:10:13 +0000 (10:10 +1100)]
Merge pull request #127 from tomtor/CR-PR
Implement CRNOR and friends
Anton Blanchard [Fri, 10 Jan 2020 22:02:43 +0000 (09:02 +1100)]
Merge pull request #130 from antonblanchard/build-fix
control: Fix build issue with Fedora 31 version of GHDL
Anton Blanchard [Fri, 10 Jan 2020 20:35:37 +0000 (07:35 +1100)]
Merge pull request #129 from antonblanchard/update-micropython
Point to upstream micropython
Anton Blanchard [Fri, 10 Jan 2020 20:20:21 +0000 (07:20 +1100)]
Point to upstream micropython
Our changes are now merged upstream, so point there instead.
Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
Tom Vijlbrief [Fri, 3 Jan 2020 14:25:00 +0000 (15:25 +0100)]
Implement CRNOR and friends
Signed-off-by: Tom Vijlbrief <tvijlbrief@gmail.com>
Anton Blanchard [Sat, 4 Jan 2020 06:05:37 +0000 (17:05 +1100)]
Merge pull request #126 from sharkcz/docs
document packaged fusesoc for Fedora users
Dan Horák [Fri, 3 Jan 2020 14:09:27 +0000 (15:09 +0100)]
document packaged fusesoc for Fedora users
Signed-off-by: Dan Horák <dan@danny.cz>
Anton Blanchard [Wed, 11 Dec 2019 01:02:06 +0000 (12:02 +1100)]
control: Fix build issue with Fedora 31 version of GHDL
I'm hitting an issue with the Fedora 31 version of GHDL that
appears to be fixed upstream:
control.vhdl:105:39:error: actual expression must be globally static
Add a signal to get rid of error.
Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
Anton Blanchard [Mon, 9 Dec 2019 11:36:29 +0000 (22:36 +1100)]
Merge pull request #122 from paulusmack/benh-sprs
Benh sprs
Anton Blanchard [Mon, 9 Dec 2019 09:35:24 +0000 (20:35 +1100)]
Merge pull request #123 from antonblanchard/spi-conf
Add SPI configuration to Xilinx constraint files
Anton Blanchard [Mon, 9 Dec 2019 05:12:37 +0000 (16:12 +1100)]
Add SPI configuration to Xilinx constraint files
Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
Paul Mackerras [Thu, 5 Dec 2019 01:42:31 +0000 (12:42 +1100)]
decode2: Minor cleanup
Remove unused variable is_reg in decode_input_reg_a.
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
Benjamin Herrenschmidt [Thu, 31 Oct 2019 02:48:43 +0000 (13:48 +1100)]
sprs: Store common SPRs in register file
This stores the most common SPRs in the register file.
This includes CTR and LR and a not yet final list of others.
The register file is set to 64 entries for now. Specific types
are defined that can represent a GPR index (gpr_index_t) or
a GPR/SPR index (gspr_index_t) along with conversion functions
between the two.
On order to deal with some forms of branch updating both LR and
CTR, we introduced a delayed update of LR after a branch link.
Note: We currently stall the pipeline on such a delayed branch,
but we could avoid stalling fetch in that specific case as we
know we have a branch delay. We could also limit that to the
specific case where we need to update both CTR and LR.
This allows us to make bcreg, mtspr and mfspr pipelined. decode1
will automatically force the single issue flag on mfspr/mtspr to
a "slow" SPR.
[paulus@ozlabs.org - fix direction of decode2.stall_in]
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
Benjamin Herrenschmidt [Thu, 31 Oct 2019 01:09:14 +0000 (12:09 +1100)]
spr: Add translation from SPR to special GPR number
We will want to store some SPRs in the register file using
a set of "extra" registers. This provides a function for
doing the translation along with some SPR definitions.
This isn't used yet
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
Paul Mackerras [Sat, 7 Dec 2019 04:26:25 +0000 (15:26 +1100)]
divider: Fix overflow calculation
We were signalling overflow when neg_result=1 but the result was zero.
Fix this.
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
Paul Mackerras [Thu, 5 Dec 2019 21:25:28 +0000 (08:25 +1100)]
decode1: Add OE=1 forms of add/sub, mul and div instructions
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
Paul Mackerras [Sat, 7 Dec 2019 03:31:33 +0000 (14:31 +1100)]
execute: Copy XER[SO] to CR for cmp[i] and cmpl[i] instructions
We were copying in XER[SO] for the dot-form instructions but not the
explicit compare instructions. Fix this.
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
Benjamin Herrenschmidt [Wed, 30 Oct 2019 02:53:23 +0000 (13:53 +1100)]
Add basic XER support
The carry is currently internal to execute1. We don't handle any of
the other XER fields.
This creates type called "xer_common_t" that contains the commonly
used XER bits (CA, CA32, SO, OV, OV32).
The value is stored in the CR file (though it could be a separate
module). The rest of the bits will be implemented as a separate
SPR and the two parts reconciled in mfspr/mtspr in latter commits.
We always read XER in decode2 (there is little point not to)
and send it down all pipeline branches as it will be needed in
writeback for all type of instructions when CR0:SO needs to be
updated (such forms exist for all pipeline branches even if we don't
yet implement them).
To avoid having to track XER hazards, we forward it back in EX1. This
assumes that other pipeline branches that can modify it (mult and div)
are running single issue for now.
One additional hazard to beware of is an XER:SO modifying instruction
in EX1 followed immediately by a store conditional. Due to our writeback
latency, the store will go down the LSU with the previous XER value,
thus the stcx. will set CR0:SO using an obsolete SO value.
I doubt there exist any code relying on this behaviour being correct
but we should account for it regardless, possibly by ensuring that
stcx. remain single issue initially, or later by adding some minimal
tracking or moving the LSU into the same pipeline as execute.
Missing some obscure XER affecting instructions like addex or mcrxrx.
[paulus@ozlabs.org - fix CA32 and OV32 for OP_ADD, fix order of
arguments to set_ov]
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
Benjamin Herrenschmidt [Thu, 14 Nov 2019 04:25:28 +0000 (15:25 +1100)]
decode1: Mark ALU ops using carry as pipelined
There is no reason not to that I can think of
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
Benjamin Herrenschmidt [Wed, 30 Oct 2019 02:26:43 +0000 (13:26 +1100)]
cr_file: Check write_cr_enable
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
Anton Blanchard [Mon, 18 Nov 2019 03:07:16 +0000 (14:07 +1100)]
Merge pull request #120 from antonblanchard/spr-decode-cleanup
spr: Cleanup decoding of SPR numbers
Anton Blanchard [Mon, 18 Nov 2019 03:05:48 +0000 (14:05 +1100)]
Merge pull request #119 from antonblanchard/reduce-pipe-depth
control: Reduce pipeline depth to 1
Anton Blanchard [Fri, 15 Nov 2019 05:02:57 +0000 (16:02 +1100)]
Merge pull request #118 from antonblanchard/bus-pipeline
Bus pipeline
Benjamin Herrenschmidt [Thu, 31 Oct 2019 08:43:58 +0000 (19:43 +1100)]
control: Reduce pipeline depth to 1
To match our one stage execute.
This might change back if we end up adding 2 stages to match the
LSU, but in that case we'll want forwards as well.
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Benjamin Herrenschmidt [Thu, 31 Oct 2019 00:42:10 +0000 (11:42 +1100)]
spr: Cleanup decoding of SPR numbers
Use a function to obtain the integer number and use constants
with the architected numbers. Replace std_match with a case
statement.
This also has the side effect of returning 0 instead of some
random previous result on mfspr of an unknown SPR.
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Benjamin Herrenschmidt [Wed, 23 Oct 2019 04:06:39 +0000 (15:06 +1100)]
wb_arbiter: Early master selection
This flips the arbiter muxes on the same cycle as a new request
comes in, thus avoiding a cycle latency.
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Benjamin Herrenschmidt [Wed, 23 Oct 2019 03:28:12 +0000 (14:28 +1100)]
wb_arbiter: Make arbiter size parametric
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Benjamin Herrenschmidt [Wed, 23 Oct 2019 03:01:48 +0000 (14:01 +1100)]
wb_arbiter: Avoid IDLE cycle when not changing master
Consecutive accesses from the same master shouldn't need an IDLE
cycle. Completely remove the IDLE state and switch master when
the bus is idle, but stay on the last selected one between cycles.
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Benjamin Herrenschmidt [Wed, 23 Oct 2019 03:00:30 +0000 (14:00 +1100)]
ram: Ack stores early
Stores only need a single cycle, so we can ack them early if there
isn't an older ack already in the pipeline
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Benjamin Herrenschmidt [Wed, 23 Oct 2019 01:08:55 +0000 (12:08 +1100)]
ram: Rework main RAM interface
This replaces the simple_ram_behavioural and mw_soc_memory modules
with a common wishbone_bram_wrapper.vhdl that interfaces the
pipelined WB with a lower-level RAM module, along with an FPGA
and a sim variants of the latter.
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Benjamin Herrenschmidt [Tue, 22 Oct 2019 23:52:37 +0000 (10:52 +1100)]
Move log2/ispow2 to a utils package
(Out of icache and dcache)
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Benjamin Herrenschmidt [Tue, 22 Oct 2019 05:05:18 +0000 (16:05 +1100)]
ram: Add block RAM pipelining
This adds an output buffer to help with timing and allows the BRAMs
to actually pipeline.
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Benjamin Herrenschmidt [Mon, 21 Oct 2019 11:57:51 +0000 (22:57 +1100)]
decode: Reformat decode_types.vhdl
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Benjamin Herrenschmidt [Mon, 21 Oct 2019 04:15:07 +0000 (15:15 +1100)]
Add option to not flatten hierarchy
Vivado by default tries to flatten the module hierarchy to improve
placement and timing. However this makes debugging timing issues
really hard as the net names in the timing report can be pretty
bogus.
This adds a generic that can be used to control attributes to stop
vivado from flattening the main core components. The resulting design
will have worst timing overall but it will be easier to understand
what the worst timing path are and address them.
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Benjamin Herrenschmidt [Mon, 21 Oct 2019 04:11:47 +0000 (15:11 +1100)]
writeback: Slightly improve timing
The CR update currently depends on the complete data formatting
mux chain. This makes it source its inputs from a bit earlier in
the chian, thus improving timing a bit
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Benjamin Herrenschmidt [Fri, 18 Oct 2019 23:34:48 +0000 (10:34 +1100)]
simple_ram: Turn on pipelining
With a 1 cycle delay
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Benjamin Herrenschmidt [Fri, 18 Oct 2019 23:33:31 +0000 (10:33 +1100)]
wb_debug: Add wishbone pipelining support
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Benjamin Herrenschmidt [Fri, 18 Oct 2019 23:33:04 +0000 (10:33 +1100)]
icache: Add wishbone pipelining support
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Benjamin Herrenschmidt [Fri, 18 Oct 2019 23:32:46 +0000 (10:32 +1100)]
dcache: Add wishbone pipelining support
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Benjamin Herrenschmidt [Sat, 19 Oct 2019 10:22:33 +0000 (21:22 +1100)]
fpga/bram: Generate stall signal
This doesn't yet pipeline the block RAM, just generate a valid stall
signal so it's compatible with a pipelined master
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Benjamin Herrenschmidt [Fri, 18 Oct 2019 23:30:39 +0000 (10:30 +1100)]
simple_ram: Add pipelining support
The generic PIPELINE_DEPTH can be set to 0 to keep it operating
as a non-pipelined slave, or a larger value indicating
the amount of extra cycles between requests and acks.
It will always generate a valid stall signal, so it can be used
in either mode with a pipelined master (but only in non-pipelined
mode with a non-pipelined master).
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Benjamin Herrenschmidt [Fri, 18 Oct 2019 23:27:56 +0000 (10:27 +1100)]
intercon: Generate stall signals for non-pipelined slaves
So far the UART and the "miss" case. Memory will be
pipelined
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Benjamin Herrenschmidt [Fri, 18 Oct 2019 23:27:02 +0000 (10:27 +1100)]
wb_arbiter: Forward stall signals
They are set to '1' for non-selected devices
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Benjamin Herrenschmidt [Fri, 18 Oct 2019 23:26:09 +0000 (10:26 +1100)]
icache_tb: Initialize stop_mark
Too much red in gtkwave..
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Benjamin Herrenschmidt [Thu, 17 Oct 2019 09:07:18 +0000 (20:07 +1100)]
wishbone: Add stall signal
Pipelined wishbone needs it
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Benjamin Herrenschmidt [Fri, 18 Oct 2019 22:21:42 +0000 (09:21 +1100)]
pp_uart: reformat
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Anton Blanchard [Fri, 25 Oct 2019 06:10:01 +0000 (17:10 +1100)]
Merge pull request #115 from antonblanchard/reduce-wishbone
Reduce wishbone
Anton Blanchard [Fri, 25 Oct 2019 04:52:24 +0000 (15:52 +1100)]
Merge pull request #113 from mikey/exec-sim-remove
Remove SIM generic from execute1
Anton Blanchard [Fri, 25 Oct 2019 04:49:33 +0000 (15:49 +1100)]
Merge pull request #114 from antonblanchard/dcache
Dcache from Ben
Michael Neuling [Thu, 24 Oct 2019 06:07:58 +0000 (17:07 +1100)]
Remove SIM generic from execute1
This does nothing, so remove.
Signed-off-by: Michael Neuling <mikey@neuling.org>