yosys.git
4 years agocxxrtl: add missing extern "C".
whitequark [Thu, 9 Jul 2020 17:52:52 +0000 (17:52 +0000)]
cxxrtl: add missing extern "C".

This bug was hidden if a header was generated.

4 years agoxilinx: Use dfflegalize.
Marcelina Kościelnicka [Tue, 23 Jun 2020 16:51:51 +0000 (18:51 +0200)]
xilinx: Use dfflegalize.

4 years agodfflibmap: Refactor to use dfflegalize internally.
Marcelina Kościelnicka [Thu, 2 Jul 2020 16:22:43 +0000 (18:22 +0200)]
dfflibmap: Refactor to use dfflegalize internally.

4 years agoFix issue #2251 (#2252)
Lucas Castro [Thu, 9 Jul 2020 16:50:26 +0000 (13:50 -0300)]
Fix issue #2251 (#2252)

* Fix #2251 - YosysJS ReferenceError: _memset is not defined.
Add '_memset' in emcc EXPORTED_FUNCTIONS in Makefile.

4 years agoclkbufmap: improve input pad handling.
Marcelina Kościelnicka [Sat, 4 Jul 2020 21:09:00 +0000 (23:09 +0200)]
clkbufmap: improve input pad handling.

- allow inserting only the input pad cell
- do not insert the usual buffer if the input pad already acts as a
  buffer

4 years agoMerge pull request #2244 from antmicro/logic
clairexen [Thu, 9 Jul 2020 16:39:30 +0000 (18:39 +0200)]
Merge pull request #2244 from antmicro/logic

Add logic type support to parameters

4 years agoclk2fflogic: Consistently treat async control signals as negative hold.
Marcelina Kościelnicka [Tue, 7 Jul 2020 12:22:04 +0000 (14:22 +0200)]
clk2fflogic: Consistently treat async control signals as negative hold.

This fixes some dfflegalize equivalence checks, and breaks others — and
I strongly suspect the others are due to bad support for multiple
async inputs in `proc` (in particular, lack of proper support for
dlatchsr and sketchy circuits on dffsr control inputs).

4 years agodfflegalize: Add special support for const-D latches.
Marcelina Kościelnicka [Mon, 6 Jul 2020 20:52:05 +0000 (22:52 +0200)]
dfflegalize: Add special support for const-D latches.

Those can be created by `opt_dff` when optimizing `$adff` with const
clock, or with D == Q.  Make dfflegalize do the opposite transform
when such dlatches would be otherwise unimplementable.

4 years agoMerge pull request #2246 from YosysHQ/mwk/dfflegalize-typo
whitequark [Tue, 7 Jul 2020 22:46:37 +0000 (22:46 +0000)]
Merge pull request #2246 from YosysHQ/mwk/dfflegalize-typo

dfflegalize: typo fix

4 years agodfflegalize: typo fix
Marcelina Kościelnicka [Tue, 7 Jul 2020 13:00:52 +0000 (15:00 +0200)]
dfflegalize: typo fix

4 years agoefinix: Use dfflegalize.
Marcelina Kościelnicka [Thu, 2 Jul 2020 22:23:32 +0000 (00:23 +0200)]
efinix: Use dfflegalize.

4 years agogowin: Use dfflegalize.
Marcelina Kościelnicka [Thu, 2 Jul 2020 22:23:18 +0000 (00:23 +0200)]
gowin: Use dfflegalize.

4 years agoAdd logic param and integer bad syntax tests
Kamil Rakoczy [Mon, 6 Jul 2020 07:05:34 +0000 (09:05 +0200)]
Add logic param and integer bad syntax tests

Signed-off-by: Kamil Rakoczy <krakoczy@antmicro.com>
4 years agoSupport logic typed parameters
Lukasz Dalek [Mon, 18 May 2020 19:02:19 +0000 (21:02 +0200)]
Support logic typed parameters

Signed-off-by: Lukasz Dalek <ldalek@antmicro.com>
4 years agointel_alm: direct M10K instantiation
Dan Ravensloft [Thu, 11 Jun 2020 21:25:04 +0000 (22:25 +0100)]
intel_alm: direct M10K instantiation

4 years agoNaming fixes.
Marcelina Kościelnicka [Sun, 5 Jul 2020 20:21:59 +0000 (22:21 +0200)]
Naming fixes.

4 years agosynth_gowin: ABC9 support
Dan Ravensloft [Wed, 1 Apr 2020 00:07:30 +0000 (01:07 +0100)]
synth_gowin: ABC9 support

This adds ABC9 support for synth_gowin; drastically improving
synthesis quality.

4 years agointel_alm: add Cyclone 10 GX tests
Dan Ravensloft [Sun, 5 Jul 2020 17:53:14 +0000 (18:53 +0100)]
intel_alm: add Cyclone 10 GX tests

4 years agoMerge pull request #2236 from YosysHQ/mwk/dfflegalize-ice40
Marcelina Kościelnicka [Sun, 5 Jul 2020 16:50:25 +0000 (18:50 +0200)]
Merge pull request #2236 from YosysHQ/mwk/dfflegalize-ice40

ice40: Use dfflegalize.

4 years agoecp5: Use dfflegalize.
Marcelina Kościelnicka [Thu, 2 Jul 2020 22:23:03 +0000 (00:23 +0200)]
ecp5: Use dfflegalize.

4 years agoMerge pull request #2227 from Ravenslofty/ccache
whitequark [Sun, 5 Jul 2020 15:53:41 +0000 (15:53 +0000)]
Merge pull request #2227 from Ravenslofty/ccache

Add option to use ccache when building

4 years agoMerge pull request #2232 from YosysHQ/mwk/gowin-sim-init
Marcelina Kościelnicka [Sun, 5 Jul 2020 10:02:31 +0000 (12:02 +0200)]
Merge pull request #2232 from YosysHQ/mwk/gowin-sim-init

gowin: Fix INIT values in sim library.

4 years agodfflegalize: Prefer mapping dff to sdff before adff
Marcelina Kościelnicka [Sun, 5 Jul 2020 02:57:24 +0000 (04:57 +0200)]
dfflegalize: Prefer mapping dff to sdff before adff

This ensures that, when both sync and async FFs are available and abc9
is involved, the sync FFs will be used, and will thus remain available
for sequential synthesis.

4 years agoopt_expr: Fix crash on $mul optimization with more zeros removed than Y has.
Marcelina Kościelnicka [Sat, 4 Jul 2020 22:55:38 +0000 (00:55 +0200)]
opt_expr: Fix crash on $mul optimization with more zeros removed than Y has.

Fixes #2221.

4 years agointel_alm: DSP inference
Dan Ravensloft [Sat, 25 Apr 2020 16:25:59 +0000 (17:25 +0100)]
intel_alm: DSP inference

4 years agoice40: Use dfflegalize.
Marcelina Kościelnicka [Thu, 2 Jul 2020 22:21:24 +0000 (00:21 +0200)]
ice40: Use dfflegalize.

4 years agogowin: Fix INIT values in sim library.
Marcelina Kościelnicka [Sun, 5 Jul 2020 01:03:48 +0000 (03:03 +0200)]
gowin: Fix INIT values in sim library.

4 years agogowin: replace determine_init with setundef
Dan Ravensloft [Sat, 4 Jul 2020 18:39:40 +0000 (19:39 +0100)]
gowin: replace determine_init with setundef

4 years agosynth_intel_alm: Use dfflegalize.
Marcelina Kościelnicka [Wed, 1 Jul 2020 01:31:34 +0000 (03:31 +0200)]
synth_intel_alm: Use dfflegalize.

4 years agoAdd option to use ccache when building
Dan Ravensloft [Sat, 4 Jul 2020 18:59:39 +0000 (19:59 +0100)]
Add option to use ccache when building

4 years agoImprove MISTRAL_FF specify rules
Dan Ravensloft [Thu, 28 May 2020 10:33:19 +0000 (11:33 +0100)]
Improve MISTRAL_FF specify rules

Co-authored-by: Eddie Hung <eddie@fpgeh.com>
4 years agotests: update fsm.ys resource count
Eddie Hung [Wed, 27 May 2020 19:49:16 +0000 (12:49 -0700)]
tests: update fsm.ys resource count

Suspect it is to do with map/set ordering in techmap; should
be fixed by #1862?

4 years agoabc9: only techmap (* abc9_flop *) modules
Eddie Hung [Wed, 27 May 2020 16:37:57 +0000 (09:37 -0700)]
abc9: only techmap (* abc9_flop *) modules

4 years agointel_alm: compose $__MISTRAL_FF_SYNCONLY from MISTRAL_FF
Eddie Hung [Tue, 26 May 2020 15:38:11 +0000 (08:38 -0700)]
intel_alm: compose $__MISTRAL_FF_SYNCONLY from MISTRAL_FF

4 years agoabc9: techmap from user design to allow abc9_flop modules to be composed
Eddie Hung [Tue, 26 May 2020 15:37:26 +0000 (08:37 -0700)]
abc9: techmap from user design to allow abc9_flop modules to be composed

from other primitives

4 years agointel_alm: add $__ prefix to MISTRAL_FF_SYNCONLY
Eddie Hung [Mon, 25 May 2020 22:15:20 +0000 (15:15 -0700)]
intel_alm: add $__ prefix to MISTRAL_FF_SYNCONLY

4 years agointel_alm: ABC9 sequential optimisations
Dan Ravensloft [Sat, 23 May 2020 11:52:13 +0000 (12:52 +0100)]
intel_alm: ABC9 sequential optimisations

4 years agoAdd newlines to help text for dfflegalize
Rupert Swarbrick [Fri, 3 Jul 2020 10:12:03 +0000 (11:12 +0100)]
Add newlines to help text for dfflegalize

I think these were probably missed by accident. Spotted because GCC
spits out lots of messages like this:

passes/techmap/dfflegalize.cc:114:7: warning: zero-length gnu_printf format string [-Wformat-zero-length]
  114 |   log("");
      |       ^~

(because we tell GCC that the first argument to log() looks like a
printf control string in log.h, and a zero length such string triggers
a warning).

4 years agoMerge pull request #2132 from YosysHQ/eddie/verific_initial
clairexen [Thu, 2 Jul 2020 15:50:22 +0000 (17:50 +0200)]
Merge pull request #2132 from YosysHQ/eddie/verific_initial

verific: rewrite initial assume/asserts prior to elaboration

4 years agoMerge pull request #2208 from boqwxp/qbfsat-cleanup
clairexen [Thu, 2 Jul 2020 15:48:37 +0000 (17:48 +0200)]
Merge pull request #2208 from boqwxp/qbfsat-cleanup

qbfsat: Cleanup and refactoring

4 years agoMerge pull request #2186 from YosysHQ/mwk/dfflegalize
clairexen [Thu, 2 Jul 2020 15:46:11 +0000 (17:46 +0200)]
Merge pull request #2186 from YosysHQ/mwk/dfflegalize

Add dfflegalize pass.

4 years agoMerge pull request #2211 from YosysHQ/mwk/fix-fmcombine-ff
clairexen [Thu, 2 Jul 2020 15:43:48 +0000 (17:43 +0200)]
Merge pull request #2211 from YosysHQ/mwk/fix-fmcombine-ff

fmcombine: use the master ff cell type list

4 years agoMerge pull request #2210 from YosysHQ/mwk/fix-opt_merge
clairexen [Thu, 2 Jul 2020 15:43:34 +0000 (17:43 +0200)]
Merge pull request #2210 from YosysHQ/mwk/fix-opt_merge

opt_merge: use the master FF type list

4 years agoMerge pull request #2195 from YosysHQ/mwk/manual-gates
clairexen [Thu, 2 Jul 2020 15:43:10 +0000 (17:43 +0200)]
Merge pull request #2195 from YosysHQ/mwk/manual-gates

Add a few more gate types to the manual.

4 years agoqbfsat: Remove useless comment and #ifndef guards.
Alberto Gonzalez [Tue, 30 Jun 2020 07:00:14 +0000 (07:00 +0000)]
qbfsat: Remove useless comment and #ifndef guards.

4 years agoqbfsat: Specify default values for some options in the help message.
Alberto Gonzalez [Tue, 30 Jun 2020 06:57:45 +0000 (06:57 +0000)]
qbfsat: Specify default values for some options in the help message.

4 years agoqbfsat: Clean up external executable command lines and update temporary directory...
Alberto Gonzalez [Mon, 29 Jun 2020 23:01:56 +0000 (23:01 +0000)]
qbfsat: Clean up external executable command lines and update temporary directory name.

4 years agoqbfsat: Clean up and refactor data structures into `qbfsat.h`.
Alberto Gonzalez [Mon, 29 Jun 2020 22:06:43 +0000 (22:06 +0000)]
qbfsat: Clean up and refactor data structures into `qbfsat.h`.

4 years agoMerge pull request #2203 from antmicro/fix-grammar
clairexen [Wed, 1 Jul 2020 14:41:32 +0000 (16:41 +0200)]
Merge pull request #2203 from antmicro/fix-grammar

Signed and macro grammar update

4 years agoMerge pull request #2179 from splhack/static-cast
clairexen [Wed, 1 Jul 2020 14:40:20 +0000 (16:40 +0200)]
Merge pull request #2179 from splhack/static-cast

Support SystemVerilog Static Cast

4 years agoMerge pull request #2138 from boqwxp/qbfsat-oflag
clairexen [Wed, 1 Jul 2020 14:35:27 +0000 (16:35 +0200)]
Merge pull request #2138 from boqwxp/qbfsat-oflag

qbfsat: Add `-O[012]` options to control pre-solving simplification with ABC

4 years agoMerge pull request #2206 from boqwxp/qbfsat-fix-name-specialization
clairexen [Wed, 1 Jul 2020 14:34:32 +0000 (16:34 +0200)]
Merge pull request #2206 from boqwxp/qbfsat-fix-name-specialization

qbfsat: Fix name-based hole specialization

4 years agodfflegalize: Add tests.
Marcelina Kościelnicka [Tue, 30 Jun 2020 13:30:59 +0000 (15:30 +0200)]
dfflegalize: Add tests.

4 years agoAdd dfflegalize pass.
Marcelina Kościelnicka [Tue, 23 Jun 2020 12:36:34 +0000 (14:36 +0200)]
Add dfflegalize pass.

4 years agofmcombine: use the master ff cell type list
Marcelina Kościelnicka [Tue, 30 Jun 2020 19:07:17 +0000 (21:07 +0200)]
fmcombine: use the master ff cell type list

4 years agoopt_merge: use the master FF type list
Marcelina Kościelnicka [Tue, 30 Jun 2020 18:57:35 +0000 (20:57 +0200)]
opt_merge: use the master FF type list

4 years agoMerge pull request #2136 from zachjs/master
clairexen [Tue, 30 Jun 2020 15:38:49 +0000 (17:38 +0200)]
Merge pull request #2136 from zachjs/master

Allow constant function calls in for loops and generate if and case

4 years agoMerge pull request #2199 from YosysHQ/mmicko/sim_memory
clairexen [Tue, 30 Jun 2020 15:12:51 +0000 (17:12 +0200)]
Merge pull request #2199 from YosysHQ/mmicko/sim_memory

sim - error when memrd and memwr detected

4 years agoMerge pull request #2201 from YosysHQ/fix_test_cell_ilang
clairexen [Tue, 30 Jun 2020 15:11:13 +0000 (17:11 +0200)]
Merge pull request #2201 from YosysHQ/fix_test_cell_ilang

Use ID macro to fix assertion

4 years agoMerge pull request #2209 from YosysHQ/verific_update
clairexen [Tue, 30 Jun 2020 15:05:51 +0000 (17:05 +0200)]
Merge pull request #2209 from YosysHQ/verific_update

Update verific API version check

4 years agosimcells: Fix reset polarity for $_DLATCH_???_ cells.
Marcelina Kościelnicka [Tue, 30 Jun 2020 13:31:12 +0000 (15:31 +0200)]
simcells: Fix reset polarity for $_DLATCH_???_ cells.

4 years agoUpdate verific API version check
Miodrag Milanovic [Tue, 30 Jun 2020 10:13:13 +0000 (12:13 +0200)]
Update verific API version check

4 years agoqbfsat: Add `-O[012]` options to control pre-solving simplification with ABC.
Alberto Gonzalez [Tue, 30 Jun 2020 05:47:03 +0000 (05:47 +0000)]
qbfsat: Add `-O[012]` options to control pre-solving simplification with ABC.

Thanks to @mwk for the gate mapping part of the ABC scripts.

Co-Authored-By: Marcelina Kościelnicka <mwk@0x04.net>
4 years agoqbfsat: Fix name-based hole specialization.
Alberto Gonzalez [Tue, 30 Jun 2020 01:53:21 +0000 (01:53 +0000)]
qbfsat: Fix name-based hole specialization.

Look for unique connections in the containing module with the $anyconst port Y SigBit on the RHS and use those. If no such connection is found, fall back to using the name of the $anyconst port Y SigBit.

4 years agoMerge pull request #2205 from whitequark/fix-2204
whitequark [Tue, 30 Jun 2020 00:08:08 +0000 (00:08 +0000)]
Merge pull request #2205 from whitequark/fix-2204

techmap: don't drop attributes on replaced cells

4 years agotechmap: don't drop attributes on replaced cells.
whitequark [Mon, 29 Jun 2020 23:14:13 +0000 (23:14 +0000)]
techmap: don't drop attributes on replaced cells.

This was introduced in 76c4ee4ea5cb6a3dc214f66237af22a1bedda010.

Fixes #2204.

4 years agoAllow constant function calls in for loops and generate if and case
Zachary Snow [Sat, 27 Jun 2020 02:52:36 +0000 (19:52 -0700)]
Allow constant function calls in for loops and generate if and case

4 years agoMerge pull request #2200 from YosysHQ/mmicko/fix_expose
Miodrag Milanović [Mon, 29 Jun 2020 13:16:29 +0000 (15:16 +0200)]
Merge pull request #2200 from YosysHQ/mmicko/fix_expose

expose pass fix

4 years agoGive error that options are exclusive
Miodrag Milanovic [Mon, 29 Jun 2020 12:45:49 +0000 (14:45 +0200)]
Give error that options are exclusive

4 years agocleanup
Miodrag Milanovic [Mon, 29 Jun 2020 12:42:48 +0000 (14:42 +0200)]
cleanup

4 years agoMerge pull request #2197 from Xiretza/test_cell-shifts
whitequark [Mon, 29 Jun 2020 12:34:09 +0000 (12:34 +0000)]
Merge pull request #2197 from Xiretza/test_cell-shifts

test_cell: don't generate directional shifts with \B_SIGNED=1

4 years agoUse ID macro to fix assertion
Miodrag Milanovic [Mon, 29 Jun 2020 11:18:13 +0000 (13:18 +0200)]
Use ID macro to fix assertion

4 years agoexpose pass fix
Miodrag Milanovic [Mon, 29 Jun 2020 09:56:43 +0000 (11:56 +0200)]
expose pass fix

4 years agosim - error when memrd and memwr detected
Miodrag Milanovic [Mon, 29 Jun 2020 08:33:39 +0000 (10:33 +0200)]
sim - error when memrd and memwr detected

4 years agotest_cell: don't generate directional shifts with \B_SIGNED=1
Xiretza [Sun, 28 Jun 2020 19:30:16 +0000 (21:30 +0200)]
test_cell: don't generate directional shifts with \B_SIGNED=1

This was made an explicit error in e97e33d, "kernel: require \B_SIGNED=0
on $shl, $sshl, $shr, $sshr.".

4 years agoAdd latches to the manual.
Marcelina Kościelnicka [Fri, 26 Jun 2020 18:57:39 +0000 (20:57 +0200)]
Add latches to the manual.

4 years agoAdd a few more gate types to the manual.
Marcelina Kościelnicka [Fri, 26 Jun 2020 15:16:00 +0000 (17:16 +0200)]
Add a few more gate types to the manual.

4 years agoFix crash in verific frontend
Miodrag Milanovic [Fri, 26 Jun 2020 18:11:01 +0000 (20:11 +0200)]
Fix crash in verific frontend

4 years agoAdd signed/unsigned tests
Kamil Rakoczy [Fri, 26 Jun 2020 13:35:35 +0000 (15:35 +0200)]
Add signed/unsigned tests

Signed-off-by: Kamil Rakoczy <krakoczy@antmicro.com>
4 years agoParse macro call attached semicolon as empty expression
Lukasz Dalek [Mon, 1 Jun 2020 13:25:24 +0000 (15:25 +0200)]
Parse macro call attached semicolon as empty expression

Signed-off-by: Lukasz Dalek <ldalek@antmicro.com>
4 years agoFix integer signing grammar
Lukasz Dalek [Mon, 18 May 2020 19:01:16 +0000 (21:01 +0200)]
Fix integer signing grammar

This commit fixes signed/unsigned grammar in parameters as defined in SV
LRM A2.2.1. Example of correct parameters:

parameter integer signed i = 0;
parameter integer unsigned i = 0;

Example of incorrect parameters:

parameter signed integer i = 0;
parameter unsigned integer i = 0;

Signed-off-by: Lukasz Dalek <ldalek@antmicro.com>
Signed-off-by: Kamil Rakoczy <krakoczy@antmicro.com>
4 years agoMerge pull request #2193 from whitequark/cxxrtl-help-text
whitequark [Fri, 26 Jun 2020 08:48:15 +0000 (08:48 +0000)]
Merge pull request #2193 from whitequark/cxxrtl-help-text

cxxrtl: update help text

4 years agocxxrtl: update help text.
whitequark [Fri, 26 Jun 2020 08:30:44 +0000 (08:30 +0000)]
cxxrtl: update help text.

4 years agoMerge pull request #2188 from antmicro/missing-operators
whitequark [Fri, 26 Jun 2020 07:30:27 +0000 (07:30 +0000)]
Merge pull request #2188 from antmicro/missing-operators

Add logic-assignments operators

4 years agoMerge pull request #2189 from antmicro/optional-labels
whitequark [Fri, 26 Jun 2020 07:29:24 +0000 (07:29 +0000)]
Merge pull request #2189 from antmicro/optional-labels

Add support for optional labels

4 years agoMerge pull request #2168 from whitequark/assert-unused-exprs
clairexen [Thu, 25 Jun 2020 16:21:51 +0000 (18:21 +0200)]
Merge pull request #2168 from whitequark/assert-unused-exprs

Use (and ignore) the expression provided to log_assert in NDEBUG builds

4 years agoMerge pull request #2135 from boqwxp/qbfsat-timeinfo
clairexen [Thu, 25 Jun 2020 16:18:09 +0000 (18:18 +0200)]
Merge pull request #2135 from boqwxp/qbfsat-timeinfo

log and qbfsat: Also include child process usage in `PerformanceTimer::query()` and report the time for each call to the QBF-SAT solver

4 years agoMerge pull request #2093 from boqwxp/qbfsat-bugfixes
clairexen [Thu, 25 Jun 2020 16:14:17 +0000 (18:14 +0200)]
Merge pull request #2093 from boqwxp/qbfsat-bugfixes

qbfsat: Multiple bugfixes

4 years agoMerge pull request #2192 from YosysHQ/verific_netbus_attr
clairexen [Thu, 25 Jun 2020 14:40:30 +0000 (16:40 +0200)]
Merge pull request #2192 from YosysHQ/verific_netbus_attr

verific - import attributes for net buses

4 years agoAdd sub-assign and and-assign tests
Kamil Rakoczy [Thu, 25 Jun 2020 12:20:47 +0000 (14:20 +0200)]
Add sub-assign and and-assign tests

Signed-off-by: Kamil Rakoczy <krakoczy@antmicro.com>
4 years agoMove combined assign tests to single file
Kamil Rakoczy [Thu, 25 Jun 2020 12:17:41 +0000 (14:17 +0200)]
Move combined assign tests to single file

Signed-off-by: Kamil Rakoczy <krakoczy@antmicro.com>
4 years agoSupport missing sub-assign and and-assign operators
Kamil Rakoczy [Thu, 25 Jun 2020 11:29:06 +0000 (13:29 +0200)]
Support missing sub-assign and and-assign operators

Signed-off-by: Kamil Rakoczy <krakoczy@antmicro.com>
4 years agooptimization, all items should have same attributes
Miodrag Milanovic [Thu, 25 Jun 2020 07:18:53 +0000 (09:18 +0200)]
optimization, all items should have same attributes

4 years agoAdd xor-assignment test
Kamil Rakoczy [Wed, 24 Jun 2020 12:38:03 +0000 (14:38 +0200)]
Add xor-assignment test

Signed-off-by: Kamil Rakoczy <krakoczy@antmicro.com>
4 years agoSupport missing xor-assign operator
Lukasz Dalek [Tue, 23 Jun 2020 16:50:50 +0000 (18:50 +0200)]
Support missing xor-assign operator

Signed-off-by: Lukasz Dalek <ldalek@antmicro.com>
4 years agoSupport optional labels at the end of package definition
Lukasz Dalek [Fri, 19 Jun 2020 18:46:38 +0000 (20:46 +0200)]
Support optional labels at the end of package definition

Signed-off-by: Lukasz Dalek <ldalek@antmicro.com>
4 years agoSupport optional labels at the end of module definition
Lukasz Dalek [Tue, 19 May 2020 14:58:48 +0000 (16:58 +0200)]
Support optional labels at the end of module definition

Signed-off-by: Lukasz Dalek <ldalek@antmicro.com>
4 years agoAdd or-assignment and plus-assignment tests
Kamil Rakoczy [Wed, 24 Jun 2020 09:45:38 +0000 (11:45 +0200)]
Add or-assignment and plus-assignment tests

Signed-off-by: Kamil Rakoczy <krakoczy@antmicro.com>
4 years agoAdd plus-assignment operator
Kamil Rakoczy [Wed, 3 Jun 2020 14:44:02 +0000 (16:44 +0200)]
Add plus-assignment operator

Signed-off-by: Kamil Rakoczy <krakoczy@antmicro.com>
4 years agoAdd or-assignment operator
Kamil Rakoczy [Wed, 3 Jun 2020 11:51:57 +0000 (13:51 +0200)]
Add or-assignment operator

Signed-off-by: Kamil Rakoczy <krakoczy@antmicro.com>