Add iteration limit to "opt_muxtree"

Signed-off-by: Clifford Wolf <clifford@clifford.at>

Update ABC to git rev 2ddc57d

Signed-off-by: Clifford Wolf <clifford@clifford.at>

Add "write_aiger -I -O -B"

Signed-off-by: Clifford Wolf <clifford@clifford.at>

Merge branch 'master' of github.com:YosysHQ/yosys

Merge pull request #697 from eddiehung/xilinx_ps7

Add support for PS7 block for Xilinx

Merge pull request #695 from daveshah1/ecp5_bb

ecp5: Adding some blackbox cells

Update ABC to git rev 68da3cf

Signed-off-by: Clifford Wolf <clifford@clifford.at>

Add support for Xilinx PS7 block

Set Verific flag vhdl_support_variable_slice=1

Signed-off-by: Clifford Wolf <clifford@clifford.at>

ecp5: Add 'fake' DCU parameters

Signed-off-by: David Shah <dave@ds0.me>

ecp5: Add blackboxes for ancillary DCU cells

Signed-off-by: David Shah <dave@ds0.me>

Merge pull request #696 from arjenroodselaar/verific_darwin

Use appropriate static libraries when building with Verific on MacOS

Fix "make ystests" to use correct Yosys binary

Signed-off-by: Clifford Wolf <clifford@clifford.at>

Use appropriate static libraries when building with Verific on MacOS

Merge pull request #693 from YosysHQ/rlimit

improve rlimit handling in smtio.py

ecp5: Adding some blackbox cells

Signed-off-by: David Shah <dave@ds0.me>

Limit stack size to 16 MB on Darwin

Signed-off-by: Clifford Wolf <clifford@clifford.at>

Merge pull request #694 from trcwm/dffmap_expr_fix

DFFLIBMAP: changed 'missing pin' error into a warning.

DFFLIBMAP: changed 'missing pin' error into a warning with additional reason/info.

Run solver in non-incremental mode whem smtio.py is configured for non-incremental solving

Signed-off-by: Clifford Wolf <clifford@clifford.at>

Update ABC rev to 4d56acf

Signed-off-by: Clifford Wolf <clifford@clifford.at>

Fix for improved smtio.py rlimit code

Signed-off-by: Clifford Wolf <clifford@clifford.at>

Improve stack rlimit code in smtio.py

Signed-off-by: Clifford Wolf <clifford@clifford.at>

Allow square brackets in liberty identifiers

Signed-off-by: Clifford Wolf <clifford@clifford.at>

Merge pull request #691 from arjenroodselaar/stacksize

Use conservative stack size for SMT2 on MacOS

Use conservative stack size for SMT2 on MacOS

Add warning for SV "restrict" without "property"

Signed-off-by: Clifford Wolf <clifford@clifford.at>

Add proper error message for when smtbmc "append" fails

Signed-off-by: Clifford Wolf <clifford@clifford.at>

Various indenting fixes in AST front-end (mostly space vs tab issues)

Signed-off-by: Clifford Wolf <clifford@clifford.at>

Merge pull request #687 from trcwm/master

Liberty file: error when it contains pin references to non-existing pins

Merge pull request #688 from ZipCPU/rosenfell

Make rose and fell dependent upon LSB only

Make  and  dependent upon LSB only

Liberty file newline handling is more relaxed. More descriptive error message

Report an error when a liberty file contains pin references that reference non-existing pins

Do not generate "reg assigned in a continuous assignment" warnings for "rand reg"

Signed-off-by: Clifford Wolf <clifford@clifford.at>

Add support for signed $shift/$shiftx in smt2 back-end

Signed-off-by: Clifford Wolf <clifford@clifford.at>

Merge branch 'igloo2'

Fix sf2 LUT interface

Signed-off-by: Clifford Wolf <clifford@clifford.at>

Basic SmartFusion2 and IGLOO2 synthesis support

Signed-off-by: Clifford Wolf <clifford@clifford.at>

Merge pull request #680 from jburgess777/fix-empty-string-back-assert

Avoid assert when label is an empty string

Avoid assert when label is an empty string

Calling back() on an empty string is not allowed and triggers
an assert with recent gcc:

$ cd manual/PRESENTATION_Intro
$ ../../yosys counter.ys
...
/usr/include/c++/8/bits/basic_string.h:1136: std::__cxx11::basic_string<_CharT, _Traits, _Alloc>::reference std::__cxx11::basic_string<_CharT, _Traits, _Alloc>::back() [with _CharT = char; _Traits = std::char_traits<char>; _Alloc = std::allocator<char>; std::__cxx11::basic_string<_CharT, _Traits, _Alloc>::reference = char&]: Assertion '!empty()' failed.

802             if (label.back() == ':' && GetSize(label) > 1)
(gdb) p label
$1 = ""

Merge pull request #678 from whentze/master

Fix unhandled std::out_of_range in run_frontend() due to integer underflow

Fix minor typo in error message

Signed-off-by: Clifford Wolf <clifford@clifford.at>

Merge pull request #679 from udif/pr_syntax_error

More meaningful SystemVerilog/Verilog parser error messages

Rename the generic "Syntax error" message from the Verilog/SystemVerilog parser into unique,
meaningful info on the error.
Also add 13 compilation examples that triggers each of these messages.

Merge pull request #677 from daveshah1/ecp5_dsp

ecp5: Add blackboxes for MULT18X18D and ALU54B

fix unhandled std::out_of_range when calling yosys with 3-character argument

ecp5: Remove DSP parameters that don't work

Signed-off-by: David Shah <davey1576@gmail.com>

ecp5: Add DSP blackboxes

Signed-off-by: David Shah <davey1576@gmail.com>

Improve read_verilog range out of bounds warning

Signed-off-by: Clifford Wolf <clifford@clifford.at>

Merge pull request #674 from rubund/feature/svinterface_at_top

Support for SystemVerilog interfaces as ports in the top level module + test case

Refactor code to avoid code duplication + added comments

Support for SystemVerilog interfaces as a port in the top level module + test case

Fixed memory leak

Merge pull request #673 from daveshah1/ecp5_improve

Small ECP5 improvements

ecp5: Sim model fixes

Signed-off-by: David Shah <dave@ds0.me>

ecp5: Add latch inference

Signed-off-by: David Shah <dave@ds0.me>

Merge pull request #672 from daveshah1/fix_bram

memory_bram: Reset make_outreg when growing read ports

memory_bram: Reset make_outreg when growing read ports

Signed-off-by: David Shah <dave@ds0.me>

Merge pull request #671 from rafaeltp/master

adding offset info to memories on verilog output

Merge pull request #670 from rubund/feature/basic_svinterface_test

Basic test for checking correct synthesis of SystemVerilog interfaces

adding offset info to memories

adding offset info to memories

Basic test for checking correct synthesis of SystemVerilog interfaces

Update ABC to git rev 14d985a

Signed-off-by: Clifford Wolf <clifford@clifford.at>

Merge pull request #659 from rubund/sv_interfaces

Support for SystemVerilog interfaces and modports

Merge pull request #657 from mithro/xilinx-vpr

xilinx: Still map LUT7/LUT8 to Xilinx specific primitives when using `-vpr`

Merge pull request #664 from tklam/ignore-verilog-protect

Ignore protect endprotect

Update ABC to git rev c5b48bb

Signed-off-by: Clifford Wolf <clifford@clifford.at>

Minor code cleanups in liberty front-end

Signed-off-by: Clifford Wolf <clifford@clifford.at>

Merge pull request #660 from tklam/parse-liberty-detect-ff-latch

Handling ff/latch in liberty files

Merge pull request #663 from aman-goel/master

Update to .smv backend

Merge pull request #658 from daveshah1/ecp5_bram

ECP5 BRAM inference

Merge pull request #641 from tklam/master

Fix issue #639

Merge pull request #638 from udif/pr_reg_wire_error

Fix issue #630

We have 2018 now

Signed-off-by: Clifford Wolf <clifford@clifford.at>

After release is before release

Signed-off-by: Clifford Wolf <clifford@clifford.at>

Merge branch 'yosys-0.8-rc'

Yosys 0.8

Signed-off-by: Clifford Wolf <clifford@clifford.at>

ignore protect endprotect

Update command reference manual

Signed-off-by: Clifford Wolf <clifford@clifford.at>

ecp5: Disable LSR inversion

Signed-off-by: David Shah <dave@ds0.me>

Minor update

Handle FIXME for modport members without type directly in front

Documentation improvements etc.

- Mention new feature in the SystemVerilog section in the README file
- Commented changes much better
- Rename a few signals to make it clearer
- Prevent warning for unused signals in an easier way
- Add myself as copyright holder to 2 files
- Fix one potential memory leak (delete 'wire' if not in modport)

detect ff/latch before processing other nodes

stop check_signal_in_fanout from traversing FFs

stop check_signal_in_fanout from traversing FFs

Merge branch 'master' of https://github.com/YosysHQ/yosys

Fix build error with clang

Support for 'modports' for System Verilog interfaces

Synthesis support for SystemVerilog interfaces

This time doing the changes mostly in AST before RTLIL generation

BRAM improvements

Signed-off-by: David Shah <dave@ds0.me>

ecp5: Adding BRAM maps for all size options

Signed-off-by: David Shah <dave@ds0.me>

ecp5: First BRAM type maps successfully

Signed-off-by: David Shah <dave@ds0.me>

ecp5: Script for BRAM IO connections

Signed-off-by: David Shah <dave@ds0.me>

ecp5: Adding BRAM initialisation and config

Signed-off-by: David Shah <dave@ds0.me>

xilinx: Still map LUT7/LUT8 to Xilinx specific primitives.

Then if targeting vpr map all the Xilinx specific LUTs back into generic
Yosys LUTs.

Improve Verific importer blackbox handling

Signed-off-by: Clifford Wolf <clifford@clifford.at>

ecp5: Add blackbox for DP16KD

Signed-off-by: David Shah <dave@ds0.me>