Cole Poirier [Sat, 6 Jun 2020 00:03:34 +0000 (17:03 -0700)]
Re: [libre-riscv-dev] daily kan-ban update 05jun2020
bugzilla-daemon [Fri, 5 Jun 2020 23:46:06 +0000 (23:46 +0000)]
[libre-riscv-dev] [Bug 325] create POWER9 TRAP pipeline
bugzilla-daemon [Fri, 5 Jun 2020 23:25:24 +0000 (23:25 +0000)]
[libre-riscv-dev] [Bug 325] create POWER9 TRAP pipeline
Luke Kenneth Casson Leighton [Fri, 5 Jun 2020 22:03:50 +0000 (23:03 +0100)]
Re: [libre-riscv-dev] daily kan-ban update 05jun2020
bugzilla-daemon [Fri, 5 Jun 2020 22:02:15 +0000 (22:02 +0000)]
[libre-riscv-dev] [Bug 325] create POWER9 TRAP pipeline
bugzilla-daemon [Fri, 5 Jun 2020 21:59:51 +0000 (21:59 +0000)]
[libre-riscv-dev] [Bug 325] create POWER9 TRAP pipeline
Jacob Lifshay [Fri, 5 Jun 2020 21:57:04 +0000 (14:57 -0700)]
Re: [libre-riscv-dev] daily kan-ban update 05jun2020
bugzilla-daemon [Fri, 5 Jun 2020 20:12:58 +0000 (20:12 +0000)]
[libre-riscv-dev] [Bug 325] create POWER9 TRAP pipeline
bugzilla-daemon [Fri, 5 Jun 2020 19:49:44 +0000 (19:49 +0000)]
[libre-riscv-dev] [Bug 325] create POWER9 TRAP pipeline
bugzilla-daemon [Fri, 5 Jun 2020 19:47:12 +0000 (19:47 +0000)]
[libre-riscv-dev] [Bug 363] inconsistency between isel and mfcr and crand unit test on bit-ordering of CR
bugzilla-daemon [Fri, 5 Jun 2020 19:41:32 +0000 (19:41 +0000)]
[libre-riscv-dev] [Bug 363] inconsistency between isel and mfcr and crand unit test on bit-ordering of CR
bugzilla-daemon [Fri, 5 Jun 2020 19:40:37 +0000 (19:40 +0000)]
[libre-riscv-dev] [Bug 216] LOAD STORE buffer needed
bugzilla-daemon [Fri, 5 Jun 2020 19:17:04 +0000 (19:17 +0000)]
[libre-riscv-dev] [Bug 216] LOAD STORE buffer needed
bugzilla-daemon [Fri, 5 Jun 2020 19:15:22 +0000 (19:15 +0000)]
[libre-riscv-dev] [Bug 325] create POWER9 TRAP pipeline
bugzilla-daemon [Fri, 5 Jun 2020 19:08:03 +0000 (19:08 +0000)]
[libre-riscv-dev] [Bug 325] create POWER9 TRAP pipeline
Luke Kenneth Casson Leighton [Fri, 5 Jun 2020 18:53:06 +0000 (19:53 +0100)]
[libre-riscv-dev] daily kan-ban update 05jun2020
Jacob Lifshay [Fri, 5 Jun 2020 18:30:31 +0000 (11:30 -0700)]
Re: [libre-riscv-dev] NLNet018TV documentation
bugzilla-daemon [Fri, 5 Jun 2020 18:14:41 +0000 (18:14 +0000)]
[libre-riscv-dev] [Bug 325] create POWER9 TRAP pipeline
Luke Kenneth Casson Leighton [Fri, 5 Jun 2020 18:08:45 +0000 (19:08 +0100)]
Re: [libre-riscv-dev] NLNet018TV documentation
bugzilla-daemon [Fri, 5 Jun 2020 18:01:26 +0000 (18:01 +0000)]
[libre-riscv-dev] [Bug 55] IOpad Cell Library needed with industry-standard GPIO and DDR capability
bugzilla-daemon [Fri, 5 Jun 2020 17:59:28 +0000 (17:59 +0000)]
[libre-riscv-dev] [Bug 55] IOpad Cell Library needed with industry-standard GPIO and DDR capability
Staf Verhaegen [Fri, 5 Jun 2020 16:44:50 +0000 (18:44 +0200)]
[libre-riscv-dev] NLNet018TV documentation
bugzilla-daemon [Fri, 5 Jun 2020 16:14:11 +0000 (16:14 +0000)]
[libre-riscv-dev] [Bug 325] create POWER9 TRAP pipeline
Luke Kenneth Casson Leighton [Fri, 5 Jun 2020 15:51:11 +0000 (16:51 +0100)]
[libre-riscv-dev] tobias: note the comment here in bug #216
bugzilla-daemon [Fri, 5 Jun 2020 15:46:38 +0000 (15:46 +0000)]
[libre-riscv-dev] [Bug 325] create POWER9 TRAP pipeline
bugzilla-daemon [Fri, 5 Jun 2020 15:43:30 +0000 (15:43 +0000)]
[libre-riscv-dev] [Bug 325] create POWER9 TRAP pipeline
bugzilla-daemon [Fri, 5 Jun 2020 15:33:03 +0000 (15:33 +0000)]
[libre-riscv-dev] [Bug 325] create POWER9 TRAP pipeline
bugzilla-daemon [Fri, 5 Jun 2020 15:21:30 +0000 (15:21 +0000)]
[libre-riscv-dev] [Bug 325] create POWER9 TRAP pipeline
bugzilla-daemon [Fri, 5 Jun 2020 15:12:47 +0000 (15:12 +0000)]
[libre-riscv-dev] [Bug 325] create POWER9 TRAP pipeline
bugzilla-daemon [Fri, 5 Jun 2020 14:16:05 +0000 (14:16 +0000)]
[libre-riscv-dev] [Bug 325] create POWER9 TRAP pipeline
bugzilla-daemon [Fri, 5 Jun 2020 13:58:28 +0000 (13:58 +0000)]
[libre-riscv-dev] [Bug 363] inconsistency between isel and mfcr and crand unit test on bit-ordering of CR
bugzilla-daemon [Fri, 5 Jun 2020 13:39:32 +0000 (13:39 +0000)]
[libre-riscv-dev] [Bug 363] inconsistency between isel and mfcr and crand unit test on bit-ordering of CR
bugzilla-daemon [Fri, 5 Jun 2020 04:19:12 +0000 (04:19 +0000)]
[libre-riscv-dev] [Bug 325] create POWER9 TRAP pipeline
bugzilla-daemon [Fri, 5 Jun 2020 04:02:08 +0000 (04:02 +0000)]
[libre-riscv-dev] [Bug 348] POWER9 SPR pipeline needed
bugzilla-daemon [Fri, 5 Jun 2020 03:55:39 +0000 (03:55 +0000)]
[libre-riscv-dev] [Bug 363] inconsistency between isel and mfcr and crand unit test on bit-ordering of CR
bugzilla-daemon [Fri, 5 Jun 2020 03:55:06 +0000 (03:55 +0000)]
[libre-riscv-dev] [Bug 363] inconsistency between isel and mfcr and crand unit test on bit-ordering of CR
bugzilla-daemon [Fri, 5 Jun 2020 03:52:55 +0000 (03:52 +0000)]
[libre-riscv-dev] [Bug 325] create POWER9 TRAP pipeline
bugzilla-daemon [Fri, 5 Jun 2020 03:37:24 +0000 (03:37 +0000)]
[libre-riscv-dev] [Bug 325] create POWER9 TRAP pipeline
bugzilla-daemon [Fri, 5 Jun 2020 02:34:18 +0000 (02:34 +0000)]
[libre-riscv-dev] [Bug 325] create POWER9 TRAP pipeline
bugzilla-daemon [Fri, 5 Jun 2020 02:13:03 +0000 (02:13 +0000)]
[libre-riscv-dev] [Bug 325] create POWER9 TRAP pipeline
Jacob Lifshay [Fri, 5 Jun 2020 02:06:40 +0000 (19:06 -0700)]
Re: [libre-riscv-dev] publish crowdsupply update ourselves
Luke Kenneth Casson Leighton [Fri, 5 Jun 2020 01:54:20 +0000 (02:54 +0100)]
Re: [libre-riscv-dev] publish crowdsupply update ourselves
Yehowshua [Fri, 5 Jun 2020 01:43:57 +0000 (21:43 -0400)]
Re: [libre-riscv-dev] publish crowdsupply update ourselves
Jacob Lifshay [Fri, 5 Jun 2020 01:37:56 +0000 (18:37 -0700)]
[libre-riscv-dev] publish crowdsupply update ourselves
bugzilla-daemon [Fri, 5 Jun 2020 01:25:19 +0000 (01:25 +0000)]
[libre-riscv-dev] [Bug 325] create POWER9 TRAP pipeline
bugzilla-daemon [Fri, 5 Jun 2020 01:09:59 +0000 (01:09 +0000)]
[libre-riscv-dev] [Bug 325] create POWER9 TRAP pipeline
bugzilla-daemon [Fri, 5 Jun 2020 01:06:31 +0000 (01:06 +0000)]
[libre-riscv-dev] [Bug 325] create POWER9 TRAP pipeline
bugzilla-daemon [Fri, 5 Jun 2020 00:35:56 +0000 (00:35 +0000)]
[libre-riscv-dev] [Bug 325] create POWER9 TRAP pipeline
bugzilla-daemon [Fri, 5 Jun 2020 00:32:42 +0000 (00:32 +0000)]
[libre-riscv-dev] [Bug 325] create POWER9 TRAP pipeline
bugzilla-daemon [Thu, 4 Jun 2020 22:41:16 +0000 (22:41 +0000)]
[libre-riscv-dev] [Bug 325] create POWER9 TRAP pipeline
Cole Poirier [Thu, 4 Jun 2020 22:28:19 +0000 (15:28 -0700)]
Re: [libre-riscv-dev] daily kan-ban update 04jun2020
Cole Poirier [Thu, 4 Jun 2020 22:24:07 +0000 (15:24 -0700)]
Re: [libre-riscv-dev] daily kan-ban update 03jun2020
bugzilla-daemon [Thu, 4 Jun 2020 20:52:16 +0000 (20:52 +0000)]
[libre-riscv-dev] [Bug 363] inconsistency between isel and mfcr and crand unit test on bit-ordering of CR
Luke Kenneth Casson Leighton [Thu, 4 Jun 2020 20:25:28 +0000 (21:25 +0100)]
Re: [libre-riscv-dev] daily kan-ban update 04jun2020
Yehowshua [Thu, 4 Jun 2020 20:15:55 +0000 (16:15 -0400)]
Re: [libre-riscv-dev] daily kan-ban update 04jun2020
Yehowshua [Thu, 4 Jun 2020 20:15:37 +0000 (16:15 -0400)]
Re: [libre-riscv-dev] daily kan-ban update 04jun2020
bugzilla-daemon [Thu, 4 Jun 2020 19:55:15 +0000 (19:55 +0000)]
[libre-riscv-dev] [Bug 363] inconsistency between isel and mfcr unit test on bit-ordering of CR
bugzilla-daemon [Thu, 4 Jun 2020 19:51:11 +0000 (19:51 +0000)]
[libre-riscv-dev] [Bug 363] New: inconsistency between isel and mfcr unit test on bit-ordering of CR
Luke Kenneth Casson Leighton [Thu, 4 Jun 2020 19:02:46 +0000 (20:02 +0100)]
Re: [libre-riscv-dev] daily kan-ban update 04jun2020
Jacob Lifshay [Thu, 4 Jun 2020 18:55:57 +0000 (11:55 -0700)]
Re: [libre-riscv-dev] daily kan-ban update 04jun2020
Luke Kenneth Casson Leighton [Thu, 4 Jun 2020 16:51:12 +0000 (17:51 +0100)]
Re: [libre-riscv-dev] daily kan-ban update 04jun2020
bugzilla-daemon [Thu, 4 Jun 2020 16:49:19 +0000 (16:49 +0000)]
[libre-riscv-dev] [Bug 216] LOAD STORE buffer needed
Tobias Platen [Thu, 4 Jun 2020 15:00:08 +0000 (17:00 +0200)]
Re: [libre-riscv-dev] daily kan-ban update 04jun2020
bugzilla-daemon [Thu, 4 Jun 2020 13:42:52 +0000 (13:42 +0000)]
[libre-riscv-dev] [Bug 362] improvements to nmigen and yosys
bugzilla-daemon [Thu, 4 Jun 2020 13:41:12 +0000 (13:41 +0000)]
[libre-riscv-dev] [Bug 175] NLNet 2019 Wishbone proposal 2019-10-043
bugzilla-daemon [Thu, 4 Jun 2020 13:40:01 +0000 (13:40 +0000)]
[libre-riscv-dev] [Bug 362] New: improvements to nmigen and yosys
Luke Kenneth Casson Leighton [Thu, 4 Jun 2020 13:32:05 +0000 (14:32 +0100)]
Re: [libre-riscv-dev] daily kan-ban update 04jun2020
Luke Kenneth Casson Leighton [Thu, 4 Jun 2020 12:10:27 +0000 (13:10 +0100)]
[libre-riscv-dev] daily kan-ban update 04jun2020
Luke Kenneth Casson Leighton [Thu, 4 Jun 2020 11:02:14 +0000 (12:02 +0100)]
Re: [libre-riscv-dev] daily kan-ban update 03jun2020
Cole Poirier [Thu, 4 Jun 2020 03:46:03 +0000 (20:46 -0700)]
Re: [libre-riscv-dev] daily kan-ban update 03jun2020
Luke Kenneth Casson Leighton [Thu, 4 Jun 2020 01:37:55 +0000 (02:37 +0100)]
Re: [libre-riscv-dev] using a stage chain in a stage
Luke Kenneth Casson Leighton [Thu, 4 Jun 2020 01:32:09 +0000 (02:32 +0100)]
Re: [libre-riscv-dev] using a stage chain in a stage
Jacob Lifshay [Thu, 4 Jun 2020 01:30:02 +0000 (18:30 -0700)]
Re: [libre-riscv-dev] using a stage chain in a stage
Luke Kenneth Casson Leighton [Thu, 4 Jun 2020 01:20:18 +0000 (02:20 +0100)]
Re: [libre-riscv-dev] using a stage chain in a stage
Jacob Lifshay [Thu, 4 Jun 2020 00:58:27 +0000 (17:58 -0700)]
Re: [libre-riscv-dev] daily kan-ban update 03jun2020
Jacob Lifshay [Thu, 4 Jun 2020 00:52:57 +0000 (17:52 -0700)]
[libre-riscv-dev] using a stage chain in a stage
bugzilla-daemon [Thu, 4 Jun 2020 00:34:43 +0000 (00:34 +0000)]
[libre-riscv-dev] [Bug 325] create POWER9 TRAP pipeline
Luke Kenneth Casson Leighton [Thu, 4 Jun 2020 00:32:14 +0000 (01:32 +0100)]
Re: [libre-riscv-dev] daily kan-ban update 03jun2020
bugzilla-daemon [Thu, 4 Jun 2020 00:29:18 +0000 (00:29 +0000)]
[libre-riscv-dev] [Bug 325] create POWER9 TRAP pipeline
Cole Poirier [Thu, 4 Jun 2020 00:09:16 +0000 (17:09 -0700)]
Re: [libre-riscv-dev] daily kan-ban update 03jun2020
Luke Kenneth Casson Leighton [Thu, 4 Jun 2020 00:03:17 +0000 (01:03 +0100)]
Re: [libre-riscv-dev] daily kan-ban update 03jun2020
Cole Poirier [Wed, 3 Jun 2020 23:58:46 +0000 (16:58 -0700)]
Re: [libre-riscv-dev] daily kan-ban update 03jun2020
Luke Kenneth Casson Leighton [Wed, 3 Jun 2020 23:46:11 +0000 (00:46 +0100)]
Re: [libre-riscv-dev] Move FHDLTestCase to our utils folder
Yehowshua [Wed, 3 Jun 2020 23:38:14 +0000 (19:38 -0400)]
Re: [libre-riscv-dev] Move FHDLTestCase to our utils folder
Yehowshua [Wed, 3 Jun 2020 23:33:20 +0000 (19:33 -0400)]
[libre-riscv-dev] Move FHDLTestCase to our utils folder
bugzilla-daemon [Wed, 3 Jun 2020 22:18:28 +0000 (22:18 +0000)]
[libre-riscv-dev] [Bug 329] coriolis2 experiment layout for Dependency Matrices
bugzilla-daemon [Wed, 3 Jun 2020 22:00:49 +0000 (22:00 +0000)]
[libre-riscv-dev] [Bug 329] coriolis2 experiment layout for Dependency Matrices
Luke Kenneth Casson Leighton [Wed, 3 Jun 2020 19:21:58 +0000 (20:21 +0100)]
[libre-riscv-dev] regfile-to-function-unit connection taking shape
Tobias Platen [Wed, 3 Jun 2020 13:28:05 +0000 (15:28 +0200)]
Re: [libre-riscv-dev] daily kan-ban update 03jun2020
Luke Kenneth Casson Leighton [Wed, 3 Jun 2020 12:50:07 +0000 (13:50 +0100)]
[libre-riscv-dev] daily kan-ban update 03jun2020
bugzilla-daemon [Wed, 3 Jun 2020 12:00:03 +0000 (12:00 +0000)]
[libre-riscv-dev] [Bug 361] New: all test_pipe_caller.py needs RA=0 tests
Luke Kenneth Casson Leighton [Wed, 3 Jun 2020 10:08:12 +0000 (11:08 +0100)]
[libre-riscv-dev] googleusercontent looks like it got hacked yesterday
bugzilla-daemon [Wed, 3 Jun 2020 03:27:01 +0000 (03:27 +0000)]
[libre-riscv-dev] [Bug 325] create POWER9 TRAP pipeline
bugzilla-daemon [Wed, 3 Jun 2020 02:31:04 +0000 (02:31 +0000)]
[libre-riscv-dev] [Bug 325] create POWER9 TRAP pipeline
bugzilla-daemon [Wed, 3 Jun 2020 01:50:05 +0000 (01:50 +0000)]
[libre-riscv-dev] [Bug 325] create POWER9 TRAP pipeline
bugzilla-daemon [Wed, 3 Jun 2020 01:41:06 +0000 (01:41 +0000)]
[libre-riscv-dev] [Bug 325] create POWER9 TRAP pipeline
bugzilla-daemon [Wed, 3 Jun 2020 01:35:18 +0000 (01:35 +0000)]
[libre-riscv-dev] [Bug 325] create POWER9 TRAP pipeline
Luke Kenneth Casson Leighton [Wed, 3 Jun 2020 01:28:59 +0000 (02:28 +0100)]
Re: [libre-riscv-dev] [OpenPOWER-HDL-Cores] microwatt decoder tables: M-Form and X-Form switched RS and RB
bugzilla-daemon [Wed, 3 Jun 2020 01:28:01 +0000 (01:28 +0000)]
[libre-riscv-dev] [Bug 325] create POWER9 TRAP pipeline
bugzilla-daemon [Wed, 3 Jun 2020 01:13:32 +0000 (01:13 +0000)]
[libre-riscv-dev] [Bug 325] create POWER9 TRAP pipeline
projects / libre-riscv-dev.git / log