gcc.git
3 years agoamdgcn: Fix subdf3 pattern
Julian Brown [Mon, 30 Nov 2020 20:01:37 +0000 (12:01 -0800)]
amdgcn: Fix subdf3 pattern

This patch fixes a typo in the subdf3 pattern that meant it had a
non-standard name and thus the compiler would emit a libcall rather than
the proper hardware instruction for DFmode subtraction.

2021-01-13  Julian Brown  <julian@codesourcery.com>

gcc/
* config/gcn/gcn-valu.md (subdf): Rename to...
(subdf3): This.

3 years agoDaily bump.
GCC Administrator [Wed, 13 Jan 2021 00:16:36 +0000 (00:16 +0000)]
Daily bump.

3 years agosyscall: ensure openat uses variadic libc wrapper
Paul E. Murphy [Fri, 8 Jan 2021 21:43:54 +0000 (15:43 -0600)]
syscall: ensure openat uses variadic libc wrapper

On powerpc64le, this caused a failure in TestUnshareUidGidMapping
due to stack corruption which resulted in a bogus execve syscall.

Use the existing c wrapper to ensure we respect the ppc abi for
variadic functions.

Fixes PR go/98610

Reviewed-on: https://go-review.googlesource.com/c/gofrontend/+/282717

3 years agoAvoid a couple more ICEs in print_mem_ref (PR c/98597).
Martin Sebor [Tue, 12 Jan 2021 19:58:27 +0000 (12:58 -0700)]
Avoid a couple more ICEs in print_mem_ref (PR c/98597).

Resolves:
PR c/98597 - ICE in -Wuninitialized printing a MEM_REF
PR c/98592 - ICE in gimple_canonical_types_compatible_p while formatting

gcc/c-family/ChangeLog:

PR c/98597
PR c/98592
* c-pretty-print.c (print_mem_ref): Avoid assuming MEM_REF operand
has pointer type.  Remove redundant code.  Avoid calling
gimple_canonical_types_compatible_p.

gcc/testsuite/ChangeLog:

PR c/98597
PR c/98592
* g++.dg/warn/Wuninitialized-13.C: New test.
 gcc.dg/uninit-39.c: New test.

#

3 years agoMAINTAINERS: Fix spacing
Segher Boessenkool [Tue, 12 Jan 2021 18:39:10 +0000 (18:39 +0000)]
MAINTAINERS: Fix spacing

We indent with tabs, not spaces.  This fixes it.

2021-01-12  Segher Boessenkool  <segher@kernel.crashing.org>

* MAINTAINERS: Fix spacing.

3 years agolibcody: Simplify configure [PR 98414, 98509]
Nathan Sidwell [Mon, 11 Jan 2021 16:50:21 +0000 (08:50 -0800)]
libcody: Simplify configure [PR 98414, 98509]

Libcody's configurey was overly 'clever'.  That didn't play well with
GCC's structure.  This removes lots of that overengineering, using
libcpp as an example.

libcody/
* Makefile.in: Remove auto parallelize, swallow Makesub.in. Don't
check compiler name here.
* Makesub.in: Delete.
* build-aux/config.guess: Delete.
* build-aux/config.sub: Delete.
* build-aux/install-sh: Delete.
* dox.cfg.in: Delete.
* gdbinit.in: Delete.
* internal.hh (BuildNote): Delete.
* fatal.cc (BuildNote): Delete.
* config.m4: Remove unneeded fns.
* configure.ac: Remove unneccessary checks and configures.
* configure: Rebuilt.
* config.h.in: Rebuilt.

3 years agogcov: fix printf format for 32-bit hosts
Martin Liska [Tue, 12 Jan 2021 17:16:05 +0000 (18:16 +0100)]
gcov: fix printf format for 32-bit hosts

gcc/ChangeLog:

* gcov.c (source_info::debug): Fix printf format for 32-bit hosts.

3 years agoFix typo in function-abi.h
Andrea Corallo [Tue, 12 Jan 2021 16:52:52 +0000 (17:52 +0100)]
Fix typo in function-abi.h

gcc/Changelog

2021-01-12  Andrea Corallo  <andrea.corallo@arm.com>

* function-abi.h: Fix typo.

3 years agoarm: Add movmisalign patterns for MVE (PR target/97875)
Christophe Lyon [Tue, 12 Jan 2021 16:47:27 +0000 (16:47 +0000)]
arm: Add movmisalign patterns for MVE (PR target/97875)

This patch adds new movmisalign<mode>_mve_load and store patterns for
MVE to help vectorization. They are very similar to their Neon
counterparts, but use different iterators and instructions.

Indeed MVE supports less vectors modes than Neon, so we use the
MVE_VLD_ST iterator where Neon uses VQX.

Since the supported modes are different from the ones valid for
arithmetic operators, we introduce two new sets of macros:

ARM_HAVE_NEON_<MODE>_LDST
  true if Neon has vector load/store instructions for <MODE>

ARM_HAVE_<MODE>_LDST
  true if any vector extension has vector load/store instructions for <MODE>

We move the movmisalign<mode> expander from neon.md to vec-commond.md, and
replace the TARGET_NEON enabler with ARM_HAVE_<MODE>_LDST.

The patch also updates the mve-vneg.c test to scan for the better code
generation when loading and storing the vectors involved: it checks
that no 'orr' instruction is generated to cope with misalignment at
runtime.
This test was chosen among the other mve tests, but any other should
be OK. Using a plain vector copy loop (dest[i] = a[i]) is not a good
test because the compiler chooses to use memcpy.

For instance we now generate:
test_vneg_s32x4:
vldrw.32       q3, [r1]
vneg.s32  q3, q3
vstrw.32       q3, [r0]
bx      lr

instead of:
test_vneg_s32x4:
orr     r3, r1, r0
lsls    r3, r3, #28
bne     .L15
vldrw.32 q3, [r1]
vneg.s32  q3, q3
vstrw.32 q3, [r0]
bx      lr
.L15:
push    {r4, r5}
ldrd    r2, r3, [r1, #8]
ldrd    r5, r4, [r1]
rsbs    r2, r2, #0
rsbs    r5, r5, #0
rsbs    r4, r4, #0
rsbs    r3, r3, #0
strd    r5, r4, [r0]
pop     {r4, r5}
strd    r2, r3, [r0, #8]
bx      lr

2021-01-12  Christophe Lyon  <christophe.lyon@linaro.org>

PR target/97875
gcc/
* config/arm/arm.h (ARM_HAVE_NEON_V8QI_LDST): New macro.
(ARM_HAVE_NEON_V16QI_LDST, ARM_HAVE_NEON_V4HI_LDST): Likewise.
(ARM_HAVE_NEON_V8HI_LDST, ARM_HAVE_NEON_V2SI_LDST): Likewise.
(ARM_HAVE_NEON_V4SI_LDST, ARM_HAVE_NEON_V4HF_LDST): Likewise.
(ARM_HAVE_NEON_V8HF_LDST, ARM_HAVE_NEON_V4BF_LDST): Likewise.
(ARM_HAVE_NEON_V8BF_LDST, ARM_HAVE_NEON_V2SF_LDST): Likewise.
(ARM_HAVE_NEON_V4SF_LDST, ARM_HAVE_NEON_DI_LDST): Likewise.
(ARM_HAVE_NEON_V2DI_LDST): Likewise.
(ARM_HAVE_V8QI_LDST, ARM_HAVE_V16QI_LDST): Likewise.
(ARM_HAVE_V4HI_LDST, ARM_HAVE_V8HI_LDST): Likewise.
(ARM_HAVE_V2SI_LDST, ARM_HAVE_V4SI_LDST, ARM_HAVE_V4HF_LDST): Likewise.
(ARM_HAVE_V8HF_LDST, ARM_HAVE_V4BF_LDST, ARM_HAVE_V8BF_LDST): Likewise.
(ARM_HAVE_V2SF_LDST, ARM_HAVE_V4SF_LDST, ARM_HAVE_DI_LDST): Likewise.
(ARM_HAVE_V2DI_LDST): Likewise.
* config/arm/mve.md (*movmisalign<mode>_mve_store): New pattern.
(*movmisalign<mode>_mve_load): New pattern.
* config/arm/neon.md (movmisalign<mode>): Move to ...
* config/arm/vec-common.md: ... here.

PR target/97875
gcc/testsuite/
* gcc.target/arm/simd/mve-vneg.c: Update test.

3 years ago[PR97969] LRA: Transform pattern `plus (plus (hard reg, const), pseudo)` after elimin...
Vladimir N. Makarov [Tue, 12 Jan 2021 16:26:15 +0000 (11:26 -0500)]
[PR97969] LRA: Transform pattern `plus (plus (hard reg, const), pseudo)` after elimination

LRA can loop infinitely on targets without `reg + imm` insns.  Register elimination
on such targets can increase register pressure resulting in permanent
stack size increase and changing elimination offset.  To avoid such situation, a simple
transformation can be done to avoid register pressure increase after
generating reload insns containing eliminated hard regs.

gcc/ChangeLog:

PR target/97969
* lra-eliminations.c (eliminate_regs_in_insn): Add transformation
of pattern 'plus (plus (hard reg, const), pseudo)'.

gcc/testsuite/ChangeLog:

PR target/97969
* gcc.target/arm/pr97969.c: New.

3 years agoc++: Fix ICE with CTAD in concept [PR98611]
Patrick Palka [Tue, 12 Jan 2021 14:34:41 +0000 (09:34 -0500)]
c++: Fix ICE with CTAD in concept [PR98611]

This patch teaches cp_walk_subtrees to visit the template represented
by a CTAD placeholder, which would otherwise be not visited during
find_template_parameters.  The template may be a template template
parameter (as in the first testcase), or it may implicitly use the
template parameters of an enclosing class template (as in the second
testcase), and in either case we need to visit this tree to record the
template parameters used therein for later satisfaction.

gcc/cp/ChangeLog:

PR c++/98611
* tree.c (cp_walk_subtrees) <case TEMPLATE_TYPE_PARM>: Visit
the template of a CTAD placeholder.

gcc/testsuite/ChangeLog:

PR c++/98611
* g++.dg/cpp2a/concepts-ctad1.C: New test.
* g++.dg/cpp2a/concepts-ctad2.C: New test.

3 years agotree-optimization/98550 - fix BB vect unrolling check
Richard Biener [Tue, 12 Jan 2021 10:17:33 +0000 (11:17 +0100)]
tree-optimization/98550 - fix BB vect unrolling check

This fixes the check that disqualifies BB vectorization because of
required unrolling to match up with the later exact_div we do.  To
not disable the ability to split groups that do not match up
exactly with a choosen vector type this also introduces a soft-fail
mechanism to vect_build_slp_tree_1 which delays failing to after
the matches[] array is populated from other checks and only then
determines the split point according to the vector type.

2021-01-12  Richard Biener  <rguenther@suse.de>

PR tree-optimization/98550
* tree-vect-slp.c (vect_record_max_nunits): Check whether
the group size is a multiple of the vector element count.
(vect_build_slp_tree_1): When we need to fail because
the vector type choosen causes unrolling do so lazily
without affecting matches only at the end to guide group splitting.

* g++.dg/opt/pr98550.C: New testcase.

3 years agooptions: properly compare string arguments
Martin Liska [Tue, 12 Jan 2021 12:20:18 +0000 (13:20 +0100)]
options: properly compare string arguments

Similarly to 7f967bd2a7ba156ede3fbb147e66dea5fb7137a6, we need to
compare string with strcmp.

gcc/ChangeLog:

PR c++/97284
* optc-save-gen.awk: Compare also n_target_save vars with
strcmp.

3 years agogcov: add more debugging facility
Martin Liska [Tue, 12 Jan 2021 10:27:34 +0000 (11:27 +0100)]
gcov: add more debugging facility

gcc/ChangeLog:

* gcov.c (source_info::debug): New.
(print_usage): Add --debug (-D) option.
(process_args): Likewise.
(generate_results): Call src->debug after
accumulate_line_counts.
(read_graph_file): Properly assign id for EXIT_BLOCK.
* profile.c (branch_prob): Dump function body before it is
instrumented.

3 years agowidening_mul: Fix up ICE caused by my signed multiplication overflow pattern recognit...
Jakub Jelinek [Tue, 12 Jan 2021 10:04:46 +0000 (11:04 +0100)]
widening_mul: Fix up ICE caused by my signed multiplication overflow pattern recognition changes [PR98629]

As the testcase shows, my latest changes caused ICE on that testcase.
The problem is that arith_overflow_check_p now can change the use_stmt
argument (has a reference), so that if it succeeds (returns non-zero),
it points it to the GIMPLE_COND or EQ/NE or COND_EXPR assignment from the
TRUNC_DIV_EXPR assignment.
The problem was that it would change use_stmt also if it returned 0 in some
cases, such as multiple imm uses of the division, and in one of the callers
if arith_overflow_check_p returns 0 it looks at use_stmt again and performs
other checks, which of course assumes that use_stmt is the one passed
to arith_overflow_check_p and not e.g. NULL instead or some other unrelated
stmt.

The following patch fixes that by only changing use_stmt when we are about
to return non-zero (for the MULT_EXPR case, which is the only one with the
need to use different use_stmt).

2021-01-12  Jakub Jelinek  <jakub@redhat.com>

PR tree-optimization/98629
* tree-ssa-math-opts.c (arith_overflow_check_p): Don't update use_stmt
unless returning non-zero.

* gcc.c-torture/compile/pr98629.c: New test.

3 years agoreassoc: Optimize in reassoc x < 0 && y < 0 to (x | y) < 0 etc. [PR95731]
Jakub Jelinek [Tue, 12 Jan 2021 10:03:40 +0000 (11:03 +0100)]
reassoc: Optimize in reassoc x < 0 && y < 0 to (x | y) < 0 etc. [PR95731]

We already had x != 0 && y != 0 to (x | y) != 0 and
x != -1 && y != -1 to (x & y) != -1 and
x < 32U && y < 32U to (x | y) < 32U, this patch adds signed
x < 0 && y < 0 to (x | y) < 0.  In that case, the low/high seem to be
always the same and just in_p indices whether it is >= 0 or < 0,
also, all types in the same bucket (same precision) should be type
compatible, but we can have some >= 0 and some < 0 comparison mixed,
so the patch handles that by using the right BIT_IOR_EXPR or BIT_AND_EXPR
and doing one set of < 0 or >= 0 first, then BIT_NOT_EXPR and then the other
one.  I had to move optimize_range_tests_var_bound before this optimization
because that one deals with signed a >= 0 && a < b, and limited it to the
last reassoc pass as reassoc itself can't virtually undo this optimization
yet (and not sure if vrp would be able to).

2021-01-12  Jakub Jelinek  <jakub@redhat.com>

PR tree-optimization/95731
* tree-ssa-reassoc.c (optimize_range_tests_cmp_bitwise): Also optimize
x < 0 && y < 0 && z < 0 into (x | y | z) < 0 for signed x, y, z.
(optimize_range_tests): Call optimize_range_tests_cmp_bitwise
only after optimize_range_tests_var_bound.

* gcc.dg/tree-ssa/pr95731.c: New test.
* gcc.c-torture/execute/pr95731.c: New test.

3 years agoconfigure, make: Fix up --enable-link-serialization
Jakub Jelinek [Tue, 12 Jan 2021 10:02:16 +0000 (11:02 +0100)]
configure, make: Fix up --enable-link-serialization

As reported by Matthias, --enable-link-serialization=1 can currently start
two concurrent links first (e.g. gnat1 and cc1).
The problem is that make var = value values seem to work differently between
dependencies and actual rules (where it was tested).
As the language make fragments can be in different order, we can have:
ada.prev = ... magic that will become $(c.serial) under --enable-link-serialization=1
gnat1$(exe): ..... $(ada.prev)
...
c.serial = cc1$(exe)
and while if I add echo $(ada.prev) in the gnat1 rule's command, it prints
cc1, the dependencies are actually evaluated during reading of the goal or
when.
The configure creates (and puts into Makefile) some serialization order of
the languages and in that order c always comes first, and the rest is
actually sorted the way the all_lang_makefrags are already sorted,
so just by forcing c/Make-lang.in first we achieve that X.serial variable
is always defined before some other Y.prev will use it in its goal
dependencies.

2021-01-12  Jakub Jelinek  <jakub@redhat.com>

* configure.ac: Ensure c/Make-lang.in comes first in @all_lang_makefrags@.
* configure: Regenerated.

3 years agoMAINTAINERS: Add myself for write after approval
Qian Jianhua [Tue, 12 Jan 2021 07:32:43 +0000 (15:32 +0800)]
MAINTAINERS: Add myself for write after approval

ChangeLog:

2021-01-12  Qian Jianhua  <qianjh@cn.fujitsu.com>

* MAINTAINERS (Write After Approval): Add myself

3 years agoc++: -Wmissing-field-initializers in unevaluated ctx [PR98620]
Marek Polacek [Mon, 11 Jan 2021 16:44:36 +0000 (11:44 -0500)]
c++: -Wmissing-field-initializers in unevaluated ctx [PR98620]

This PR wants us not to warn about missing field initializers when
the code in question takes places in decltype and similar.  Fixed
thus.

gcc/cp/ChangeLog:

PR c++/98620
* typeck2.c (process_init_constructor_record): Don't emit
-Wmissing-field-initializers warnings in unevaluated contexts.

gcc/testsuite/ChangeLog:

PR c++/98620
* g++.dg/warn/Wmissing-field-initializers-2.C: New test.

3 years agoDelete dead code in ix86_expand_sse_comi.
liuhongt [Mon, 11 Jan 2021 06:47:49 +0000 (14:47 +0800)]
Delete dead code in ix86_expand_sse_comi.

d->flag is always 0 for builtins located in
BDESC_FIRST (comi,COMI,...)
...
BDESC_END (COMI, PCMPESTR)

gcc/ChangeLog:
PR target/98612
* config/i386/i386-builtins.h (BUILTIN_DESC_SWAP_OPERANDS):
Deleted.
* config/i386/i386-expand.c (ix86_expand_sse_comi): Delete
dead code.

3 years agomake FOR_EACH_IMM_USE_STMT safe for early exits
Alexandre Oliva [Tue, 12 Jan 2021 02:37:59 +0000 (23:37 -0300)]
make FOR_EACH_IMM_USE_STMT safe for early exits

Use a dtor to automatically remove ITER from IMM_USE list in
FOR_EACH_IMM_USE_STMT.

for  gcc/ChangeLog

* ssa-iterators.h (end_imm_use_stmt_traverse): Forward
declare.
(auto_end_imm_use_stmt_traverse): New struct.
(FOR_EACH_IMM_USE_STMT): Use it.
(BREAK_FROM_IMM_USE_STMT, RETURN_FROM_IMM_USE_STMT): Remove,
along with uses...
* gimple-ssa-strength-reduction.c: ... here, ...
* graphite-scop-detection.c: ... here, ...
* ipa-modref.c, ipa-pure-const.c, ipa-sra.c: ... here, ...
* tree-predcom.c, tree-ssa-ccp.c: ... here, ...
* tree-ssa-dce.c, tree-ssa-dse.c: ... here, ...
* tree-ssa-loop-ivopts.c, tree-ssa-math-opts.c: ... here, ...
* tree-ssa-phiprop.c, tree-ssa.c: ... here, ...
* tree-vect-slp.c: ... and here, ...
* doc/tree-ssa.texi: ... and the example here.

3 years agoanalyzer: fix ICE merging dereferencing unknown ptrs [PR98628]
David Malcolm [Tue, 12 Jan 2021 01:23:41 +0000 (20:23 -0500)]
analyzer: fix ICE merging dereferencing unknown ptrs [PR98628]

gcc/analyzer/ChangeLog:
PR analyzer/98628
* store.cc (binding_cluster::make_unknown_relative_to): Don't mark
dereferenced unknown pointers as having escaped.

gcc/testsuite/ChangeLog:
PR analyzer/98628
* gcc.dg/analyzer/pr98628.c: New test.

3 years agoDaily bump.
GCC Administrator [Tue, 12 Jan 2021 00:16:22 +0000 (00:16 +0000)]
Daily bump.

3 years agoaarch64: Add support for unpacked SVE ASRD
Richard Sandiford [Mon, 11 Jan 2021 18:03:26 +0000 (18:03 +0000)]
aarch64: Add support for unpacked SVE ASRD

This patch adds support for both conditional and unconditional unpacked
ASRD.  This meant adding a new define_insn for the unconditional form,
instead of reusing the conditional instructions.  It also meant
extending the current conditional patterns to support merging with
any independent value, not just zero.

gcc/
* config/aarch64/aarch64-sve.md (sdiv_pow2<mode>3): Extend from
SVE_FULL_I to SVE_I.  Generate an UNSPEC_PRED_X.
(*sdiv_pow2<mode>3): New pattern.
(@cond_<sve_int_op><mode>): Extend from SVE_FULL_I to SVE_I.
Wrap the ASRD in an UNSPEC_PRED_X.
(*cond_<sve_int_op><mode>_2): Likewise.  Replace the UNSPEC_PRED_X
predicate with a constant PTRUE, if it isn't already.
(*cond_<sve_int_op><mode>_z): Replace with...
(*cond_<sve_int_op><mode>_any): ...this new pattern.

gcc/testsuite/
* gcc.target/aarch64/sve/asrdiv_4.c: New test.
* gcc.target/aarch64/sve/cond_asrd_1.c: Likewise.
* gcc.target/aarch64/sve/cond_asrd_1_run.c: Likewise.
* gcc.target/aarch64/sve/cond_asrd_2.c: Likewise.
* gcc.target/aarch64/sve/cond_asrd_2_run.c: Likewise.
* gcc.target/aarch64/sve/cond_asrd_3.c: Likewise.
* gcc.target/aarch64/sve/cond_asrd_3_run.c: Likewise.

3 years agoaarch64: Add support for unpacked SVE conditional BIC
Richard Sandiford [Mon, 11 Jan 2021 18:03:25 +0000 (18:03 +0000)]
aarch64: Add support for unpacked SVE conditional BIC

This patch adds support for unpacked conditional BIC.  The type suffix
could be taken from the element size or the container size, so the
patch continues to use the element size.  This is consistent with
the existing support for unconditional BIC.

gcc/
* config/aarch64/aarch64-sve.md (*cond_bic<mode>_2): Extend from
SVE_FULL_I to SVE_I.
(*cond_bic<mode>_any): Likewise.

gcc/testsuite/
* g++.target/aarch64/sve/cond_bic_1.C: New test.
* g++.target/aarch64/sve/cond_bic_2.C: Likewise.
* g++.target/aarch64/sve/cond_bic_3.C: Likewise.
* g++.target/aarch64/sve/cond_bic_4.C: Likewise.

3 years agoaarch64: Add support for unpacked SVE MULH
Richard Sandiford [Mon, 11 Jan 2021 18:03:24 +0000 (18:03 +0000)]
aarch64: Add support for unpacked SVE MULH

This patch extends the SMULH and UMULH support to unpacked vectors.
The type suffix must be taken from the element size rather than the
container size.

The main use of these patterns is to support division and modulus
by a constant.  The conditional forms would be hard to trigger from
non-ACLE code, and ACLE code needs fully-packed vectors only.

gcc/
* config/aarch64/aarch64-sve.md (<su>mul<mode>3_highpart)
(@aarch64_pred_<MUL_HIGHPART:optab><mode>): Extend from SVE_FULL_I
to SVE_I.

gcc/testsuite/
* gcc.target/aarch64/sve/mul_highpart_3.c: New test.

3 years agoaarch64: Add support for unpacked SVE ABD
Richard Sandiford [Mon, 11 Jan 2021 18:03:23 +0000 (18:03 +0000)]
aarch64: Add support for unpacked SVE ABD

This patch adds support for unpacked SVE SABD and UABD.
It also rewrites the patterns so that they match as combine
patterns without the need for REG_EQUAL notes.  Finally,
there was no pattern for merging with the second input,
which can be handled by reversing the operands.

The type suffix needs to be taken from the element size rather
than the container size.

gcc/
* config/aarch64/aarch64-sve.md (<su>abd<mode>_3): Extend from
SVE_FULL_I to SVE_I.
(*aarch64_cond_<su>abd<mode>_2): Likewise.
(*aarch64_cond_<su>abd<mode>_any): Likewise.
(@aarch64_pred_<su>abd<mode>): Likewise.  Use UNSPEC_PRED_X
for the max and min but not for the minus.
(*aarch64_cond_<su>abd<mode>_3): New pattern.

gcc/testsuite/
* g++.target/aarch64/sve/abd_1.C: New test.
* g++.target/aarch64/sve/cond_abd_1.C: Likewise.
* g++.target/aarch64/sve/cond_abd_2.C: Likewise.
* g++.target/aarch64/sve/cond_abd_3.C: Likewise.
* g++.target/aarch64/sve/cond_abd_4.C: Likewise.

3 years agoaarch64: Add support for unpacked SVE ADR
Richard Sandiford [Mon, 11 Jan 2021 18:03:23 +0000 (18:03 +0000)]
aarch64: Add support for unpacked SVE ADR

This patch extends the ADR patterns to handle unpacked vectors.
They would work with both elements and containers, but since
the instructions only support .s and .d, we get more coverage
by using containers.

gcc/
* config/aarch64/iterators.md (SVE_24I): New iterator.
* config/aarch64/aarch64-sve.md (*aarch64_adr<mode>_shift): Extend from
SVE_FULL_SDI to SVE_24I.  Use containers rather than elements.

gcc/testsuite/
* gcc.target/aarch64/sve/adr_6.c: New test.

3 years agoaarch64: Add general unpacked SVE conditional binary arithmetic
Richard Sandiford [Mon, 11 Jan 2021 18:03:22 +0000 (18:03 +0000)]
aarch64: Add general unpacked SVE conditional binary arithmetic

This patch adds support for conditional binary ADD, SUB, MUL, SMAX,
UMAX, SMIN, UMIN, LSL, LSR, ASR, AND, ORR and EOR.  It's not really
possible to split it up further given how the patterns are written.

Min, max and right-shift need the element size rather than the container
size.  The others would work with both, although MUL should be more
efficient when applied to elements instead of containers.

gcc/
* config/aarch64/aarch64-sve.md (@cond_<SVE_INT_BINARY:optab><mode>)
(*cond_<SVE_INT_BINARY:optab><mode>_2): Extend from SVE_FULL_I
to SVE_I.
(*cond_<SVE_INT_BINARY:optab><mode>_3): Likewise.
(*cond_<SVE_INT_BINARY:optab><mode>_any): Likewise.
(*cond_<SVE_INT_BINARY:optab><mode>_2_const): Likewise.
(*cond_<SVE_INT_BINARY:optab><mode>_any_const): Likewise.

gcc/testsuite/
* g++.target/aarch64/sve/cond_arith_1.C: New test.
* g++.target/aarch64/sve/cond_arith_2.C: Likewise.
* g++.target/aarch64/sve/cond_arith_3.C: Likewise.
* g++.target/aarch64/sve/cond_arith_4.C: Likewise.
* g++.target/aarch64/sve/cond_shift_1.C: New test.
* g++.target/aarch64/sve/cond_shift_2.C: Likewise.
* g++.target/aarch64/sve/cond_shift_3.C: Likewise.
* g++.target/aarch64/sve/cond_shift_4.C: Likewise.

3 years agoaarch64: Add support for unpacked SVE mult, max and min
Richard Sandiford [Mon, 11 Jan 2021 18:03:21 +0000 (18:03 +0000)]
aarch64: Add support for unpacked SVE mult, max and min

This patch makes the SVE_INT_BINARY_IMM patterns support
unpacked arithmetic, covering MUL, SMAX, SMIN, UMAX and UMIN.
For min and max, the type suffix must be taken from the element
size rather than the container size.

The XFAILs are due to PR98602.

gcc/
* config/aarch64/aarch64-sve.md (<SVE_INT_BINARY_IMM:optab><mode>3)
(@aarch64_pred_<SVE_INT_BINARY_IMM:optab><mode>)
(*post_ra_<SVE_INT_BINARY_IMM:optab><mode>3): Extend from SVE_FULL_I
to SVE_I.

gcc/testsuite/
PR testsuite/98602
* g++.target/aarch64/sve/max_1.C: New test.
* g++.target/aarch64/sve/min_1.C: Likewise.
* gcc.target/aarch64/sve/mul_2.c: Likewise.

3 years agoaarch64: Add support for unpacked SVE shifts
Richard Sandiford [Mon, 11 Jan 2021 18:03:20 +0000 (18:03 +0000)]
aarch64: Add support for unpacked SVE shifts

This patch adds support for unpacked SVE LSL, ASR and LSR.
For right shifts, the type suffix needs to be taken from the
element size rather than the container size.

gcc/
* config/aarch64/aarch64-sve.md (<ASHIFT:optab><mode>3)
(v<ASHIFT:optab><mode>3, @aarch64_pred_<optab><mode>)
(*post_ra_v<ASHIFT:optab><mode>3): Extend from SVE_FULL_I to SVE_I.

gcc/testsuite/
* gcc.target/aarch64/sve/shift_2.c: New test.

3 years agoProperly release symtab::m_clones.
Martin Liska [Mon, 11 Jan 2021 13:01:07 +0000 (14:01 +0100)]
Properly release symtab::m_clones.

gcc/ChangeLog:

PR jit/98615
* symtab-clones.h (clone_info::release): Release
symtab::m_clones with ggc_delete as it's a GGC memory.

3 years agoc++, abi: Fix abi_tag attribute handling [PR98481]
Jakub Jelinek [Thu, 7 Jan 2021 16:47:18 +0000 (17:47 +0100)]
c++, abi: Fix abi_tag attribute handling [PR98481]

In GCC10 cp_walk_subtrees has been changed to walk template arguments.
As the following testcase, that changed the mangling of some functions.
I believe the previous behavior that find_abi_tags_r doesn't recurse into
template args has been the correct one, but setting *walk_subtrees = 0
for the types and handling the types subtree walking manually in
find_abi_tags_r looks too hard, there are a lot of subtrees and details what
should and shouldn't be walked, both in tree.c (walk_type_fields there,
which is static) and in cp_walk_subtrees itself.

The following patch abuses the fact that *walk_subtrees is an int to
tell cp_walk_subtrees it shouldn't walk the template args.

Co-authored-by: Jason Merrill <jason@redhat.com>
gcc/cp/ChangeLog:

PR c++/98481
* class.c (find_abi_tags_r): Set *walk_subtrees to 2 instead of 1
for types.
(mark_abi_tags_r): Likewise.
* decl2.c (min_vis_r): Likewise.
* tree.c (cp_walk_subtrees): If *walk_subtrees_p is 2, look through
typedefs.

gcc/testsuite/ChangeLog:

PR c++/98481
* g++.dg/abi/abi-tag24.C: New test.

3 years agoMake the serialized link target more verbose
Matthias Klose [Mon, 11 Jan 2021 14:51:35 +0000 (14:51 +0000)]
Make the serialized link target more verbose

2020-12-07  Matthias Klose  <doko@ubuntu.com>

* Makefile.in (LINK_PROGRESS): Show the link target.

3 years agoPort update-copyright.py to Python3
Martin Liska [Mon, 4 Jan 2021 10:13:04 +0000 (11:13 +0100)]
Port update-copyright.py to Python3

contrib/ChangeLog:

* update-copyright.py: Port to python3 by guessing encoding
(first utf8, then iso8859). Add 2 more ignores: .png and .pyc.

3 years agotree-optimization/91403 - avoid excessive code-generation
Richard Biener [Mon, 11 Jan 2021 11:04:32 +0000 (12:04 +0100)]
tree-optimization/91403 - avoid excessive code-generation

The vectorizer, for large permuted grouped loads, generates
inefficient intermediate code (cleaned up only later) that runs
into complexity issues in SCEV analysis and elsewhere.  For the
non-single-element interleaving case we already put a hard limit
in place, this applies the same limit to the missing case.

2021-01-11  Richard Biener  <rguenther@suse.de>

PR tree-optimization/91403
* tree-vect-data-refs.c (vect_analyze_group_access_1): Cap
single-element interleaving group size at 4096 elements.

* gcc.dg/vect/pr91403.c: New testcase.

3 years agotestsuite: Fix test failures from outputs.exp [PR98225]
Bernd Edlinger [Thu, 7 Jan 2021 08:37:32 +0000 (09:37 +0100)]
testsuite: Fix test failures from outputs.exp [PR98225]

The .ld1_args file is not created when HAVE_GNU_LD is false.
The ltrans0.ltrans_arg file is not created when the make jobserver
is available, so remove the MAKEFLAGS variable.
Add an exception for *.gcc_args files similar to the
exception for *.cdtor.* files.
Limit both exceptions to targets that define EH_FRAME_THROUGH_COLLECT2.
That means although the test case does not use C++ constructors
or destructors it is still using dwarf2 frame info.

2021-01-11  Bernd Edlinger  <bernd.edlinger@hotmail.de>

PR testsuite/98225
* gcc.misc-tests/outputs.exp: Unset MAKEFLAGS.
Expect .ld1_args only when GNU LD is used.
Add an exception for *.gcc_args files.

3 years agotree-optimization/98526 - fix vectorizer reduction cost
Richard Biener [Mon, 11 Jan 2021 10:47:46 +0000 (11:47 +0100)]
tree-optimization/98526 - fix vectorizer reduction cost

This fixes a double-counting in the reduction cost when vectorizing
the reduction through the regular vectorizable_* functions.

2021-01-11  Richard Biener  <rguenther@suse.de>

PR tree-optimization/98526
* tree-vect-loop.c (vect_model_reduction_cost): Remove costing
of the actual reduction op for the regular case.
(vectorizable_reduction): Cost the stmts
vect_transform_reduction produces here.

3 years agod: Remove visibility and lookup deprecation
Iain Buclaw [Mon, 11 Jan 2021 09:53:18 +0000 (10:53 +0100)]
d: Remove visibility and lookup deprecation

The deprecation phase for access checks is finished.

The `-ftransition=import` and `-ftransition=checkimports` switches no
longer have an effect and are now removed.  Symbols that are not visible
in a particular scope will no longer be found by the compiler.

Reviewed-on: https://github.com/dlang/dmd/pull/12124

gcc/d/ChangeLog:

* dmd/MERGE: Merge upstream dmd 2d3d13748.
* d-lang.cc (d_handle_option): Remove OPT_ftransition_checkimports and
OPT_ftransition_import.
* gdc.texi (Warnings): Remove documentation for -ftransition=import
and -ftransition=checkimports.
* lang.opt (ftransition=checkimports): Remove.
(ftransition=import): Remove.

3 years agotree-optimization/98221 - fix wrong unpack operation used for big-endian
Andreas Krebbel [Mon, 11 Jan 2021 09:59:43 +0000 (10:59 +0100)]
tree-optimization/98221 - fix wrong unpack operation used for big-endian

The vec-abi-varargs-1.c testcase on IBM Z currently fails.

While adding an SI mode vector to a DI mode vector the first is unpacked using:

  _28 = BIT_INSERT_EXPR <{ 0, 0, 0, 0 }, _2, 0>;
  _34 = [vec_unpack_lo_expr] _28;

However, on big endian targets lo refers to the right hand side of the vector - in this case the zeroes.

2021-01-11  Andreas Krebbel  <krebbel@linux.ibm.com>

* tree-ssa-forwprop.c (simplify_vector_constructor): For
big-endian, use UNPACK[_FLOAT]_HI.

3 years agoslp: upgrade complex add to new format and fix memory leaks
Tamar Christina [Mon, 11 Jan 2021 09:58:36 +0000 (09:58 +0000)]
slp: upgrade complex add to new format and fix memory leaks

This fixes a memory leak in complex_add_pattern because I was not calling
vect_free_slp_tree when dissolving one side of the TWO_OPERANDS nodes.

Secondly it also upgrades the class to the new inteface required by the other
patterns.

gcc/ChangeLog:

* tree-vect-slp-patterns.c (class complex_pattern,
class complex_add_pattern): Add parameters to matches.
(complex_add_pattern::build): Free memory.
(complex_add_pattern::matches): Move validation end of match.
(complex_add_pattern::recognize): Likewise.

3 years agoslp: handle externals correctly in linear_loads_p
Tamar Christina [Mon, 11 Jan 2021 09:57:41 +0000 (09:57 +0000)]
slp: handle externals correctly in linear_loads_p

This fixes a bug with externals and linear_loads_p where I forgot to save the
value before returning.

It also fixes handling of nodes with multiple children on a non VEC_PERM node.
There the child iteration would already resolve the kind and the loads are All
expected to be the same if valid so just return one.

gcc/ChangeLog:

* tree-vect-slp-patterns.c (linear_loads_p): Fix externals.

3 years agoslp: fix is_linear_load_p to prevent multiple answers
Tamar Christina [Mon, 11 Jan 2021 09:56:44 +0000 (09:56 +0000)]
slp: fix is_linear_load_p to prevent multiple answers

This fixes an issue where is_linear_load_p could return the incorrect
permutation kind because it is singe pass.

This arranges the candidates in such a way that there won't be any ambiguity so
that the function can still be linear but give correct values.

gcc/ChangeLog:

* tree-vect-slp-patterns.c (is_linear_load_p): Fix ambiguity.

3 years agoreassoc: Reassociate integral multiplies [PR95867]
Jakub Jelinek [Mon, 11 Jan 2021 09:35:10 +0000 (10:35 +0100)]
reassoc: Reassociate integral multiplies [PR95867]

For floating point multiply, we have nice code in reassoc to reassociate
multiplications to almost optimal sequence of as few multiplications as
possible (or library call), but for integral types we just give up
because there is no __builtin_powi* for those types.

As there is no library routine we could use, instead of adding new internal
call just to hold it temporarily and then lower to multiplications again,
this patch for the integral types calls into the sincos pass routine that
expands it into multiplications right away.

2021-01-11  Jakub Jelinek  <jakub@redhat.com>

PR tree-optimization/95867
* tree-ssa-math-opts.h: New header.
* tree-ssa-math-opts.c: Include tree-ssa-math-opts.h.
(powi_as_mults): No longer static.  Use build_one_cst instead of
build_real.  Formatting fix.
* tree-ssa-reassoc.c: Include tree-ssa-math-opts.h.
(attempt_builtin_powi): Handle multiplication reassociation without
powi_fndecl using powi_as_mults.
(reassociate_bb): For integral types don't require
-funsafe-math-optimizations to call attempt_builtin_powi.

* gcc.dg/tree-ssa/pr95867.c: New test.

3 years agowidening_mul: Pattern recognize also signed multiplication with overflow check [PR95852]
Jakub Jelinek [Mon, 11 Jan 2021 09:34:07 +0000 (10:34 +0100)]
widening_mul: Pattern recognize also signed multiplication with overflow check [PR95852]

On top of the previous widening_mul patch, this one recognizes also
(non-perfect) signed multiplication with overflow, like:
int
f5 (int x, int y, int *res)
{
  *res = (unsigned) x * y;
  return x && (*res / x) != y;
}
The problem with such checks is that they invoke UB if x is -1 and
y is INT_MIN during the division, but perhaps the code knows that
those values won't appear.  As that case is UB, we can do for that
case whatever we want and handling that case as signed overflow
is the best option.  If x is a constant not equal to -1, then the checks
are 100% correct though.
Haven't tried to pattern match bullet-proof checks, because I really don't
know if users would write it in real-world code like that,
perhaps
  *res = (unsigned) x * y;
  return x && (x == -1 ? (*res / y) != x : (*res / x) != y);
?

https://wiki.sei.cmu.edu/confluence/display/c/INT32-C.+Ensure+that+operations+on+signed+integers+do+not+result+in+overflow
suggests to use twice as wide multiplication (perhaps we should handle that
too, for both signed and unsigned), or some very large code
with 4 different divisions nested in many conditionals, no way one can
match all the possible variants thereof.

2021-01-11  Jakub Jelinek  <jakub@redhat.com>

PR tree-optimization/95852
* tree-ssa-math-opts.c (maybe_optimize_guarding_check): Change
mul_stmts parameter type to vec<gimple *> &.  Before cond_stmt
allow in the bb any of the stmts in that vector, div_stmt and
up to 3 cast stmts.
(arith_cast_equal_p): New function.
(arith_overflow_check_p): Add cast_stmt argument, handle signed
multiply overflow checks.
(match_arith_overflow): Adjust caller.  Handle signed multiply
overflow checks.

* gcc.target/i386/pr95852-3.c: New test.
* gcc.target/i386/pr95852-4.c: New test.

3 years agowidening_mul: Pattern recognize unsigned multiplication with overflow check [PR95852]
Jakub Jelinek [Mon, 11 Jan 2021 09:32:07 +0000 (10:32 +0100)]
widening_mul: Pattern recognize unsigned multiplication with overflow check [PR95852]

The following patch pattern recognizes some forms of multiplication followed
by overflow check through division by one of the operands compared to the
other one, with optional removal of guarding non-zero check for that operand
if possible.  The patterns are replaced with effectively
__builtin_mul_overflow or __builtin_mul_overflow_p.  The testcases cover 64
different forms of that.

2021-01-11  Jakub Jelinek  <jakub@redhat.com>

PR tree-optimization/95852
* tree-ssa-math-opts.c (maybe_optimize_guarding_check): New function.
(uaddsub_overflow_check_p): Renamed to ...
(arith_overflow_check_p): ... this.  Handle also multiplication
with overflow check.
(match_uaddsub_overflow): Renamed to ...
(match_arith_overflow): ... this.  Add cfg_changed argument.  Handle
also multiplication with overflow check.  Adjust function comment.
(math_opts_dom_walker::after_dom_children): Adjust callers.  Call
match_arith_overflow also for MULT_EXPR.

* gcc.target/i386/pr95852-1.c: New test.
* gcc.target/i386/pr95852-2.c: New test.

3 years agoaarch64: Reimplement vmovl*/vmovn* intrinsics using __builtin_convertvector
Kyrylo Tkachov [Fri, 8 Jan 2021 13:20:49 +0000 (13:20 +0000)]
aarch64: Reimplement vmovl*/vmovn* intrinsics using __builtin_convertvector

__builtin_convertvector seems well-suited to implementing the vmovl and
vmovn intrinsics that widen and narrow
the integer elements in a vector.

This removes some more inline assembly from the intrinsics.

gcc/
* config/aarch64/arm_neon.h (vmovl_s8): Reimplement using
__builtin_convertvector.
(vmovl_s16): Likewise.
(vmovl_s32): Likewise.
(vmovl_u8): Likewise.
(vmovl_u16): Likewise.
(vmovl_u32): Likewise.
(vmovn_s16): Likewise.
(vmovn_s32): Likewise.
(vmovn_s64): Likewise.
(vmovn_u16): Likewise.
(vmovn_u32): Likewise.
(vmovn_u64): Likewise.

3 years agoAdd pytest for a GCOV test-case
Martin Liska [Mon, 21 Dec 2020 08:14:28 +0000 (09:14 +0100)]
Add pytest for a GCOV test-case

gcc/testsuite/ChangeLog:

PR gcov-profile/98273
* lib/gcov.exp: Add run-gcov-pytest function which runs pytest.
* g++.dg/gcov/pr98273.C: New test.
* g++.dg/gcov/gcov.py: New test.
* g++.dg/gcov/test-pr98273.py: New test.

3 years agoif-to-switch: remove memory leaks
Martin Liska [Fri, 8 Jan 2021 13:28:29 +0000 (14:28 +0100)]
if-to-switch: remove memory leaks

gcc/ChangeLog:

* gimple-if-to-switch.cc (struct condition_info): Use auto_var.
(if_chain::is_beneficial): Delete clusters
(find_conditions): Make second argument of conditions_in_bbs a
pointer so that we control over it's lifetime.
(pass_if_to_switch::execute): Delete them.

3 years agoira: Skip some pseudos in move_unallocated_pseudos
Kewen Lin [Mon, 11 Jan 2021 02:33:23 +0000 (20:33 -0600)]
ira: Skip some pseudos in move_unallocated_pseudos

This patch is to make move_unallocated_pseudos consistent
to what we have in function find_moveable_pseudos, where we
record the original pseudo into pseudo_replaced_reg only if
validate_change succeeds with newreg.  To ensure every
unallocated pseudo in move_unallocated_pseudos has expected
information, it's better to add a check and skip it if it's
unexpected.  This avoids possible ICEs in future.

gcc/ChangeLog:

* ira.c (move_unallocated_pseudos): Check other_reg and skip if
it isn't set.

3 years agoDaily bump.
GCC Administrator [Mon, 11 Jan 2021 00:16:17 +0000 (00:16 +0000)]
Daily bump.

3 years agolibstdc++: Suppress more vstring testsuite warnings. [PR 98613]
David Edelsohn [Sun, 10 Jan 2021 23:10:34 +0000 (18:10 -0500)]
libstdc++: Suppress more vstring testsuite warnings. [PR 98613]

    PR c++/57111 - 57111 - Generalize -Wfree-nonheap-object to delete

can create false positive warnings for vstring _S_empty_rep.

This patch prunes the excess false positive warnings from two more
testcases.

libstdc++-v3/ChangeLog:

PR libstdc++/98613
* testsuite/ext/vstring/cons/moveable.cc: Suppress false positive
warning.
* testsuite/ext/vstring/modifiers/assign/move_assign.cc: Same.

3 years agoDaily bump.
GCC Administrator [Sun, 10 Jan 2021 00:16:20 +0000 (00:16 +0000)]
Daily bump.

3 years agod: Synchronize testsuite with upstream dmd
Iain Buclaw [Sat, 9 Jan 2021 22:25:44 +0000 (23:25 +0100)]
d: Synchronize testsuite with upstream dmd

Adds TEST_OUTPUT directives and reduces the verbosity of many tests.

Reviewed-on: https://github.com/dlang/dmd/pull/12112

gcc/d/ChangeLog:

* dmd/MERGE: Merge upstream dmd cb1106ad5.

3 years agod: Support deprecated, @disable, and user-defined attributes on enum members
Iain Buclaw [Thu, 7 Jan 2021 21:00:24 +0000 (22:00 +0100)]
d: Support deprecated, @disable, and user-defined attributes on enum members

Reviewed-on: https://github.com/dlang/dmd/pull/12108

gcc/d/ChangeLog:

* dmd/MERGE: Merge upstream dmd 9bba772fa.

3 years agod: Implement expression-based contract syntax
Iain Buclaw [Thu, 7 Jan 2021 17:30:30 +0000 (18:30 +0100)]
d: Implement expression-based contract syntax

Expression-based contract syntax has been added.  Contracts that consist
of a single assertion can now be written more succinctly and multiple
`in` or `out` contracts can be specified for the same function.

Reviewed-on: https://github.com/dlang/dmd/pull/12106

gcc/d/ChangeLog:

* dmd/MERGE: Merge upstream dmd e598f69c0.

3 years agoVAX/testsuite: Remove notsi comparison elimination regressions
Maciej W. Rozycki [Fri, 8 Jan 2021 12:49:59 +0000 (12:49 +0000)]
VAX/testsuite: Remove notsi comparison elimination regressions

Remove fallout from commit 0bd675183d94 ("match.pd: Add ~(X - Y) -> ~X
+ Y simplification [PR96685]") and paper over the regression caused as
it is not the matter of the test cases affected.

Previously assembly like this:

.text
.align 1
.globl eq_notsi
.type eq_notsi, @function
eq_notsi:
.word 0 # 35 [c=0]  procedure_entry_mask
subl2 $4,%sp # 46 [c=32]  *addsi3
mcoml 4(%ap),%r0 # 32 [c=16]  *one_cmplsi2_ccz
jeql .L1 # 34 [c=26]  *branch_ccz
addl2 $2,%r0 # 31 [c=32]  *addsi3
.L1:
ret # 40 [c=0]  return
.size eq_notsi, .-eq_notsi

was produced.  Now this:

.text
.align 1
.globl eq_notsi
.type eq_notsi, @function
eq_notsi:
.word 0 # 36 [c=0]  procedure_entry_mask
subl2 $4,%sp # 48 [c=32]  *addsi3
movl 4(%ap),%r0 # 33 [c=16]  *movsi_2
cmpl %r0,$-1 # 34 [c=8]  *cmpsi_ccz/1
jeql .L3 # 35 [c=26]  *branch_ccz
subl3 %r0,$1,%r0 # 32 [c=32]  *subsi3/1
ret # 27 [c=0]  return
.L3:
clrl %r0 # 31 [c=2]  *movsi_2
ret # 41 [c=0]  return
.size eq_notsi, .-eq_notsi

is, which cannot work with post-reload comparison elimination, due to
the comparison against -1 rather than 0.

Use subtraction from a constant then rather than addition as the former
operation is not transformed, removing these regressions:

FAIL: gcc.target/vax/cmpelim-eq-notsi.c   -O1   scan-rtl-dump-times cmpelim "deleting insn with uid" 1
FAIL: gcc.target/vax/cmpelim-eq-notsi.c   -O1   scan-assembler-not \t(bit|cmpz?|tst).
FAIL: gcc.target/vax/cmpelim-eq-notsi.c   -O1   scan-assembler one_cmplsi[^ ]*_ccz(/[0-9]+)?\n
FAIL: gcc.target/vax/cmpelim-lt-notsi.c   -O1   scan-rtl-dump-times cmpelim "deleting insn with uid" 1
FAIL: gcc.target/vax/cmpelim-lt-notsi.c   -O1   scan-assembler-not \t(bit|cmpz?|tst).
FAIL: gcc.target/vax/cmpelim-lt-notsi.c   -O1   scan-assembler one_cmplsi[^ ]*_ccn(/[0-9]+)?\n

and likewise across some of the other the optimization levels verified.

The LE variant appears unaffected as the new transformation produces
slightly different although still suboptimal code:

.text
.align 1
.globl le_notsi
.type le_notsi, @function
le_notsi:
.word 0 # 27 [c=0]  procedure_entry_mask
subl2 $4,%sp # 34 [c=32]  *addsi3
movl 4(%ap),%r1 # 23 [c=16]  *movsi_2
mcoml %r1,%r0 # 24 [c=8]  *one_cmplsi2_ccnz
jleq .L1 # 26 [c=26]  *branch_ccnz
subl3 %r1,$1,%r0 # 22 [c=32]  *subsi3/1
.L1:
ret # 32 [c=0]  return
.size le_notsi, .-le_notsi

but update the test case too, for consistency with the other two.

gcc/testsuite/
* gcc.target/vax/cmpelim-eq-notsi.c: Use subtraction from a
constant then rather than addition.
* gcc.target/vax/cmpelim-le-notsi.c: Likewise.
* gcc.target/vax/cmpelim-lt-notsi.c: Likewise.

3 years agoVAX: Remove a duplicate `cc' mode attribute
Maciej W. Rozycki [Fri, 8 Jan 2021 01:51:13 +0000 (01:51 +0000)]
VAX: Remove a duplicate `cc' mode attribute

Remove the `cc' mode attribute that duplicates the implicitly defined
`mode' attribute.  No change to semantics.

gcc/
* config/vax/vax.md (cc): Remove mode attribute.
(subst_<cc>, subst_f<cc>): Rename to...
(subst_<mode>, subst_f<VAXccnz:mode>): ... these respectively.
(*cbranch<VAXint:mode>4_<VAXcc:mode>): Update for `cc' removal.
(*cbranch<VAXfp:mode>4_<VAXccnz:mode>): Likewise.
(*branch_<mode>, *branch_<mode>_reversed): Likewise.

3 years agoVAX: Use a mode with `const_double_zero' expressions
Maciej W. Rozycki [Fri, 8 Jan 2021 01:50:27 +0000 (01:50 +0000)]
VAX: Use a mode with `const_double_zero' expressions

For predictable semantics propagate the mode from operands referred by
the FP substitution to the `const_double_zero' expressions used with the
associated condition code calculation.  Use an iterator to make copies
of the FP substitution across the FP modes supported as the substitution
now has to match the mode of the operands.

gcc/
* config/vax/vax.md (subst_f<cc>): Add mode to operands and
`const_double_zero'.

3 years agoPDP11: Use a mode with `const_double_zero' expressions
Maciej W. Rozycki [Fri, 8 Jan 2021 01:50:20 +0000 (01:50 +0000)]
PDP11: Use a mode with `const_double_zero' expressions

For predictable semantics propagate the mode from operands referred by
FP substitutions to the `const_double_zero' expressions used with the
associated condition code calculation, resulting in the following update
to insn-emit.c code produced for the `pdp11-aout' target (with machine
description line numbering change noise removed):

@@ -1514,7 +1514,7 @@
  gen_rtx_COMPARE (CCmode,
  gen_rtx_ABS (DFmode,
  operand1),
- CONST_DOUBLE_ATOF ("0", VOIDmode))),
+ CONST_DOUBLE_ATOF ("0", DFmode))),
  gen_rtx_SET (operand0,
  gen_rtx_ABS (DFmode,
  copy_rtx (operand1)))));
@@ -1555,7 +1555,7 @@
  gen_rtx_COMPARE (CCmode,
  gen_rtx_NEG (DFmode,
  operand1),
- CONST_DOUBLE_ATOF ("0", VOIDmode))),
+ CONST_DOUBLE_ATOF ("0", DFmode))),
  gen_rtx_SET (operand0,
  gen_rtx_NEG (DFmode,
  copy_rtx (operand1)))));
@@ -1790,7 +1790,7 @@
  gen_rtx_MULT (DFmode,
  operand1,
  operand2),
- CONST_DOUBLE_ATOF ("0", VOIDmode))),
+ CONST_DOUBLE_ATOF ("0", DFmode))),
  gen_rtx_SET (operand0,
  gen_rtx_MULT (DFmode,
  copy_rtx (operand1),
@@ -1942,7 +1942,7 @@
  gen_rtx_DIV (DFmode,
  operand1,
  operand2),
- CONST_DOUBLE_ATOF ("0", VOIDmode))),
+ CONST_DOUBLE_ATOF ("0", DFmode))),
  gen_rtx_SET (operand0,
  gen_rtx_DIV (DFmode,
  copy_rtx (operand1),

Provide a new iterator to provide copies of FP substitutions across the
FP modes supported as the substitutions now need to match the mode of
the operands.

gcc/
* config/pdp11/pdp11.md (PDPfp): New mode iterator.
(fcc_cc, fcc_ccnz): Use it.  Add mode to `const_double_zero' and
operands.

3 years agoRTL: Update `const_double_zero' handling for mode and callable insns
Maciej W. Rozycki [Fri, 8 Jan 2021 01:50:10 +0000 (01:50 +0000)]
RTL: Update `const_double_zero' handling for mode and callable insns

Handle machine mode specification with `const_double_zero' and handle
the rtx with callable code produced from named insns.  Complementing
commit 20ab43b5cad6 ("RTL: Add `const_double_zero' syntactic rtx") and
removing a commit c60d0736dff7 ("PDP11: Use `const_double_zero' to
express double zero constant") build regression observed with the
`pdp11-aout' target:

genemit: Internal error: abort in gen_exp, at genemit.c:202
make[2]: *** [Makefile:2427: s-emit] Error 1

where a:

(const_double 0 [0] 0 [0] 0 [0] 0 [0])

rtx coming from:

(parallel [
        (set (reg:CC 16)
            (compare:CC (abs:DF (match_operand:DF 1 ("general_operand") ("0,0")))
                (const_double 0 [0] 0 [0] 0 [0] 0 [0])))
        (set (match_operand:DF 0 ("nonimmediate_operand") ("=fR,Q"))
            (abs:DF (match_dup 1)))
    ])

and ultimately `(const_double_zero)' referred in a named RTL insn cannot
be interpreted.  Handle the rtx then by supplying the constant 0 double
operand requested, resulting in the following update to insn-emit.c code
produced for the `pdp11-aout' target, relative to before the triggering
commit:

@@ -1514,7 +1514,7 @@ gen_absdf2_cc (rtx operand0 ATTRIBUTE_UN
  gen_rtx_COMPARE (CCmode,
  gen_rtx_ABS (DFmode,
  operand1),
- const0_rtx)),
+ CONST_DOUBLE_ATOF ("0", VOIDmode))),
  gen_rtx_SET (operand0,
  gen_rtx_ABS (DFmode,
  copy_rtx (operand1)))));
@@ -1555,7 +1555,7 @@ gen_negdf2_cc (rtx operand0 ATTRIBUTE_UN
  gen_rtx_COMPARE (CCmode,
  gen_rtx_NEG (DFmode,
  operand1),
- const0_rtx)),
+ CONST_DOUBLE_ATOF ("0", VOIDmode))),
  gen_rtx_SET (operand0,
  gen_rtx_NEG (DFmode,
  copy_rtx (operand1)))));
@@ -1790,7 +1790,7 @@ gen_muldf3_cc (rtx operand0 ATTRIBUTE_UN
  gen_rtx_MULT (DFmode,
  operand1,
  operand2),
- const0_rtx)),
+ CONST_DOUBLE_ATOF ("0", VOIDmode))),
  gen_rtx_SET (operand0,
  gen_rtx_MULT (DFmode,
  copy_rtx (operand1),
@@ -1942,7 +1942,7 @@ gen_divdf3_cc (rtx operand0 ATTRIBUTE_UN
  gen_rtx_DIV (DFmode,
  operand1,
  operand2),
- const0_rtx)),
+ CONST_DOUBLE_ATOF ("0", VOIDmode))),
  gen_rtx_SET (operand0,
  gen_rtx_DIV (DFmode,
  copy_rtx (operand1),

This does not (yet) remove VOIDmode CONST_DOUBLE use, as it is up to
individual machine descriptions to choose.

gcc/
* genemit.c (gen_exp) <CONST_DOUBLE>: Handle `const_double_zero'
rtx.
* read-rtl.c (rtx_reader::read_rtx_code): Handle machine mode
with `const_double_zero'.
* doc/rtl.texi (Constant Expression Types): Document it.

3 years agotree-cfg: Allow enum types as result of POINTER_DIFF_EXPR [PR98556]
Jakub Jelinek [Sat, 9 Jan 2021 09:49:38 +0000 (10:49 +0100)]
tree-cfg: Allow enum types as result of POINTER_DIFF_EXPR [PR98556]

As conversions between signed integers and signed enums with the same
precision are useless in GIMPLE, it seems strange that we require that
POINTER_DIFF_EXPR result must be INTEGER_TYPE.

If we really wanted to require that, we'd need to change the gimplifier
to ensure that, which it isn't the case on the following testcase.
What is going on during the gimplification is that when we have the
(enum T) (p - q) cast, it is stripped through
      /* Strip away as many useless type conversions as possible
         at the toplevel.  */
      STRIP_USELESS_TYPE_CONVERSION (*expr_p);
and when the MODIFY_EXPR is gimplified, the *to_p has enum T type,
while *from_p has intptr_t type and as there is no conversion in between,
we just create GIMPLE_ASSIGN from that.

2021-01-09  Jakub Jelinek  <jakub@redhat.com>

PR c++/98556
* tree-cfg.c (verify_gimple_assign_binary): Allow lhs of
POINTER_DIFF_EXPR to be any integral type.

* c-c++-common/pr98556.c: New test.

3 years agovregs: Fix up instantiate_virtual_regs_in_insn for asm goto with outputs [PR98603]
Jakub Jelinek [Sat, 9 Jan 2021 09:48:20 +0000 (10:48 +0100)]
vregs: Fix up instantiate_virtual_regs_in_insn for asm goto with outputs [PR98603]

If an asm insn fails constraint checking during vregs, it is just deleted.
We don't delete asm goto though because of the edges to the labels, so
instantiate_virtual_regs_in_insn would just remove the inputs and their
constraints, the pattern etc.
This worked fine when asm goto couldn't have output operands, but causes
ICEs later on when it has more than one output (and furthermore doesn't
really remove the problematic outputs).  The problem is that
for multiple outputs we have a PARALLEL with multiple ASM_OPERANDS, but
those must use the same ASM_OPERANDS_INPUT_VEC etc., but the code was
adjusting just one.

The following patch turns invalid asm goto into a bare
asm goto ("" : : : : lab, lab2, lab3);
i.e. no inputs/outputs/clobbers, just the labels.

2021-01-09  Jakub Jelinek  <jakub@redhat.com>

PR rtl-optimization/98603
* function.c (instantiate_virtual_regs_in_insn): For asm goto
with impossible constraints, drop all SETs, CLOBBERs, drop PARALLEL
if any, set ASM_OPERANDS mode to VOIDmode and change
ASM_OPERANDS_OUTPUT_CONSTRAINT and ASM_OPERANDS_OUTPUT_IDX.

* gcc.target/i386/pr98603.c: New test.
* gcc.target/aarch64/pr98603.c: New test.

3 years agofinal: accept markers at line 0
Alexandre Oliva [Fri, 1 Jan 2021 00:37:24 +0000 (21:37 -0300)]
final: accept markers at line 0

Back when I introduced debug markers, I seem to have been under the
impression that location line 0 would only ever occur for unknown and
builtin locations.

Though line 0 never comes up in normal processing of source files, and
debug info formats often cannot represent them, I suppose there's no
need to preemptively discard them during final.

for  gcc/ChangeLog

PR debug/97714
* final.c (notice_source_line): Narrow down the condition to
skip a line-0 marker.

for  gcc/testsuite/ChangeLog

PR debug/97714
* gcc.dg/debug/pr97714.c: New.

3 years agoDaily bump.
GCC Administrator [Sat, 9 Jan 2021 00:16:22 +0000 (00:16 +0000)]
Daily bump.

3 years agoipa-modref: avoid linebreak split in debug print
Sergei Trofimovich [Thu, 7 Jan 2021 23:00:46 +0000 (23:00 +0000)]
ipa-modref: avoid linebreak split in debug print

* ipa-modref.c (merge_call_side_effects): Fix
linebreak split by reordering two print calls.

3 years agoIBM Z: Fix constraints in vpdi patterns
Ilya Leoshkevich [Fri, 8 Jan 2021 13:01:20 +0000 (14:01 +0100)]
IBM Z: Fix constraints in vpdi patterns

The destination register is only partially overwritten, so + should be
used instead of =.

gcc/ChangeLog:

2021-01-08  Ilya Leoshkevich  <iii@linux.ibm.com>

* config/s390/vector.md (*tf_to_fprx2_0): Rename from
"*mov_tf_to_fprx2_0" for consistency, fix constraint.
(*tf_to_fprx2_1): Rename from "*mov_tf_to_fprx2_1" for
consistency, fix constraint.

3 years agox86-64: Require lp64 for PR target/98482 tests
H.J. Lu [Fri, 8 Jan 2021 16:41:38 +0000 (08:41 -0800)]
x86-64: Require lp64 for PR target/98482 tests

Require lp64 for PR target/98482 tests since -mcmodel=large is isn't
supported for x32.

PR target/98482
* gcc.target/i386/pr98482-1.c: Require lp64.
* gcc.target/i386/pr98482-2.c: Likewise.

3 years agoIBM Z: Introduce __LONG_DOUBLE_VX__ macro
Ilya Leoshkevich [Mon, 14 Dec 2020 13:05:28 +0000 (14:05 +0100)]
IBM Z: Introduce __LONG_DOUBLE_VX__ macro

Give end users the opportunity to find out whether long doubles are
stored in floating-point register pairs or in vector registers, so that
they could fine-tune their asm statements.

gcc/ChangeLog:

2020-12-14  Ilya Leoshkevich  <iii@linux.ibm.com>

* config/s390/s390-c.c (s390_def_or_undef_macro): Accept
callables instead of mask values.
(struct target_flag_set_p): New predicate.
(s390_cpu_cpp_builtins_internal): Define or undefine
__LONG_DOUBLE_VX__ macro.

2020-12-14  Ilya Leoshkevich  <iii@linux.ibm.com>

gcc/testsuite/ChangeLog:

* gcc.target/s390/vector/long-double-vx-macro-off-on.c: New test.
* gcc.target/s390/vector/long-double-vx-macro-on-off.c: New test.

3 years agoTweak dg-prune-output regex for out-of-build-tree contexts
Olivier Hainque [Fri, 18 Dec 2020 18:09:21 +0000 (18:09 +0000)]
Tweak dg-prune-output regex for out-of-build-tree contexts

libstdc++-v3/

* testsuite/20_util/bind/ref_neg.cc: Tweak the
dg-prune-output regex for out-of-build-tree contexts.

3 years agoc++: ICE with constexpr call that returns a PMF [PR98551]
Patrick Palka [Fri, 8 Jan 2021 15:11:25 +0000 (10:11 -0500)]
c++: ICE with constexpr call that returns a PMF [PR98551]

We shouldn't do replace_result_decl after evaluating a call that returns
a PMF because PMF temporaries aren't wrapped in a TARGET_EXPR (and so we
can't trust ctx->object), and PMF initializers can't be self-referential
anyway, so replace_result_decl would always be a no-op.

To that end, this patch changes the relevant AGGREGATE_TYPE_P test to
CLASS_TYPE_P, which should rule out PMFs (as well as arrays, which we
can't return and therefore won't see here).  This fixes an ICE from the
sanity check in replace_result_decl in the below testcase during
constexpr evaluation of the call f() in the initializer g(f()).

gcc/cp/ChangeLog:

PR c++/98551
* constexpr.c (cxx_eval_call_expression): Check CLASS_TYPE_P
instead of AGGREGATE_TYPE_P before calling replace_result_decl.

gcc/testsuite/ChangeLog:

PR c++/98551
* g++.dg/cpp0x/constexpr-pmf2.C: New test.

3 years agoc++: Fix access checking of scoped non-static member [PR98515]
Patrick Palka [Fri, 8 Jan 2021 15:02:04 +0000 (10:02 -0500)]
c++: Fix access checking of scoped non-static member [PR98515]

In the first testcase below, we incorrectly reject the use of the
protected non-static member A::var0 from C<int>::g() because
check_accessibility_of_qualified_id, at template parse time, determines
that the access doesn't go through 'this'.  (This happens because the
dependent base B<T> of C<T> doesn't have a binfo object, so it appears
to DERIVED_FROM_P that A is not an indirect base of C<T>.)  From there
we create the corresponding deferred access check, which we then
perform at instantiation time and which (expectedly) fails.

The problem ultimately seems to be that we can't in general determine
whether a use of a scoped non-static member goes through 'this' until
instantiation time, as the second testcase below illustrates.  So this
patch makes check_accessibility_of_qualified_id punt in such situations
to avoid creating a bogus deferred access check.

gcc/cp/ChangeLog:

PR c++/98515
* semantics.c (check_accessibility_of_qualified_id): Punt if
we're checking access of a scoped non-static member inside a
class template.

gcc/testsuite/ChangeLog:

PR c++/98515
* g++.dg/template/access32.C: New test.
* g++.dg/template/access33.C: New test.

3 years agox86-64: Use R10 and R11 for profiling large model with PIC
H.J. Lu [Fri, 8 Jan 2021 13:20:19 +0000 (05:20 -0800)]
x86-64: Use R10 and R11 for profiling large model with PIC

For NO_PROFILE_COUNTERS targets, R11 is a scratch register.  We can use
R10 and R11 to call mcount in large model with PIC.

gcc/

PR target/98482
* config/i386/i386.c (x86_function_profiler): Use R10 and R11
to call mcount in large model with PIC for NO_PROFILE_COUNTERS
targets.

gcc/testsuite/

PR target/98482
* gcc.target/i386/pr98482-2.c: Updated.

3 years agoreset the SCEV htab after FRE in loop pipeline
Richard Biener [Fri, 8 Jan 2021 13:37:09 +0000 (14:37 +0100)]
reset the SCEV htab after FRE in loop pipeline

When running FRE in the loop pipeline (as part of the conditionally
scheduled scalar cleanups) we have to reset the SCEV hashtable as
otherwise we can end up with stale entries and all sorts of problems.

Catched by my out-of-tree verifier for this problem.

2021-01-08  Richard Biener  <rguenther@suse.de>

* tree-ssa-sccvn.c (pass_fre::execute): Reset the SCEV hash table.

3 years agofix vectorizer memleaks
Richard Biener [Fri, 8 Jan 2021 13:22:00 +0000 (14:22 +0100)]
fix vectorizer memleaks

This plugs two memleaks in the vectorizer.

2021-01-08  Richard Biener  <rguenther@suse.de>

* tree-vect-slp.c (scalar_stmts_to_slp_tree_map_t): Fix.
(vect_build_slp_tree): On cache hit release the matched
scalar stmts vector.
* tree-vect-stmts.c (vectorizable_store): Properly free
vec_oprnds before possibly gathering them again.

3 years agotree-optimization/98544 - more permute optimization fixes
Richard Biener [Fri, 8 Jan 2021 12:17:18 +0000 (13:17 +0100)]
tree-optimization/98544 - more permute optimization fixes

Permute nodes are not transparent to the permute of their children.
Instead we have to materialize child permutes always and in future
may treat permute nodes as the source of arbitrary permutes as
we can permute the lane permutation vector at will (as the target
supports in the end).

2021-01-08  Richard Biener  <rguenther@suse.de>

PR tree-optimization/98544
* tree-vect-slp.c (vect_optimize_slp): Always materialize
permutes at a permute node.

* gcc.dg/vect/bb-slp-pr98544.c: New testcase.

3 years agox86-64: Use R10 for profiling large model
H.J. Lu [Thu, 7 Jan 2021 22:27:49 +0000 (14:27 -0800)]
x86-64: Use R10 for profiling large model

R10 is caller-saved.  Although it can be used as a static chain register,
it is preserved when calling mcount for nested functions.  Use R10 as a
scratch register to call mcount in large model.

gcc/

PR target/98482
* config/i386/i386.c (x86_function_profiler): Use R10 to call
mcount in large model.  Sorry for large model with PIC.

gcc/testsuite/

PR target/98482
* gcc.target/i386/pr98482-1.c: New test.
* gcc.target/i386/pr98482-1.c: Likewise.

3 years agoi386: Fix -mcmodel= vs. target attribute [PR98585]
Jakub Jelinek [Fri, 8 Jan 2021 11:28:25 +0000 (12:28 +0100)]
i386: Fix -mcmodel= vs. target attribute [PR98585]

My patch to save/restore opts_set rather than essentially treating
global_options_set as a logical or whether some option has ever been
explicitly set somewhere apparently broke -mcmodel= vs. target attribute
(and as the patch shows some other options too).
The thing is, at least for options for which we ever test opts_set->x_*
or global_options_set.x_*, we need to save/restore them next to the
saving/restoring of the actual option values.
If an option has Save keyword or in case of TargetVariable, it is the
generic code that handles the saving and restoring of both the option
and corresponding opts_set flag automatically, for other variables
(TargetSave, or Target without Save) the backend needs to do that in the
target hook manually and in that case should save/restore both the option
values (the hooks mostly did that) and opts_set (they didn't).

As it seems much easier to let the automatic saving/restoring do the work
for us unless the saving/restoring of the option needs some specific magic,
the following patch is a result of grepping through the backend for
opts_set->x_ and global_options_set.x_ and for all such referenced
variables, grepping whether it is saved/restored including opts_set properly
in the generated options-save.c or not.

2021-01-08  Jakub Jelinek  <jakub@redhat.com>

PR target/98585
* config/i386/i386.opt (ix86_cmodel, ix86_incoming_stack_boundary_arg,
ix86_pmode, ix86_preferred_stack_boundary_arg, ix86_regparm,
ix86_veclibabi_type): Remove x_ prefix, use TargetVariable instead of
TargetSave and initialize for variables with enum types.
(mfentry, mstack-protector-guard-reg=, mstack-protector-guard-offset=,
mstack-protector-guard-symbol=): Add Save.
* config/i386/i386-options.c (ix86_function_specific_save,
ix86_function_specific_restore): Don't save or restore x_ix86_cmodel,
x_ix86_incoming_stack_boundary_arg, x_ix86_pmode,
x_ix86_preferred_stack_boundary_arg, x_ix86_regparm,
x_ix86_veclibabi_type.

* gcc.target/i386/pr98585.c: New test.

3 years agoaarch64: Support unpacked CNOT on SVE
Richard Sandiford [Fri, 8 Jan 2021 10:49:38 +0000 (10:49 +0000)]
aarch64: Support unpacked CNOT on SVE

This patch adds unpacked support for unconditional and
conditional CNOT.  The type suffix has to be taken from
the element size rather than the container size.

gcc/
* config/aarch64/aarch64-sve.md (*cnot<mode>): Extend from
SVE_FULL_I to SVE_I.
(*cond_cnot<mode>_2, *cond_cnot<mode>_any): Likewise.

gcc/testsuite/
* gcc.target/aarch64/sve/cnot_2.c: New test.
* gcc.target/aarch64/sve/cond_cnot_4.c: Likewise.
* gcc.target/aarch64/sve/cond_cnot_4_run.c: Likewise.
* gcc.target/aarch64/sve/cond_cnot_5.c: Likewise.
* gcc.target/aarch64/sve/cond_cnot_5_run.c: Likewise.
* gcc.target/aarch64/sve/cond_cnot_6.c: Likewise.
* gcc.target/aarch64/sve/cond_cnot_6_run.c: Likewise.

3 years agoaarch64: Support conditional unpacked UXT on SVE
Richard Sandiford [Fri, 8 Jan 2021 10:49:37 +0000 (10:49 +0000)]
aarch64: Support conditional unpacked UXT on SVE

This patch extends the conditional UXT patterns from SVE_FULL_I
to SVE_I.  It doesn't matter in this case whether the type suffix
is taken from the element size or the container size.

gcc/
* config/aarch64/aarch64-sve.md (*cond_uxt<mode>_2): Extend from
SVE_FULL_I to SVE_I.
(*cond_uxt<mode>_any): Likewise.

gcc/testsuite/
* gcc.target/aarch64/sve/cond_uxt_5.c: New test.
* gcc.target/aarch64/sve/cond_uxt_5_run.c: Likewise.
* gcc.target/aarch64/sve/cond_uxt_6.c: Likewise.
* gcc.target/aarch64/sve/cond_uxt_6_run.c: Likewise.
* gcc.target/aarch64/sve/cond_uxt_7.c: Likewise.
* gcc.target/aarch64/sve/cond_uxt_7_run.c: Likewise.
* gcc.target/aarch64/sve/cond_uxt_8.c: Likewise.
* gcc.target/aarch64/sve/cond_uxt_8_run.c: Likewise.

3 years agoSVE2: Fix aarch64-sve2-acle-asm tests.
Tamar Christina [Fri, 8 Jan 2021 10:44:22 +0000 (10:44 +0000)]
SVE2: Fix aarch64-sve2-acle-asm tests.

This fixes a logical inconsistency with the SVE2 ACLE tests where the SVE2 tests
are checking for SVE support in the assembler instead of SVE2.

This makes all these tests fail when the user has an SVE enabled assembler but
not an SVE2 one.

gcc/testsuite/ChangeLog:

* lib/target-supports.exp
(check_effective_target_aarch64_asm_sve2_ok): New.
* g++.target/aarch64/sve2/acle/aarch64-sve2-acle-asm.exp: Use it.
* gcc.target/aarch64/sve2/acle/aarch64-sve2-acle-asm.exp: Likewise.

3 years agoaarch64: Reimplement most vpadal intrinsics using builtins
Kyrylo Tkachov [Thu, 7 Jan 2021 16:03:08 +0000 (16:03 +0000)]
aarch64: Reimplement most vpadal intrinsics using builtins

This patch reimplements most of the vpadal intrinsics to use RTL
builtins in the normal way.
The ones that aren't converted are the int32x2_t -> int64x1_t ones as
the RTL pattern doesn't currently handle
these modes. We don't have a V1DI mode so it would need to return a
DImode value or a V2DI one with the first lane
being the result. It's not hard to do, but it would require a bit more
refactoring so we can do it separately later.

This patch hopefully improves the status quo.

The new Vwhalf mode attribute is created because the existing Vwtype
attribute maps V8QI wrongly (for this pattern) to "8h" as the
suffix rather than "4h" as needed.

gcc/
* config/aarch64/iterators.md (Vwhalf): New iterator.
* config/aarch64/aarch64-simd.md (aarch64_<sur>adalp<mode>_3):
Rename to...
(aarch64_<sur>adalp<mode>): ... This.  Make more
builtin-friendly.
(<sur>sadv16qi): Adjust callsite of the above.
* config/aarch64/aarch64-simd-builtins.def (sadalp, uadalp): New
builtins.
* config/aarch64/arm_neon.h (vpadal_s8): Reimplement using
builtins.
(vpadal_s16): Likewise.
(vpadal_u8): Likewise.
(vpadal_u16): Likewise.
(vpadalq_s8): Likewise.
(vpadalq_s16): Likewise.
(vpadalq_s32): Likewise.
(vpadalq_u8): Likewise.
(vpadalq_u16): Likewise.
(vpadalq_u32): Likewise.

3 years agoaarch64: Reimplement vabd* intrinsics using builtins
Kyrylo Tkachov [Thu, 7 Jan 2021 15:09:43 +0000 (15:09 +0000)]
aarch64: Reimplement vabd* intrinsics using builtins

This patch reimplements the vabd* intrinsics using RTL builtins.
It's fairly straightforward with new builtins + arm_neon.h changes.

gcc/
* config/aarch64/aarch64-simd.md (aarch64_<su>abd<mode>_3):
Rename to...
(aarch64_<su>abd<mode>): ... This.
(<sur>sadv16qi): Adjust callsite of the above.
* config/aarch64/aarch64-simd-builtins.def (sabd, uabd): Define
builtins.
* config/aarch64/arm_neon.h (vabd_s8): Reimplement using
builtin.
(vabd_s16): Likewise.
(vabd_s32): Likewise.
(vabd_u8): Likewise.
(vabd_u16): Likewise.
(vabd_u32): Likewise.
(vabdq_s8): Likewise.
(vabdq_s16): Likewise.
(vabdq_s32): Likewise.
(vabdq_u8): Likewise.
(vabdq_u16): Likewise.
(vabdq_u32): Likewise.

3 years agoaarch64: Reimplement vaba* intrinsics using builtins
Kyrylo Tkachov [Thu, 7 Jan 2021 14:49:08 +0000 (14:49 +0000)]
aarch64: Reimplement vaba* intrinsics using builtins

This patch reimplements the vaba* arm_neon.h intrinsics using RTL
builtins that expand to proper RTL patterns
rather than using inline asm.
The implementation is fairly straightforward by defining new builtins
and using them in the header.

gcc/
* config/aarch64/aarch64-simd-builtins.def (saba, uaba): Define
builtins.
* config/aarch64/arm_neon.h (vaba_s8): Implement using builtin.
(vaba_s16): Likewise.
(vaba_s32): Likewise.
(vaba_u8): Likewise.
(vaba_u16): Likewise.
(vaba_u32): Likewise.
(vabaq_s8): Likewise.
(vabaq_s16): Likewise.
(vabaq_s32): Likewise.
(vabaq_u8): Likewise.
(vabaq_u16): Likewise.
(vabaq_u32): Likewise.

3 years agoaarch64: Fix RTL patterns for UABA/SABA
Kyrylo Tkachov [Thu, 7 Jan 2021 14:02:02 +0000 (14:02 +0000)]
aarch64: Fix RTL patterns for UABA/SABA

Sometime ago we changed the RTL representation of the (SU)ABD
instructions in RTL to a (MINUS (MAX) (MIN)) rather than a (MINUS (ABS) (ABS))
as it is more correctly models the semantics.
We should do the same for the accumulation forms of these instructions:
UABA/SABA.

This patch does that and allows the new pattern to generate the unsigned
UABA form as well.
The new form also allows it to more easily be re-used to implement the
relevant arm_neon.h intrinsics in the future.

The testcase takes an -fno-tree-reassoc to work around a side-effect of
PR98581.

gcc/
* config/aarch64/aarch64-simd.md (aba<mode>_3): Rename to...
(aarch64_<su>aba<mode>): ... This.  Handle uaba as well.
Change RTL pattern to match.

gcc/testsuite/
* gcc.target/aarch64/usaba_1.c: New test.

3 years agoFortran: Allow pointer deferred length associate selectors. [PR93794]
Paul Thomas [Fri, 8 Jan 2021 10:15:22 +0000 (10:15 +0000)]
Fortran: Allow pointer deferred length associate selectors. [PR93794]

2021-01-05  Paul Thomas  <pault@gcc.gnu.org>

gcc/fortran
PR fortran/93794
* trans-expr.c (gfc_conv_component_ref): Remove the condition
that deferred character length components only be allocatable.

gcc/testsuite/
PR fortran/93794
* gfortran.dg/deferred_character_35.f90 : New test.

3 years agoFortran:Fix simplification of constructors with implied-do [PR98458]
Paul Thomas [Fri, 8 Jan 2021 10:11:00 +0000 (10:11 +0000)]
Fortran:Fix simplification of constructors with implied-do [PR98458]

2021-01-08  Paul Thomas  <pault@gcc.gnu.org>

gcc/fortran
PR fortran/98458
* simplify.c (is_constant_array_expr): If an array constructor
expression has elements other than constants or structures, try
fixing the expression with gfc_reduce_init_expr. Also, if shape
is NULL, obtain the array size and set it.

gcc/testsuite/
PR fortran/98458
* gfortran.dg/implied_do_3.f90 : New test.

3 years agoFix array-quals-1.c for RISC-V
Kito Cheng [Mon, 4 Jan 2021 09:14:48 +0000 (17:14 +0800)]
Fix array-quals-1.c for RISC-V

RISC-V will put those variable on srodata rather than rodata.

gcc/testsuite/ChangeLog:

* gcc.dg/array-quals-1.c: Allow srodata.

3 years agoRISC-V: Implement new style of architecture extension test macros.
Kito Cheng [Fri, 11 Dec 2020 08:51:40 +0000 (16:51 +0800)]
RISC-V: Implement new style of architecture extension test macros.

- This patch introduce new set of architecture extension test macros
  which is accept on riscv-c-api-doc recently.
  - https://github.com/riscv/riscv-c-api-doc/blob/master/riscv-c-api.md#architecture-extension-test-macro

- We will also mark deprecated for legacy architecture extension test macros
  in GCC 11, but still support that for 1 or 2 release cycles.

gcc/ChangeLog:

* common/config/riscv/riscv-common.c (riscv_current_subset_list): New.
* config/riscv/riscv-c.c (riscv-subset.h): New.
(INCLUDE_STRING): Define.
(riscv_cpu_cpp_builtins): Add new style architecture extension
test macros.
* config/riscv/riscv-subset.h (riscv_subset_list::begin): New.
(riscv_subset_list::end): New.
(riscv_current_subset_list): New.

gcc/testsuite/ChangeLog:

* gcc.target/riscv/predef-10.c: New.
* gcc.target/riscv/predef-11.c: New.
* gcc.target/riscv/predef-12.c: New.
* gcc.target/riscv/predef-13.c: New.

3 years agoRISC-V: Move class riscv_subset_list and riscv_subset_t to riscv-protos.h
Kito Cheng [Tue, 29 Dec 2020 08:15:19 +0000 (16:15 +0800)]
RISC-V: Move class riscv_subset_list and riscv_subset_t to riscv-protos.h

Pre-work of new style of architecture extension test macros, we need the
list used in `config/riscv/riscv-c.c`, so those struct/class declaration
must move to header file rather than local C file.

gcc/ChangeLog

* common/config/riscv/riscv-common.c (RISCV_DONT_CARE_VERSION):
Move to riscv-subset.h.
(struct riscv_subset_t): Ditto.
(class riscv_subset_list): Ditto.
* config/riscv/riscv-subset.h (RISCV_DONT_CARE_VERSION): Move
from riscv-common.c.
(struct riscv_subset_t): Ditto.
(class riscv_subset_list): Ditto.
* config/riscv/t-riscv ($(common_out_file)): Add file
dependency.

3 years agoDaily bump.
GCC Administrator [Fri, 8 Jan 2021 00:16:23 +0000 (00:16 +0000)]
Daily bump.

3 years agoc++: Fix up tsubst of BIT_CAST_EXPR [PR98329]
Jakub Jelinek [Thu, 7 Jan 2021 22:00:28 +0000 (23:00 +0100)]
c++: Fix up tsubst of BIT_CAST_EXPR [PR98329]

As the testcase shows, calling cp_build_bit_cast in tsubst_copy doesn't seem
to be a good idea, because tsubst_copy might not really make the operand
non-dependent, but as processing_template_decl can be 0,
type_dependent_expression_p will return false and then cp_build_bit_cast
assumes the type is non-NULL and non-dependent.
So, this patch just follows what is done e.g. for NOP_EXPR etc. and just
builds some tree in tsubst_copy, and only calls the semantics.c function
from tsubst_copy_and_build.

2021-01-07  Jakub Jelinek  <jakub@redhat.com>

PR c++/98329
* pt.c (tsubst_copy) <case BIT_CAST_EXPR>: Don't call
cp_build_bit_cast here, instead just build_min a BIT_CAST_EXPR and set
its location.
(tsubst_copy_and_build): Handle BIT_CAST_EXPR.

* g++.dg/cpp2a/bit-cast10.C: New test.

3 years agoPR middle-end/98578 - ICE warning on uninitialized VLA access
Martin Sebor [Thu, 7 Jan 2021 21:20:39 +0000 (14:20 -0700)]
PR middle-end/98578 - ICE warning on uninitialized VLA access

gcc/c-family/ChangeLog:

PR middle-end/98578
* c-pretty-print.c (print_mem_ref): Strip array from access type.
Avoid assuming acces type's size is constant.  Correct condition
guarding the printing of a parenthesis.

gcc/testsuite/ChangeLog:

PR middle-end/98578
* gcc.dg/plugin/gil-1.c: Adjust expected output.
* gcc.dg/uninit-pr98578.c: New test.

3 years agoc++: Fix thinko in auto return type checking [PR98441]
Marek Polacek [Wed, 6 Jan 2021 00:17:10 +0000 (19:17 -0500)]
c++: Fix thinko in auto return type checking [PR98441]

This fixes a thinko in my r11-2085 patch: when I said "But only give the
!late_return_type errors when funcdecl_p, to accept e.g. auto (*fp)() = f;
in C++11" I should've done this, otherwise we give bogus errors mentioning
"function with trailing return type" when there is none.

gcc/cp/ChangeLog:

PR c++/98441
* decl.c (grokdeclarator): Move the !funcdecl_p check inside the
!late_return_type block.

gcc/testsuite/ChangeLog:

PR c++/98441
* g++.dg/cpp0x/auto55.C: New test.

3 years agoc++: Add TARGET_EXPR comments
Jason Merrill [Mon, 4 Jan 2021 21:11:08 +0000 (16:11 -0500)]
c++: Add TARGET_EXPR comments

Discussing the 98469 patch and class prvalues with Jakub led me to
double-check our handling of TARGET_EXPR in constexpr.c, and add a note
about why we don't strip them in parameter initialization.  And another to
clarify that we're handling an INIT_EXPR in a place we do strip them.

gcc/cp/ChangeLog:

* constexpr.c (cxx_bind_parameters_in_call): Add comment.
(cxx_eval_store_expression): Add comment.

3 years agoc++: Add some conversion sanity checking.
Jason Merrill [Tue, 5 Jan 2021 21:56:44 +0000 (16:56 -0500)]
c++: Add some conversion sanity checking.

Another change I was working on revealed that for complex numbers we were
building a ck_identity with build_conv, leading to the wrong active member
in the union being set.  Rather than add another enumeration of the
appropriate conversion codes, I factored that out.

gcc/cp/ChangeLog:

* call.c (has_next): Factor out from...
(next_conversion): ...here.
(strip_standard_conversion): And here.
(is_subseq): And here.
(build_conv): Check it.
(standard_conversion): Don't call build_conv
for ck_identity.

3 years agolibstdc++: Add support for C++20 barriers
Thomas Rodgers [Thu, 7 Jan 2021 20:07:06 +0000 (12:07 -0800)]
libstdc++: Add support for C++20 barriers

Adds <barrier>

libstdc++-v3/ChangeLog:

* doc/doxygen/user.cfg.in: Add new header.
* include/Makefile.am (std_headers): likewise.
* include/Makefile.in: Regenerate.
* include/precompiled/stdc++.h: Add new header.
* include/std/barrier: New file.
* include/std/version: Add __cpp_lib_barrier feature test macro.
* testsuite/30_threads/barrier/1.cc: New test.
* testsuite/30_threads/barrier/2.cc: Likewise.
* testsuite/30_threads/barrier/arrive_and_drop.cc: Likewise.
* testsuite/30_threads/barrier/arrive_and_wait.cc: Likewise.
* testsuite/30_threads/barrier/arrive.cc: Likewise.
* testsuite/30_threads/barrier/completion.cc: Likewise.

3 years agoanalyzer: fix ICE when DECL_INITIAL is error_mark_node [PR98580]
David Malcolm [Thu, 7 Jan 2021 20:45:29 +0000 (15:45 -0500)]
analyzer: fix ICE when DECL_INITIAL is error_mark_node [PR98580]

lto-streamer-out.c's get_symbol_initial_value can return error_mark_node
rather than DECL_INITIAL as an optimization to avoid extra sections for
simple scalar values.

Add a check to the analyzer to handle such cases gracefully.

gcc/analyzer/ChangeLog:
PR analyzer/98580
* region.cc (decl_region::get_svalue_for_initializer): Gracefully
handle when LTO writes out DECL_INITIAL as error_mark_node.

gcc/testsuite/ChangeLog:
PR analyzer/98580
* gcc.dg/analyzer/pr98580-a.c: New test.
* gcc.dg/analyzer/pr98580-b.c: New test.

3 years agotest: add new Go tests from source repo
Ian Lance Taylor [Thu, 7 Jan 2021 19:02:02 +0000 (11:02 -0800)]
test: add new Go tests from source repo

3 years agoUpdate cpplib es.po.
Joseph Myers [Thu, 7 Jan 2021 17:54:39 +0000 (17:54 +0000)]
Update cpplib es.po.

* es.po: Update.