microwatt.git
5 years agoMerge pull request #73 from antonblanchard/remove-divide-patch
Anton Blanchard [Tue, 24 Sep 2019 23:13:18 +0000 (09:13 +1000)]
Merge pull request #73 from antonblanchard/remove-divide-patch

Remove gcc software divide patch

5 years agoRemove gcc software divide patch
Anton Blanchard [Tue, 24 Sep 2019 22:03:10 +0000 (08:03 +1000)]
Remove gcc software divide patch

We have a divider, thanks to Paul.

Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
5 years agoMerge pull request #72 from antonblanchard/build-error
Anton Blanchard [Tue, 24 Sep 2019 10:54:28 +0000 (20:54 +1000)]
Merge pull request #72 from antonblanchard/build-error

Fix build issue in dmi_dtm_dummy.vhdl

5 years agoMerge pull request #71 from antonblanchard/dependencies
Anton Blanchard [Tue, 24 Sep 2019 10:34:52 +0000 (20:34 +1000)]
Merge pull request #71 from antonblanchard/dependencies

Update Makefile dependencies

5 years agoFix build issue in dmi_dtm_dummy.vhdl
Anton Blanchard [Tue, 24 Sep 2019 10:27:34 +0000 (20:27 +1000)]
Fix build issue in dmi_dtm_dummy.vhdl

Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
5 years agoUpdate Makefile dependencies
Anton Blanchard [Tue, 24 Sep 2019 07:50:17 +0000 (17:50 +1000)]
Update Makefile dependencies

Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
5 years agoMerge branch 'divider' of https://github.com/paulusmack/microwatt
Anton Blanchard [Tue, 24 Sep 2019 07:33:21 +0000 (17:33 +1000)]
Merge branch 'divider' of https://github.com/paulusmack/microwatt

5 years agoMerge pull request #70 from antonblanchard/badly-named-carry
Anton Blanchard [Tue, 24 Sep 2019 07:25:44 +0000 (17:25 +1000)]
Merge pull request #70 from antonblanchard/badly-named-carry

Rename OP_SUBFC -> OP_SUBFE, OP_ADDC -> OP_ADDE

5 years agoRename OP_SUBFC -> OP_SUBFE, OP_ADDC -> OP_ADDE
Anton Blanchard [Tue, 24 Sep 2019 06:55:09 +0000 (16:55 +1000)]
Rename OP_SUBFC -> OP_SUBFE, OP_ADDC -> OP_ADDE

These were somewhat badly named.

Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
5 years agoMerge pull request #69 from antonblanchard/debug-module
Anton Blanchard [Tue, 24 Sep 2019 06:51:03 +0000 (16:51 +1000)]
Merge pull request #69 from antonblanchard/debug-module

Merge debug module patches

5 years agoTerminate test on illegal instruction
Anton Blanchard [Mon, 23 Sep 2019 11:22:18 +0000 (21:22 +1000)]
Terminate test on illegal instruction

This gets the CI going again, but we will want to fix the test
harness since it's useful to be able to debug the core after it
executes an illegal instruction.

Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
5 years agoFix ghdl error
Anton Blanchard [Mon, 23 Sep 2019 11:20:12 +0000 (21:20 +1000)]
Fix ghdl error

I'm seeing an issue on my version of ghdl:

  core.vhdl:137:24:error: actual expression must be globally static

Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
5 years agoAdd core_debug.vhdl to fusesoc configs
Anton Blanchard [Mon, 23 Sep 2019 10:49:21 +0000 (20:49 +1000)]
Add core_debug.vhdl to fusesoc configs

Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
5 years agoSpeed up the divider a little
Paul Mackerras [Mon, 23 Sep 2019 04:39:50 +0000 (14:39 +1000)]
Speed up the divider a little

This looks for cases where the next 8 bits of the quotient are obviously
going to be zero, because the top 72 bits of the 128-bit dividend
register are all zero.  In those cases we shift 8 zero bits into the
quotient and increase count by 8.  We only do this if count < 56.

Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
5 years agoAdd a divider unit and a testbench for it
Paul Mackerras [Sun, 22 Sep 2019 07:24:14 +0000 (17:24 +1000)]
Add a divider unit and a testbench for it

This adds a divider unit, connected to the core in much the same way
that the multiplier unit is connected.  The division algorithm is
very simple-minded, taking 64 clock cycles for any division (even
32-bit division instructions).

The decoding is simplified by making use of regularities in the
instruction encoding for div* and mod* instructions.  Instead of
having PPC_* encodings from the first-stage decoder for each of the
different div* and mod* instructions, we now just have PPC_DIV and
PPC_MOD, and the inputs to the divider that indicate what sort of
division operation to do are derived from instruction word bits.

Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
5 years agoAdd distclean to Makefile
Benjamin Herrenschmidt [Fri, 20 Sep 2019 06:45:26 +0000 (16:45 +1000)]
Add distclean to Makefile

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
5 years agoNew C based JTAG debug tool
Benjamin Herrenschmidt [Mon, 16 Sep 2019 15:29:08 +0000 (16:29 +0100)]
New C based JTAG debug tool

This works with both the sim socket and urjtag, and supports the
new core functions, loading a file in memory etc...

The code still needs a lot of cleanup and a help!

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
5 years agoAdd core debug module
Benjamin Herrenschmidt [Tue, 10 Sep 2019 16:43:52 +0000 (17:43 +0100)]
Add core debug module

This module adds some simple core controls:

  reset, stop, start, step

along with icache clear and reading the NIA and core
status bits

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org
5 years agoAdd jtag support in simulation via a socket
Benjamin Herrenschmidt [Mon, 16 Sep 2019 15:28:48 +0000 (16:28 +0100)]
Add jtag support in simulation via a socket

This adds a local socket that can be used to communicate with
the debug tool (which will be committed separately) and generates
the JTAG signals.

We generate the low level JTAG signals, thus directly driving the
simulated BSCANE2, and the Xilinx DTM

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
5 years agoAdd DMI address decoder
Benjamin Herrenschmidt [Tue, 10 Sep 2019 16:39:59 +0000 (17:39 +0100)]
Add DMI address decoder

And prepare signals for core DMI support

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
5 years agoWishbone debug module
Benjamin Herrenschmidt [Tue, 10 Sep 2019 16:31:25 +0000 (17:31 +0100)]
Wishbone debug module

This adds a debug module off the DMI (debug) bus which can act as a
wishbone master to generate read and write cycles.

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
5 years agoAdd a debug (DMI) bus and a JTAG interface to it on Xilinx FPGAs
Benjamin Herrenschmidt [Tue, 10 Sep 2019 16:17:59 +0000 (17:17 +0100)]
Add a debug (DMI) bus and a JTAG interface to it on Xilinx FPGAs

This adds a simple bus that can be mastered from an external
system via JTAG, which will be used to hookup various debug
modules.

It's loosely based on the RiscV model (hence the DMI name).

The module currently only supports hooking up to a Xilinx BSCANE2
but it shouldn't be too hard to adapt it to support different TAPs
if necessary.

The JTAG protocol proper is not exactly the RiscV one at this point,
though I might still change it.

This comes with some sim variants of Xilinx BSCANE2 and BUFG and a
test bench.

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
5 years agoUse a 3 way WB arbiter and cleanup fpga toplevel
Benjamin Herrenschmidt [Tue, 10 Sep 2019 16:03:37 +0000 (17:03 +0100)]
Use a 3 way WB arbiter and cleanup fpga toplevel

The 3rd master is currently unused, it will host the WB debug module.

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
5 years agoMerge pull request #66 from antonblanchard/reformat-4
Anton Blanchard [Thu, 19 Sep 2019 12:49:41 +0000 (22:49 +1000)]
Merge pull request #66 from antonblanchard/reformat-4

More reformatting

5 years agoReformat crhelpers, and remove some stale code
Anton Blanchard [Thu, 19 Sep 2019 11:53:27 +0000 (21:53 +1000)]
Reformat crhelpers, and remove some stale code

Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
5 years agoReformat helpers
Anton Blanchard [Thu, 19 Sep 2019 11:53:09 +0000 (21:53 +1000)]
Reformat helpers

Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
5 years agoReformat insn_helpers
Anton Blanchard [Thu, 19 Sep 2019 11:52:07 +0000 (21:52 +1000)]
Reformat insn_helpers

Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
5 years agoMerge pull request #65 from antonblanchard/loadstore-opt
Anton Blanchard [Thu, 19 Sep 2019 11:48:22 +0000 (21:48 +1000)]
Merge pull request #65 from antonblanchard/loadstore-opt

A small loadstore optimisation, and some reformatting

5 years agoReformat loadstore1
Anton Blanchard [Thu, 19 Sep 2019 11:37:43 +0000 (21:37 +1000)]
Reformat loadstore1

Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
5 years agoReformat loadstore2
Anton Blanchard [Thu, 19 Sep 2019 11:36:51 +0000 (21:36 +1000)]
Reformat loadstore2

Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
5 years agoloads don't do both byte reversal and sign extension
Anton Blanchard [Thu, 19 Sep 2019 11:31:34 +0000 (21:31 +1000)]
loads don't do both byte reversal and sign extension

Give the synthesis tools a clue that we don't need to do both byte reversal
and sign extension.

Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
5 years agoMerge pull request #64 from antonblanchard/reformat-3
Anton Blanchard [Thu, 19 Sep 2019 11:07:31 +0000 (21:07 +1000)]
Merge pull request #64 from antonblanchard/reformat-3

Reformat some more files

5 years agoMerge pull request #63 from antonblanchard/multiply-cleanup
Anton Blanchard [Thu, 19 Sep 2019 10:36:26 +0000 (20:36 +1000)]
Merge pull request #63 from antonblanchard/multiply-cleanup

Multiply cleanup

5 years agoReformat wishbone code
Anton Blanchard [Thu, 19 Sep 2019 10:35:42 +0000 (20:35 +1000)]
Reformat wishbone code

Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
5 years agoReformat glibc_random
Anton Blanchard [Thu, 19 Sep 2019 10:33:58 +0000 (20:33 +1000)]
Reformat glibc_random

Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
5 years agoReformat simple_ram_behavioural
Anton Blanchard [Thu, 19 Sep 2019 10:32:07 +0000 (20:32 +1000)]
Reformat simple_ram_behavioural

Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
5 years agoReformat sim_console
Anton Blanchard [Thu, 19 Sep 2019 10:28:37 +0000 (20:28 +1000)]
Reformat sim_console

Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
5 years agoReformat multiply_tb
Anton Blanchard [Thu, 19 Sep 2019 10:26:55 +0000 (20:26 +1000)]
Reformat multiply_tb

Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
5 years agoReformat execute2
Anton Blanchard [Thu, 19 Sep 2019 10:24:29 +0000 (20:24 +1000)]
Reformat execute2

Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
5 years agoReformat CR file
Anton Blanchard [Thu, 19 Sep 2019 10:22:36 +0000 (20:22 +1000)]
Reformat CR file

Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
5 years agoReformat register file
Anton Blanchard [Thu, 19 Sep 2019 10:21:58 +0000 (20:21 +1000)]
Reformat register file

Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
5 years agoReformat multiply code
Anton Blanchard [Thu, 19 Sep 2019 10:19:46 +0000 (20:19 +1000)]
Reformat multiply code

Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
5 years agoDon't use VHDL 2008 condition operator in multiply
Anton Blanchard [Thu, 19 Sep 2019 10:18:01 +0000 (20:18 +1000)]
Don't use VHDL 2008 condition operator in multiply

Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
5 years agoMerge pull request #62 from antonblanchard/byte-reverse-store-opt
Anton Blanchard [Mon, 16 Sep 2019 03:17:37 +0000 (13:17 +1000)]
Merge pull request #62 from antonblanchard/byte-reverse-store-opt

Move byte reversal of stores to first cycle

5 years agoMerge pull request #61 from antonblanchard/execute-cleanup
Anton Blanchard [Mon, 16 Sep 2019 03:14:25 +0000 (13:14 +1000)]
Merge pull request #61 from antonblanchard/execute-cleanup

execute1 no longer needs sim_console

5 years agoMove byte reversal of stores to first cycle
Anton Blanchard [Mon, 16 Sep 2019 01:49:44 +0000 (11:49 +1000)]
Move byte reversal of stores to first cycle

We are seeing some timing issues with the second cycle of loadstore,
and  we aren't doing much in the first cycle, so move it here.

Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
5 years agoexecute1 no longer needs sim_console
Anton Blanchard [Mon, 16 Sep 2019 01:18:53 +0000 (11:18 +1000)]
execute1 no longer needs sim_console

Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
5 years agoMerge pull request #60 from antonblanchard/testbenches
Anton Blanchard [Sun, 15 Sep 2019 12:52:14 +0000 (22:52 +1000)]
Merge pull request #60 from antonblanchard/testbenches

Add a few more test benches

5 years agoFix multiply_tb
Anton Blanchard [Fri, 13 Sep 2019 10:35:08 +0000 (20:35 +1000)]
Fix multiply_tb

Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
5 years agoAdd an icache testbench
Anton Blanchard [Fri, 13 Sep 2019 10:17:17 +0000 (20:17 +1000)]
Add an icache testbench

Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
5 years agoMerge pull request #56 from antonblanchard/writeback-fix3
Anton Blanchard [Sun, 15 Sep 2019 12:08:57 +0000 (22:08 +1000)]
Merge pull request #56 from antonblanchard/writeback-fix3

Remove cycle in writeback

5 years agoRemove cycle in writeback
Anton Blanchard [Sun, 15 Sep 2019 08:03:48 +0000 (18:03 +1000)]
Remove cycle in writeback

The pipeline had a cycle in writeback. Writeback is pretty
simple and unlikely to be a bottleneck, so lets remove it.

Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
5 years agoMerge pull request #59 from antonblanchard/trap-decode
Anton Blanchard [Sun, 15 Sep 2019 11:37:47 +0000 (21:37 +1000)]
Merge pull request #59 from antonblanchard/trap-decode

Fix make check

5 years agoMerge pull request #58 from antonblanchard/decode2-assert
Anton Blanchard [Sun, 15 Sep 2019 11:30:30 +0000 (21:30 +1000)]
Merge pull request #58 from antonblanchard/decode2-assert

Fix spurious outstanding assert

5 years agoFix make check
Anton Blanchard [Sun, 15 Sep 2019 11:21:36 +0000 (21:21 +1000)]
Fix make check

We need to finish support for all the trap instructions, but for now
we at least need a decode entry for tw, so we know to stall until the
previous instruction completes. Some of our test cases were failing
because the trap executed before the previous instruction completed.

All these trap instructions need to be resolved at completion, not
in execute.

Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
5 years agoFix spurious outstanding assert
Anton Blanchard [Sun, 15 Sep 2019 08:59:24 +0000 (18:59 +1000)]
Fix spurious outstanding assert

Check it in the sequential process, not the combinatorial one.

Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
5 years agoMerge pull request #57 from antonblanchard/add-nop
Anton Blanchard [Sun, 15 Sep 2019 08:34:27 +0000 (18:34 +1000)]
Merge pull request #57 from antonblanchard/add-nop

Add a decode for the nop instruction

5 years agoAdd a decode for the nop instruction
Anton Blanchard [Sun, 15 Sep 2019 08:18:24 +0000 (18:18 +1000)]
Add a decode for the nop instruction

We want these to go out without any GPR dependencies, so add
a specific entry in decode for them.

Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
5 years agoMerge pull request #55 from antonblanchard/fetch-fix
Anton Blanchard [Sun, 15 Sep 2019 01:18:42 +0000 (11:18 +1000)]
Merge pull request #55 from antonblanchard/fetch-fix

Add a default value for RESET_ADDRESS

5 years agoAdd a default value for RESET_ADDRESS
Anton Blanchard [Sun, 15 Sep 2019 00:25:57 +0000 (10:25 +1000)]
Add a default value for RESET_ADDRESS

Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
5 years agoMerge pull request #51 from antonblanchard/writeback-fix
Anton Blanchard [Sat, 14 Sep 2019 23:55:10 +0000 (09:55 +1000)]
Merge pull request #51 from antonblanchard/writeback-fix

Some writeback updates

5 years agoReformat writeback.vhdl
Anton Blanchard [Sat, 14 Sep 2019 23:07:34 +0000 (09:07 +1000)]
Reformat writeback.vhdl

Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
5 years agoExit if we try to write more than one GPR or CR in a cycle
Anton Blanchard [Sat, 14 Sep 2019 23:04:47 +0000 (09:04 +1000)]
Exit if we try to write more than one GPR or CR in a cycle

Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
5 years agoMerge pull request #50 from antonblanchard/decode1-opt
Anton Blanchard [Thu, 12 Sep 2019 11:15:24 +0000 (21:15 +1000)]
Merge pull request #50 from antonblanchard/decode1-opt

No need to gate nia or insn in decode1

5 years agoNo need to gate nia or insn in decode1
Anton Blanchard [Thu, 12 Sep 2019 07:06:09 +0000 (17:06 +1000)]
No need to gate nia or insn in decode1

Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
5 years agoMerge pull request #49 from antonblanchard/icache-2
Anton Blanchard [Thu, 12 Sep 2019 06:14:28 +0000 (16:14 +1000)]
Merge pull request #49 from antonblanchard/icache-2

Add a simple direct mapped icache

5 years agoAdd a simple direct mapped icache
Anton Blanchard [Wed, 11 Sep 2019 03:05:17 +0000 (13:05 +1000)]
Add a simple direct mapped icache

Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
5 years agoSOC memory wishbone should clear ACK regardless of STB
Anton Blanchard [Wed, 11 Sep 2019 07:21:52 +0000 (17:21 +1000)]
SOC memory wishbone should clear ACK regardless of STB

The memory wishbone doesn't clear ACK and move the state machine on
until STB is de-asserted. This seems like it isn't compliant with
the spec and results in a maximum throughput of 1 transfer every
3 cycles.

Fixing this improves the situation to one transfer every 2 cycles.

Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
5 years agoMerge pull request #48 from antonblanchard/clk_gen_bypass
Anton Blanchard [Thu, 12 Sep 2019 03:03:33 +0000 (13:03 +1000)]
Merge pull request #48 from antonblanchard/clk_gen_bypass

Fix clk_gen_bypass

5 years agoFix clk_gen_bypass
Anton Blanchard [Thu, 12 Sep 2019 02:25:18 +0000 (12:25 +1000)]
Fix clk_gen_bypass

I broke clk_gen_bypass when updating the SOC reset code.

Fixes 03fd06deaf9f ("Rework SOC reset")
Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
5 years agoMerge pull request #47 from antonblanchard/if-fix
Anton Blanchard [Wed, 11 Sep 2019 23:46:22 +0000 (09:46 +1000)]
Merge pull request #47 from antonblanchard/if-fix

Explicitly check against '1' in if statements

5 years agoMerge pull request #46 from antonblanchard/record-fix
Anton Blanchard [Wed, 11 Sep 2019 23:46:01 +0000 (09:46 +1000)]
Merge pull request #46 from antonblanchard/record-fix

Remove names from end record statements

5 years agoExplicitly check against '1' in if statements
Anton Blanchard [Wed, 11 Sep 2019 23:19:31 +0000 (09:19 +1000)]
Explicitly check against '1' in if statements

nvc doesn't like what I think is a VHDL 2008 construct. Lets just
check against '1' explicitly.

Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
5 years agoRemove names from end record statements
Anton Blanchard [Wed, 11 Sep 2019 23:04:02 +0000 (09:04 +1000)]
Remove names from end record statements

These are optional, and vhdlpp from iverilog barfs on them.

Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
5 years agoMerge pull request #45 from antonblanchard/fixes
Anton Blanchard [Wed, 11 Sep 2019 12:53:47 +0000 (22:53 +1000)]
Merge pull request #45 from antonblanchard/fixes

Fix a couple of issues in the recent pipelining merge

5 years agoFix issue in loadstore1
Anton Blanchard [Wed, 11 Sep 2019 12:40:53 +0000 (22:40 +1000)]
Fix issue in loadstore1

We weren't using the register in this stage.

Fixes: 819f8200905f ("Register outputs on loadstore1")
Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
5 years agoFix issue in execute2
Anton Blanchard [Wed, 11 Sep 2019 12:39:30 +0000 (22:39 +1000)]
Fix issue in execute2

We weren't using the register in this stage.

Fixes: c7aa683ba8aa ("Register outputs on execute2")
Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
5 years agoMerge pull request #44 from antonblanchard/nia-remove
Anton Blanchard [Wed, 11 Sep 2019 11:58:01 +0000 (21:58 +1000)]
Merge pull request #44 from antonblanchard/nia-remove

Remove nia from loadstore and multiply

5 years agoRemove nia from loadstore and multiply
Anton Blanchard [Wed, 11 Sep 2019 11:42:37 +0000 (21:42 +1000)]
Remove nia from loadstore and multiply

Neither unit needs the NIA, so remove it.

Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
5 years agoMerge pull request #43 from mikey/trivial
Anton Blanchard [Wed, 11 Sep 2019 11:42:00 +0000 (21:42 +1000)]
Merge pull request #43 from mikey/trivial

Remove FIXME comment

5 years agoRemove FIXME comment
Michael Neuling [Wed, 11 Sep 2019 06:50:57 +0000 (16:50 +1000)]
Remove FIXME comment

This was mistakenly left behind in 4d5abfb430d1 ("Remove dynamic
ranges from code")

Signed-off-by: Michael Neuling <mikey@neuling.org>
5 years agoMerge pull request #41 from mikey/travis
Anton Blanchard [Wed, 11 Sep 2019 06:05:05 +0000 (16:05 +1000)]
Merge pull request #41 from mikey/travis

Allow a full make check on Travis

5 years agoMerge pull request #42 from antonblanchard/fetch-rework-v2
Anton Blanchard [Wed, 11 Sep 2019 06:04:10 +0000 (16:04 +1000)]
Merge pull request #42 from antonblanchard/fetch-rework-v2

Fetch rework

5 years agoReformat core.vhdl
Anton Blanchard [Tue, 10 Sep 2019 21:55:35 +0000 (07:55 +1000)]
Reformat core.vhdl

5 years agoRemove sim console
Anton Blanchard [Tue, 10 Sep 2019 21:16:56 +0000 (07:16 +1000)]
Remove sim console

We can force all existing code to use the UART console
by passing 0 in bit zero of the sim config register.

Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
5 years agoReduce multiply to 2 cycles
Anton Blanchard [Tue, 10 Sep 2019 06:22:58 +0000 (16:22 +1000)]
Reduce multiply to 2 cycles

We want all non load/store ops to take 2 cycles to make
tracking write back easier.

Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
5 years agoRegister outputs on writeback
Anton Blanchard [Tue, 10 Sep 2019 06:04:39 +0000 (16:04 +1000)]
Register outputs on writeback

Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
5 years agoRegister outputs on execute2
Anton Blanchard [Tue, 10 Sep 2019 05:40:20 +0000 (15:40 +1000)]
Register outputs on execute2

Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
5 years agoRegister outputs on loadstore1
Anton Blanchard [Tue, 10 Sep 2019 05:39:50 +0000 (15:39 +1000)]
Register outputs on loadstore1

Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
5 years agoMove debug execute output into decode2
Anton Blanchard [Tue, 10 Sep 2019 05:02:18 +0000 (15:02 +1000)]
Move debug execute output into decode2

This covers all units, and we avoid double printing.

Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
5 years agoRework pipeline, add stall and flush signals
Anton Blanchard [Tue, 3 Sep 2019 23:36:30 +0000 (09:36 +1000)]
Rework pipeline, add stall and flush signals

This adds stall and flush signals to the pipeline.

Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
5 years agoAllow a full make check on Travis
Michael Neuling [Wed, 11 Sep 2019 00:18:19 +0000 (10:18 +1000)]
Allow a full make check on Travis

Some Travis instances allow more CPU time. On these we can perform the
full 'make check'.

This patch allows this longer `make check`. To enable it you need to
go into your Travis configuration and add a TRAVIS_FULL_CHECK
environment variable.

If you don't add this environment, the shorter make check_light is
still run.

Signed-off-by: Michael Neuling <mikey@neuling.org>
5 years agoMerge pull request #40 from antonblanchard/makefile-dependencies
Anton Blanchard [Tue, 10 Sep 2019 21:48:19 +0000 (07:48 +1000)]
Merge pull request #40 from antonblanchard/makefile-dependencies

Update Makefile dependencies

5 years agoUpdate Makefile dependencies
Anton Blanchard [Tue, 10 Sep 2019 21:32:00 +0000 (07:32 +1000)]
Update Makefile dependencies

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
5 years agoSwitch soc to use std_ulogic
Benjamin Herrenschmidt [Tue, 10 Sep 2019 15:59:10 +0000 (16:59 +0100)]
Switch soc to use std_ulogic

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
5 years agoShare soc.vhdl between FPGA and sim
Benjamin Herrenschmidt [Tue, 10 Sep 2019 15:40:11 +0000 (16:40 +0100)]
Share soc.vhdl between FPGA and sim

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
5 years agoPass wishbone record to bram memory module
Benjamin Herrenschmidt [Tue, 10 Sep 2019 15:39:52 +0000 (16:39 +0100)]
Pass wishbone record to bram memory module

(And rename it to mw_soc_memory).

This makes soc.vhdl simpler and provides the same interface as
the simulated memory, which will help when sharing soc.vhdl
with sim later

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
5 years agoRework wishbone slave address decoding
Benjamin Herrenschmidt [Tue, 10 Sep 2019 13:52:23 +0000 (14:52 +0100)]
Rework wishbone slave address decoding

Don't make it synchronous, no latches

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
5 years agoMove wishbone arbiter out of the core
Benjamin Herrenschmidt [Sat, 31 Aug 2019 08:54:58 +0000 (18:54 +1000)]
Move wishbone arbiter out of the core

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
5 years agoRe-indent and reformat soc.vhdl
Benjamin Herrenschmidt [Tue, 10 Sep 2019 12:01:17 +0000 (13:01 +0100)]
Re-indent and reformat soc.vhdl

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>