mesa.git
6 years agoi965/miptree: Use the tiling from the modifier instead of the BO
Jason Ekstrand [Sat, 18 Nov 2017 00:10:54 +0000 (16:10 -0800)]
i965/miptree: Use the tiling from the modifier instead of the BO

This fixes a bug where we were taking the tiling from the BO regardless
of what the modifier said.  When we got images in from Vulkan where it
doesn't set the tiling on the BO, we would treat them as linear even
though the modifier expressly said to treat it as Y-tiled.

Reviewed-by: Daniel Stone <daniels@collabora.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Cc: mesa-stable@lists.freedesktop.org
6 years agoi965/miptree: Add an explicit tiling parameter to create_for_bo
Jason Ekstrand [Sat, 18 Nov 2017 00:10:53 +0000 (16:10 -0800)]
i965/miptree: Add an explicit tiling parameter to create_for_bo

Otherwise, create_for_bo will just grab the tiling from the BO which is
not what we want when using modifiers.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Cc: mesa-stable@lists.freedesktop.org
6 years agoradv: Don't allow 3d or 1d depth/stencil textures.
Bas Nieuwenhuizen [Sun, 21 Jan 2018 22:39:36 +0000 (23:39 +0100)]
radv: Don't allow 3d or 1d depth/stencil textures.

addrlib asserts when that happens, and supporting it is not
required so lets not allow this for now.

It also assert on fmask, but we don't have the number of samples here.

CC: <mesa-stable@lists.freedesktop.org>
Reviewed-by: Dave Airlie <airlied@redhat.com>
6 years agoradv: Init variant entry with memset.
Bas Nieuwenhuizen [Sun, 21 Jan 2018 21:03:02 +0000 (22:03 +0100)]
radv: Init variant entry with memset.

This gets memcpy'd and written driectly, and due to alignment, this
resulted in uninitialized gaps. This makes those gaps go away.

CC: <mesa-stable@lists.freedesktop.org>
Reviewed-by: Dave Airlie <airlied@redhat.com>
6 years agoradv: Fix bufimage failure deallocation.
Bas Nieuwenhuizen [Sun, 21 Jan 2018 21:01:49 +0000 (22:01 +0100)]
radv: Fix bufimage failure deallocation.

The inidividual init parts don't clean up their own stuff on failure.

CC: <mesa-stable@lists.freedesktop.org>
Reviewed-by: Dave Airlie <airlied@redhat.com>
6 years agoradv: Fix fragment resolve init memory allocation failure paths.
Bas Nieuwenhuizen [Sun, 21 Jan 2018 20:59:26 +0000 (21:59 +0100)]
radv: Fix fragment resolve init memory allocation failure paths.

CC: <mesa-stable@lists.freedesktop.org>
Reviewed-by: Dave Airlie <airlied@redhat.com>
6 years agoradv: Fix freeing meta state if the device pipeline cache fails to allocate.
Bas Nieuwenhuizen [Sun, 21 Jan 2018 20:47:31 +0000 (21:47 +0100)]
radv: Fix freeing meta state if the device pipeline cache fails to allocate.

CC: <mesa-stable@lists.freedesktop.org>
Reviewed-by: Dave Airlie <airlied@redhat.com>
6 years agoradv: Fix memory allocation failure path in compute resolve init.
Bas Nieuwenhuizen [Sun, 21 Jan 2018 19:20:50 +0000 (20:20 +0100)]
radv: Fix memory allocation failure path in compute resolve init.

CC: <mesa-stable@lists.freedesktop.org>
Reviewed-by: Dave Airlie <airlied@redhat.com>
6 years agoradv: Fix ordering issue in meta memory allocation failure path.
Bas Nieuwenhuizen [Sun, 21 Jan 2018 19:19:48 +0000 (20:19 +0100)]
radv: Fix ordering issue in meta memory allocation failure path.

CC: <mesa-stable@lists.freedesktop.org>
Reviewed-by: Dave Airlie <airlied@redhat.com>
6 years agoetnaviv: dirty TS state when framebuffer has changed
Lucas Stach [Thu, 11 Jan 2018 10:29:29 +0000 (11:29 +0100)]
etnaviv: dirty TS state when framebuffer has changed

When switching between framebuffers with and without TS, the TS state
needs to be flushed to the command stream even if the derived state
isn't changed.

Fixes: 4ee7c2c2843c ("etnaviv: enable TS, but disable autodisable")
Cc: mesa-stable@lists.freedesktop.org
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>
6 years agobroadcom/vc5: Fix source file name.
Vinson Lee [Sat, 20 Jan 2018 01:19:34 +0000 (01:19 +0000)]
broadcom/vc5: Fix source file name.

Fixes: c9b2cb78972d ("vc5: add missing files to the tarball")
Signed-off-by: Vinson Lee <vlee@freedesktop.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
6 years agobroadcom/vc5: Add missing include paths.
Vinson Lee [Sat, 20 Jan 2018 00:56:12 +0000 (00:56 +0000)]
broadcom/vc5: Add missing include paths.

Fixes: 954a704da305 ("broadcom/vc5: Port the RCL setup to V3D4.1.")
Signed-off-by: Vinson Lee <vlee@freedesktop.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
6 years agomesa: Only require independent blending for GLES 3.2.
Eric Anholt [Fri, 19 Jan 2018 00:24:42 +0000 (16:24 -0800)]
mesa: Only require independent blending for GLES 3.2.

We've been requiring this since GLES 3.0 was introduced, but the GLES 3.2
spec is the one that has "Supporting blending on a per-draw-buffer basis"
in the new features.  V3D 3.3 would require lowering blending to shader
code to implement independent blending.

Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
6 years agoi965: Delete completely bogus comment
Kenneth Graunke [Sat, 20 Jan 2018 09:28:07 +0000 (01:28 -0800)]
i965: Delete completely bogus comment

This hasn't been true in 6+ years, if it was even true then.  Before
we rewrote the compiler and introduced GLSL IR in 2010-2011, i965 used
to have two compiler backends for WM programs, based on Mesa IR.  One
handled flow control and was SIMD8-only, while the other was SIMD16
only and didn't handle flow control.  Or something like that.

Even then, this certainly didn't handle vertex shaders, so "all ...
code generation" is a bit strong.

6 years agoautotools: include meson build files in tarball
Dylan Baker [Wed, 17 Jan 2018 22:13:11 +0000 (14:13 -0800)]
autotools: include meson build files in tarball

This adds the meson.build, meson_options.txt, and a few scripts that are
used exclusively by the meson build.

v2: - Remove accidentally included changes needed to test make dist with
      LLVM > 3.9

Signed-off-by: Dylan Baker <dylan.c.baker@intel.com>
Acked-by: Eric Engestrom <eric@engestrom.ch>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
6 years agoswr/rast: Fix llvm5 behavior
George Kyriazis [Fri, 19 Jan 2018 22:46:56 +0000 (16:46 -0600)]
swr/rast: Fix llvm5 behavior

For some reason llvm5 is picky about accepting a void * type in the
case of building an argument list.

Since we don't care about the type (we ignore the argument for now),
pick another pointer type

Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
6 years agoswr/rast: Enable early rasterization
George Kyriazis [Fri, 19 Jan 2018 21:47:15 +0000 (15:47 -0600)]
swr/rast: Enable early rasterization

Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
6 years agoswr/rast: Implement Early Rasterization optimization
George Kyriazis [Fri, 19 Jan 2018 21:47:14 +0000 (15:47 -0600)]
swr/rast: Implement Early Rasterization optimization

Early Rasterization is an optimization for small triangles.

Scientific workloads often contain very small triangles that has non-zero
area and cannot be trivially rejected as falling between pixel centers,
but does not cover any pixel center. Those triangles can be initially
rasterized as early as in binner and rejected if they cover no pixels The
optimization can be disabled in compilation using KNOB_ENABLE_EARLY_RAST
option in knobs.h

The Early Rast is disabled by default.

Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
6 years agoswr/rast: Enable simd16 vertex shaders
George Kyriazis [Fri, 19 Jan 2018 21:47:13 +0000 (15:47 -0600)]
swr/rast: Enable simd16 vertex shaders

Flip the switch(es) to enable simd16 vertex shaders:

USE_SIMD16_SHADERS and USE_SIMD16_VS

Both have to be enabled at the same time.  Currently, just setting
USE_SIMD16_SHADERS does not work correctly.

Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
6 years agoswr: Support simd16 vertex shaders
George Kyriazis [Fri, 19 Jan 2018 21:47:12 +0000 (15:47 -0600)]
swr: Support simd16 vertex shaders

Supporting simd16 vertex shaders involves packing the output of the
fetch shader appropriately, especially the vertexID buffers that have to
be formatted in one simd16 register, needed by the VS.

As part of this support, we needed to remove the 2nd JitManager, since it
was not accounting for vector width correctly.

USE_SIMD16_SHADERS is also split into two defines.  The additional
one (USE_SIMD16_VS) controls the width of the vertex shader (VS), while
the original one (USE_SIMD16_SHADERS) controls overall front end width.

Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
6 years agoswr/rast: changed jit debug magic number
George Kyriazis [Fri, 19 Jan 2018 21:47:11 +0000 (15:47 -0600)]
swr/rast: changed jit debug magic number

Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
6 years agoswr/rast: Added ICLAMP builder function
George Kyriazis [Fri, 19 Jan 2018 21:47:10 +0000 (15:47 -0600)]
swr/rast: Added ICLAMP builder function

Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
6 years agoswr/rast: Jit debug work
George Kyriazis [Fri, 19 Jan 2018 21:47:09 +0000 (15:47 -0600)]
swr/rast: Jit debug work

Properly validate DLL matches OBJ for jitted function

Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
6 years agoswr/rast: silence generated file warnings
George Kyriazis [Fri, 19 Jan 2018 21:47:08 +0000 (15:47 -0600)]
swr/rast: silence generated file warnings

Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
6 years agoswr/rast: jit shader lib debug work
George Kyriazis [Fri, 19 Jan 2018 21:47:07 +0000 (15:47 -0600)]
swr/rast: jit shader lib debug work

Create shader_lib during build, link with shaders at DLL generation time

Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
6 years agoswr/rast: AVX-512 changes to enable 16-wide VS
George Kyriazis [Fri, 19 Jan 2018 21:47:06 +0000 (15:47 -0600)]
swr/rast: AVX-512 changes to enable 16-wide VS

Add a new define (USE_SIMD16_VS), to denote calling a 16-wide vertex shader.
This is needed because the mesa driver can do 16-wide shaders, but rasty
cannot yet, so we need to distinguish.

Create a new VertexID entry (VertexID16) for the USE_SIMD16_VS case, since
we need to format the vertex id in a way that is digestible by the 16-wide VS

Disabled for now.  To be enabled in a future checkin when driver work
is complete.

Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
6 years agoswr/rast: x86 autogenerated macro work
George Kyriazis [Fri, 19 Jan 2018 21:47:05 +0000 (15:47 -0600)]
swr/rast: x86 autogenerated macro work

Add name argument to x86 autogenerated macros.
Add useful variable names for DCL_inputVec implementation.

Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
6 years agoswr/rast: Shorten some filenames
George Kyriazis [Fri, 19 Jan 2018 21:47:04 +0000 (15:47 -0600)]
swr/rast: Shorten some filenames

in shader and fetch dump files

Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
6 years agoswr/rast: work supporting optimizations in Debug builds.
George Kyriazis [Fri, 19 Jan 2018 21:47:03 +0000 (15:47 -0600)]
swr/rast: work supporting optimizations in Debug builds.

Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
6 years agoswr/rast: Add debugging type support for function types.
George Kyriazis [Fri, 19 Jan 2018 21:47:02 +0000 (15:47 -0600)]
swr/rast: Add debugging type support for function types.

Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
6 years agoswr/rast: Shader debugging work
George Kyriazis [Fri, 19 Jan 2018 21:47:01 +0000 (15:47 -0600)]
swr/rast: Shader debugging work

- Move debug .ll files to JIT_CACHE_DIR
- Don't link against jitter SRGBLut table, add global data to shader that needs it.

Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
6 years agoswr/rast: Debug Symbols work
George Kyriazis [Fri, 19 Jan 2018 21:47:00 +0000 (15:47 -0600)]
swr/rast: Debug Symbols work

Added support for Fetch / Sample / LD functions
Added DLL link to JitCache implementation

Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
6 years agoswr/rast: Initial work for debugging support.
George Kyriazis [Fri, 19 Jan 2018 21:46:59 +0000 (15:46 -0600)]
swr/rast: Initial work for debugging support.

Adds ability to step into jitted llvm IR in Visual Studio.
- Updated llvm type generation script to also generate corresponding debug types.
- New module pass inserts debug metadata into the IR for each function

Disabled by default.

Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
6 years agoswr/rast: Add private state parameter in fetcher
George Kyriazis [Fri, 19 Jan 2018 21:46:58 +0000 (15:46 -0600)]
swr/rast: Add private state parameter in fetcher

Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
6 years agoswr/rast: Added missing define for Linux/gcc
George Kyriazis [Fri, 19 Jan 2018 21:46:57 +0000 (15:46 -0600)]
swr/rast: Added missing define for Linux/gcc

+ ZeroMemory() macro definition for non win32-compilation in common/os.h

Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
6 years agoswr/rast: Fix one more invalid object format for windows.
George Kyriazis [Fri, 19 Jan 2018 21:46:56 +0000 (15:46 -0600)]
swr/rast: Fix one more invalid object format for windows.

Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
6 years agoradv: Always re-emit the sample position offset user SGPR.
Bas Nieuwenhuizen [Tue, 16 Jan 2018 01:08:02 +0000 (02:08 +0100)]
radv: Always re-emit the sample position offset user SGPR.

The user SGPR location can change between pipelines, so we need to
emit it again to the pottentially changed SGPR index.

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
6 years agoradv: emit pa_sc_mode_cntl_0 with multisample state.
Bas Nieuwenhuizen [Tue, 16 Jan 2018 21:20:13 +0000 (22:20 +0100)]
radv: emit pa_sc_mode_cntl_0 with multisample state.

We don't have the meta kludge with 0 viewports anymore,
so we can always enable them.

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
6 years agoi965: Avoid problems from referencing orphaned BOs after growing.
Kenneth Graunke [Tue, 28 Nov 2017 16:44:11 +0000 (08:44 -0800)]
i965: Avoid problems from referencing orphaned BOs after growing.

Growing the batch/state buffer is a lot more dangerous than I thought.

A number of places emit multiple state buffer sections, and then write
data to the returned pointer, or save a pointer to brw->batch.state.bo
and then use it in relocations.  If each call can grow, this can result
in stale map references or stale BO pointers.  Furthermore, fences refer
to the old batch BO, and that reference needs to continue working.

To avoid these woes, we avoid ever swapping the brw->batch.*.bo pointer,
instead exchanging the brw_bo structures in place.  That way, stale BO
references are fine - the GEM handle changes, but the brw_bo pointer
doesn't.  We also defer the memcpy until a quiescent point, so callers
can write to the returned pointer - which may be in either BO - and
we'll sort it out and combine the two properly in the end.

v2/v3:
- Handle stale pointers in the shadow copy case, where realloc may or
  may not move our shadow copy to a new address.
- Track the partial map explicitly, to avoid problems with buffer reuse
  where multiple map modes exist (caught by Chris Wilson).

v4:
- Don't use realloc in the CPU shadow case, it isn't safe.

Fixes: 2dfc119f22f257082ab0 "i965: Grow the batch/state buffers if we need space and can't flush."
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com> [v3]
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
6 years agoi965: Rename 'aux' to 'prog_data' in program cache.
Kenneth Graunke [Thu, 18 Jan 2018 22:01:20 +0000 (14:01 -0800)]
i965: Rename 'aux' to 'prog_data' in program cache.

'aux' is a very generic name, suggesting it can be a bunch of things.
However, it's always the brw_*_prog_data structure.  So, call it that.

Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
6 years agoswr: allow a single swr architecture to be builtin
Chuck Atkins [Thu, 18 Jan 2018 19:57:58 +0000 (14:57 -0500)]
swr: allow a single swr architecture to be builtin

Part 2 of 2 (part 1 is autoconf changes, part 2 is C++ changes)

When only a single SWR architecture is being used, this allows that
architecture to be builtin rather than as a separate libswrARCH.so that
gets loaded via dlopen.  Since there are now several different code
paths for each detected CPU architecture, the log output is also
adjusted to convey where the backend is getting loaded from.

This allows SWR to be used for static mesa builds which are still
important for large HPC environments where shared libraries can impose
unacceptable application startup times as hundreds of thousands of copies
of the libs are loaded from a shared parallel filesystem.

Based on an initial implementation by Tim Rowley.

v2: Refactor repetitive preprocessor checks to reduce code duplication
v3: Formatting changes per Bruce C. Also delay screen creation until end
    to avoid leaks when failure conditions are hit.

Signed-off-by: Chuck Atkins <chuck.atkins@kitware.com>
Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
CC: Tim Rowley <timothy.o.rowley@intel.com>
Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
6 years agoswr: (autoconf) allow a single swr architecture to be builtin
Chuck Atkins [Thu, 18 Jan 2018 19:57:57 +0000 (14:57 -0500)]
swr: (autoconf) allow a single swr architecture to be builtin

Part 1 of 2 (part 1 is autoconf changes, part 2 is C++ changes)

When only a single SWR architecture is being used, this allows that
architecture to be builtin rather than as a separate libswrARCH.so that
gets loaded via dlopen.  Since there are now several different code
paths for each detected CPU architecture, the log output is also
adjusted to convey where the backend is getting loaded from.

This allows SWR to be used for static mesa builds which are still
important for large HPC environments where shared libraries can impose
unacceptable application startup times as hundreds of thousands of copies
of the libs are loaded from a shared parallel filesystem.

Based on an initial implementation by Tim Rowley.

v2: Fix comment placement pointed out by Bruce C.

Signed-off-by: Chuck Atkins <chuck.atkins@kitware.com>
Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
CC: Tim Rowley <timothy.o.rowley@intel.com>
Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
6 years agoswr: fix clang 5 null cast warning
Greg V [Sun, 31 Dec 2017 16:55:27 +0000 (19:55 +0300)]
swr: fix clang 5 null cast warning

Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
6 years agomesa/program: Fix -Wunused-param warning
Gert Wollny [Thu, 18 Jan 2018 08:57:29 +0000 (09:57 +0100)]
mesa/program: Fix -Wunused-param warning

v2: Don't annotate, but remove the unused ctx parameter

Signed-off-by: Gert Wollny <gw.fossdev@gmail.com>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
6 years agomesa/program/prog_execute.c: Silence -Wunused-param
Gert Wollny [Thu, 18 Jan 2018 08:57:28 +0000 (09:57 +0100)]
mesa/program/prog_execute.c: Silence -Wunused-param

v2: Don't annotate, but remove the unused ctx parameter

Signed-off-by: Gert Wollny <gw.fossdev@gmail.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
6 years agomesa: Make numSamples an unsigned int
Gert Wollny [Thu, 18 Jan 2018 08:57:27 +0000 (09:57 +0100)]
mesa: Make numSamples an unsigned int

As a followup to the previous patch propagate the change of numSamples
from int to unsigned to gl_config::samples and consequently fix some
-Wsign-compare warnings.

Signed-off-by: Gert Wollny <gw.fossdev@gmail.com>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
6 years agogallium: Make (num_)samples an unsigned int
Gert Wollny [Thu, 18 Jan 2018 08:57:26 +0000 (09:57 +0100)]
gallium: Make (num_)samples an unsigned int

According to the ARB_multisample num_samples is a non-negative integer.
Consequently define it as such, fail in glx/choose_visual if a negative
number is given.

v2: split patch into gallium and mesa part

Signed-off-by: Gert Wollny <gw.fossdev@gmail.com>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
6 years agodocs: correct a typo in releasing instructions
Andres Gomez [Thu, 18 Jan 2018 22:29:10 +0000 (00:29 +0200)]
docs: correct a typo in releasing instructions

Cc: Emil Velikov <emil.velikov@collabora.com>
Cc: Juan A. Suarez Romero <jasuarez@igalia.com>
Signed-off-by: Andres Gomez <agomez@igalia.com>
Reviewed-by: Eric Engestrom <eric@engestrom.ch>
Reviewed-by: Juan A. Suarez <jasuarez@igalia.com>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
6 years agodocs: move untar line in basic testing instructions for coherence
Andres Gomez [Thu, 18 Jan 2018 22:29:09 +0000 (00:29 +0200)]
docs: move untar line in basic testing instructions for coherence

For scons, windows/mingw dealing with LLVM_CONFIG is done before
untarring. This is also more convenient for copy and paste.

Cc: Emil Velikov <emil.velikov@collabora.com>
Cc: Juan A. Suarez Romero <jasuarez@igalia.com>
Signed-off-by: Andres Gomez <agomez@igalia.com>
Reviewed-by: Eric Engestrom <eric@engestrom.ch>
Reviewed-by: Juan A. Suarez <jasuarez@igalia.com>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
6 years agodocs: add a notice whenever a release is the final in a series
Andres Gomez [Thu, 18 Jan 2018 22:29:08 +0000 (00:29 +0200)]
docs: add a notice whenever a release is the final in a series

Cc: Emil Velikov <emil.velikov@collabora.com>
Cc: Juan A. Suarez Romero <jasuarez@igalia.com>
Signed-off-by: Andres Gomez <agomez@igalia.com>
Reviewed-by: Eric Engestrom <eric@engestrom.ch>
Reviewed-by: Juan A. Suarez <jasuarez@igalia.com>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
6 years agodocs: add final release note for 17.2.8
Andres Gomez [Thu, 18 Jan 2018 22:29:07 +0000 (00:29 +0200)]
docs: add final release note for 17.2.8

Cc: Emil Velikov <emil.velikov@collabora.com>
Cc: Juan A. Suarez Romero <jasuarez@igalia.com>
Signed-off-by: Andres Gomez <agomez@igalia.com>
Reviewed-by: Eric Engestrom <eric@engestrom.ch>
Reviewed-by: Juan A. Suarez <jasuarez@igalia.com>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
6 years agodocs: add final release note for 17.1.10
Andres Gomez [Thu, 18 Jan 2018 22:29:06 +0000 (00:29 +0200)]
docs: add final release note for 17.1.10

Cc: Emil Velikov <emil.velikov@collabora.com>
Cc: Juan A. Suarez Romero <jasuarez@igalia.com>
Signed-off-by: Andres Gomez <agomez@igalia.com>
Reviewed-by: Eric Engestrom <eric@engestrom.ch>
Reviewed-by: Juan A. Suarez <jasuarez@igalia.com>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
6 years agost/vdpau: release held lock in error path
Grazvydas Ignotas [Mon, 15 Jan 2018 22:00:33 +0000 (00:00 +0200)]
st/vdpau: release held lock in error path

Signed-off-by: Grazvydas Ignotas <notasas@gmail.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Cc: mesa-stable@lists.freedesktop.org
6 years agodocs: update calendar, add news and link release notes to 17.3.3
Juan A. Suarez Romero [Thu, 18 Jan 2018 21:38:59 +0000 (22:38 +0100)]
docs: update calendar, add news and link release notes to 17.3.3

Signed-off-by: Juan A. Suarez Romero <jasuarez@igalia.com>
6 years agodocs: add sha256 checksums for 17.3.3
Juan A. Suarez Romero [Thu, 18 Jan 2018 21:34:34 +0000 (22:34 +0100)]
docs: add sha256 checksums for 17.3.3

Signed-off-by: Juan A. Suarez Romero <jasuarez@igalia.com>
(cherry picked from commit bc1503b13fcf8190262757ea7f86613e14e25981)

6 years agodocs: add release notes for 17.3.3
Juan A. Suarez Romero [Thu, 18 Jan 2018 20:02:46 +0000 (20:02 +0000)]
docs: add release notes for 17.3.3

Signed-off-by: Juan A. Suarez Romero <jasuarez@igalia.com>
(cherry picked from commit 80f5f279b3f9fc752ba35b1cb2878a936f8ace90)

6 years agoanv: avoid segmentation fault due to vk_error()
Samuel Iglesias Gonsálvez [Fri, 19 Jan 2018 07:45:10 +0000 (08:45 +0100)]
anv: avoid segmentation fault due to vk_error()

vk_error() is a macro that calls __vk_errorf() with instance == NULL.

Then, __vk_errorf() passes a pointer to instance->debug_report_callbacks
to vk_debug_error(), which segfaults as this pointer is invalid but not
NULL.

Fixes: e5b1bd6ab8 "vulkan: move anv VK_EXT_debug_report implementation to common code."
Signed-off-by: Samuel Iglesias Gonsálvez <siglesias@igalia.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
6 years agoac/nir: Fix vector extraction if source vector has >4 elements.
Bas Nieuwenhuizen [Wed, 17 Jan 2018 13:33:39 +0000 (14:33 +0100)]
ac/nir: Fix vector extraction if source vector has >4 elements.

v2: Add forgotten argument and start offset.

Fixes: 91074bb11bda "radv/ac: Implement Float64 SSBO stores."
Tested-by: Timothy Arceri <tarceri@itsqueeze.com>
Acked-by: Timothy Arceri <tarceri@itsqueeze.com>
6 years agoac/nir: Use correct 32-bit component writemask for 64-bit SSBO stores.
Bas Nieuwenhuizen [Wed, 17 Jan 2018 13:23:17 +0000 (14:23 +0100)]
ac/nir: Use correct 32-bit component writemask for 64-bit SSBO stores.

Fixes: 91074bb11bda "radv/ac: Implement Float64 SSBO stores."
Tested-by: Timothy Arceri <tarceri@itsqueeze.com>
Acked-by: Timothy Arceri <tarceri@itsqueeze.com>
6 years agoac/nir: Fix TCS output LDS offsets.
Bas Nieuwenhuizen [Fri, 19 Jan 2018 00:20:12 +0000 (01:20 +0100)]
ac/nir: Fix TCS output LDS offsets.

When a channel was not set we also did not increase the LDS address,
while that obviously should happen.

The output loading code was inadvertently fixed which resulted in a
mismatch causing the SaschaWillems tessellation demo to result
in corrupt rendering.

Fixes: 7898eb9a60 "ac: rework load_tcs_{inputs,outputs}"
Reviewed-by: Dave Airlie <airlied@redhat.com>
6 years agoradv: Use correct bindings for inputRate in key generation.
Bas Nieuwenhuizen [Thu, 18 Jan 2018 14:35:11 +0000 (15:35 +0100)]
radv: Use correct bindings for inputRate in key generation.

The bindings also have an index field.

Fixes: 49d035122e "radv: Add single pipeline cache key."
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=104677
Reviewed-by: Dave Airlie <airlied@redhat.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
6 years agoradv: Implement VK_ANDROID_native_buffer.
Bas Nieuwenhuizen [Thu, 4 Jan 2018 17:38:32 +0000 (18:38 +0100)]
radv: Implement VK_ANDROID_native_buffer.

Passes
  dEQP-VK.api.smoke.*
  dEQP-VK.wsi.android.*

with android-cts-7.1_r12 .

Unlike the initial anv implementation this does
use syncobjs instead of waiting on the CPU.

This is missing meson build coverage for now.

One possible todo is that linux 4.15 now has a
sycall that allows us to export amdgpu fence to
a sync_file, which allows us not to force all
fences and semaphores to use syncobjs. However,
I had trouble with my kernel crashing regularly
with NULL pointers, and I'm not sure how beneficial
it is in the first place given that intel uses
syncobjs for all fences if available.

Reviewed-by: Dave Airlie <airlied@redhat.com>
6 years agoradv: Add create image flag to not use DCC/CMASK.
Bas Nieuwenhuizen [Thu, 4 Jan 2018 17:38:31 +0000 (18:38 +0100)]
radv: Add create image flag to not use DCC/CMASK.

If we import an image, we might not have space in the
buffer for CMASK, even though it is compatible.

Reviewed-by: Dave Airlie <airlied@redhat.com>
6 years agoradv: Generate VK_ANDROID_native_buffer.
Bas Nieuwenhuizen [Thu, 4 Jan 2018 17:38:30 +0000 (18:38 +0100)]
radv: Generate VK_ANDROID_native_buffer.

Reviewed-by: Dave Airlie <airlied@redhat.com>
6 years agoradv: Replace an assert with unreachable.
Bas Nieuwenhuizen [Wed, 17 Jan 2018 22:23:02 +0000 (23:23 +0100)]
radv: Replace an assert with unreachable.

Otherwise we get uninitialized variable warnings for es_vgpr_comp_cnt.

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
6 years agoradv: Remove DCC check on CS resolve dst image.
Bas Nieuwenhuizen [Wed, 17 Jan 2018 22:21:42 +0000 (23:21 +0100)]
radv: Remove DCC check on CS resolve dst image.

Gives a warning when the assert is disabled, and not even
necessarily true.

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
6 years agogallivm: support avx512 (16x32) in interleave2_half
George Kyriazis [Wed, 17 Jan 2018 00:06:34 +0000 (18:06 -0600)]
gallivm: support avx512 (16x32) in interleave2_half

lp_build_interleave2_half was not doing the right thing for avx512-style
16-wide loads.

This path is hit in the swr driver with a 16-wide vertex shader. It is
called from lp_build_transpose_aos, when doing texel fetches and the
fetched data needs to be transposed to one component per output register.

Special-case the post-load swizzle operations for avx512 16x32 (16-wide
32-bit values) so that we move the xyzw components correctly to the outputs.

Reviewed-by: Roland Scheidegger <sroland@vmware.com>
6 years agovbo: fix VBO optimization regression
Brian Paul [Wed, 17 Jan 2018 22:15:54 +0000 (15:15 -0700)]
vbo: fix VBO optimization regression

The optimization in change 8e4efdc895ea ("vbo: optimize some display
list drawing") missed the loopback case.  This is used when the
glBegin/End primitive doesn't have a uniform set of vertex attributes.
The new Piglit gl-1.0-dlist-materials test hits this.

So check the aligned_vertex_buffer_offset(list) value and adjust the
buffer offset accordingly.

We also need to remove the 'start == 0' assertion in the loopback
code since it no longer applies.

Reviewed-by: Roland Scheidegger <sroland@vmware.com>
6 years agomeson: ensure that xmlpool_options.h is generated for targets that need it
Dylan Baker [Thu, 18 Jan 2018 00:08:51 +0000 (16:08 -0800)]
meson: ensure that xmlpool_options.h is generated for targets that need it

Currently a couple of gallium targets race with xmlpool_options.h being
generated, don't do that.

Signed-off-by: Dylan Baker <dylan.c.baker@intel.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
6 years agoac: fix visit_ssa_undef() for doubles
Timothy Arceri [Thu, 18 Jan 2018 01:01:33 +0000 (12:01 +1100)]
ac: fix visit_ssa_undef() for doubles

V2: use LLVMIntTypeInContext()

Fixes: f4e499ec7914 "radv: add initial non-conformant radv vulkan driver"
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
6 years agoac/nir: account for view index in the user sgpr allocation.
Dave Airlie [Thu, 18 Jan 2018 02:31:40 +0000 (02:31 +0000)]
ac/nir: account for view index in the user sgpr allocation.

The view index user sgpr wasn't being accounted for properly,
this refactors out the code to decide if it's required and then
uses that info to account for it.

Fixes: 180c1b924e (ac/nir: Add shader support for multiviews.)
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Signed-off-by: Dave Airlie <airlied@redhat.com>
6 years agor600: enable ARB_enhanced_layouts
Dave Airlie [Thu, 18 Jan 2018 04:09:38 +0000 (14:09 +1000)]
r600: enable ARB_enhanced_layouts

Only one piglit test fails,
sso-vs-gs-fs-array-interleave

There are 3 tests using ssbo without checking sizes failing also
but those are test bugs.

Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
6 years agointel: Future-proof ring names for aubinator_error_decode
Chris Wilson [Wed, 17 Jan 2018 15:41:25 +0000 (15:41 +0000)]
intel: Future-proof ring names for aubinator_error_decode

The kernel is moving to a $class$instance naming scheme in preparation
for accommodating more rings in the future in a consistent manner. It is
already using the naming scheme internally, and now we are looking at
updating some soft-ABI such as the error state to use the new naming
scheme. This of course means we need to teach aubinator_error_decode how
to map both sets of ring names onto its register maps.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Michel Thierry <michel.thierry@intel.com>
Cc: Michal Wajdeczko <michal.wajdeczko@intel.com>
Cc: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com>
Cc: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Cc: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Michel Thierry <michel.thierry@intel.com>
6 years agoi965: Bind null render targets for shadow sampling + color.
Kenneth Graunke [Wed, 17 Jan 2018 22:16:04 +0000 (14:16 -0800)]
i965: Bind null render targets for shadow sampling + color.

Portal 2 appears to bind RGBA8888_UNORM textures to a sampler2DShadow,
and calls shadow2D() on it.  This causes undefined behavior in OpenGL.

Unfortunately, our sampler appears to hang in this scenario, which is
not acceptable.  Just give them a null surface instead, which returns
all zeroes.

Fixes GPU hangs in Portal 2 on Kabylake.

Huge thanks to Jason Ekstrand for noticing this crazy behavior while
sifting through crash dumps.

Cc: mesa-stable@lists.freedesktop.org
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=104487
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
6 years agoanv/query: implement multiview interactions
Iago Toral Quiroga [Thu, 4 Jan 2018 02:45:56 +0000 (03:45 +0100)]
anv/query: implement multiview interactions

From the Vulkan spec with KHX extensions:

  "If queries are used while executing a render pass instance that has
   multiview enabled, the query uses N consecutive query indices
   in the query pool (starting at query) where N is the number of bits
   set in the view mask in the subpass the query is used in.

   How the numerical results of the query are distributed among the
   queries is implementation-dependent. For example, some implementations
   may write each view's results to a distinct query, while other
   implementations may write the total result to the first query and write
   zero to the other queries. However, the sum of the results in all the
   queries must accurately reflect the total result of the query summed
   over all views. Applications can sum the results from all the queries to
   compute the total result."

In our case we only really emit a single query (in the first query index)
that stores the aggregated result for all views, but we still need to manage
availability for all the other query indices involved, even if we don't
actually use them.

This is relevant when clients call vkGetQueryPoolResults and pass all N
queries to retrieve the results. In that scenario, without this patch,
we will never see queries other than the first being available since we
never emit them.

v2: we need the same treatment for timestamp queries.

v3 (Jason):
 - Better an if instead of an early return.
 - We can't write to this memory in the CPU, we should use
   MI_STORE_DATA_IMM and emit_query_availability (Jason).

v4 (Jason):
 - No need to take the value to write as parameter, just hard code it to 0.

Fixes test failures in some work-in-progress CTS multiview+query tests.

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
6 years agovc5: add missing files to the tarball
Emil Velikov [Wed, 17 Jan 2018 16:34:48 +0000 (16:34 +0000)]
vc5: add missing files to the tarball

Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
6 years agobroadcom: add missing headers to the tarball
Emil Velikov [Wed, 17 Jan 2018 16:27:52 +0000 (16:27 +0000)]
broadcom: add missing headers to the tarball

Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
6 years agoi965/screen: Allow drirc to set 'allow_rgb10_configs' again.
Mario Kleiner [Thu, 18 Jan 2018 06:16:20 +0000 (08:16 +0200)]
i965/screen: Allow drirc to set 'allow_rgb10_configs' again.

Since setup of ALLOW_RGB10_CONFIGS was moved to i965's own
brw_config_options.xml, this was hard-coded to false and
could not be overriden by drirc. Add some parsing into
i965's private screen->optionCache to enable drirc again.

Fixes: b391fb26df9f1b ("dri_util: remove ALLOW_RGB10_CONFIGS option (v2)")
Signed-off-by: Mario Kleiner <mario.kleiner.de@gmail.com>
Cc: Marek Olšák <marek.olsak@amd.com>
Cc: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
6 years agoanv: return VK_ERROR_OUT_OF_DEVICE_MEMORY when surface size is out of HW limits
Samuel Iglesias Gonsálvez [Fri, 12 Jan 2018 08:41:17 +0000 (09:41 +0100)]
anv: return VK_ERROR_OUT_OF_DEVICE_MEMORY when surface size is out of HW limits

Signed-off-by: Samuel Iglesias Gonsálvez <siglesias@igalia.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
6 years agoac: tidy up array indexing logic
Timothy Arceri [Thu, 18 Jan 2018 04:46:35 +0000 (15:46 +1100)]
ac: tidy up array indexing logic

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
6 years agomesa/st: translate SO info in glsl_to_nir() case
Rob Clark [Wed, 10 Jan 2018 02:54:14 +0000 (03:54 +0100)]
mesa/st: translate SO info in glsl_to_nir() case

This was handled for VS, but not for GS.

Fixes for gallium drivers using nir:
spec@arb_gpu_shader5@arb_gpu_shader5-xfb-streams-without-invocations
spec@arb_gpu_shader5@arb_gpu_shader5-xfb-streams*
spec@arb_transform_feedback3@arb_transform_feedback3-ext_interleaved_two_bufs_gs*
spec@ext_transform_feedback@geometry-shaders-basic
spec@ext_transform_feedback@* use_gs
spec@glsl-1.50@execution@geometry@primitive-id*
spec@glsl-1.50@execution@geometry@tri-strip-ordering-with-prim-restart gl_triangle_strip *
spec@glsl-1.50@transform-feedback-builtins
spec@glsl-1.50@transform-feedback-type-and-size

v2: don't call st_translate_program_stream_output) for TCS

v3: drop scanning patch outputs as TCS can't output xfb

Signed-off-by: Rob Clark <robdclark@gmail.com>
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Tested-by: Karol Herbst <kherbst@redhat.com>
6 years agor600/sb: add lds related peepholes.
Dave Airlie [Wed, 10 Jan 2018 06:08:48 +0000 (06:08 +0000)]
r600/sb: add lds related peepholes.

if no destination:
a) convert _RET instructions to non _RET variants if no dst
b) set src0 to undefined if it's a READ, this should get DCE then.

Acked-By: Roland Scheidegger <sroland@vmware.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
6 years agor600/sb: use different stacks for tracking lds and queue usage.
Dave Airlie [Wed, 10 Jan 2018 05:49:16 +0000 (05:49 +0000)]
r600/sb: use different stacks for tracking lds and queue usage.

The normal ssa renumbering isn't sufficient for LDS queue access,
this uses two stacks, one for the lds queue, and one for the
lds r/w ordering.

The LDS oq values are incremented in their use in a linear
fashion.
The LDS rw values are incremented in their definitions and used
in the next lds operation to ensure reordering doesn't occur.

Acked-By: Roland Scheidegger <sroland@vmware.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
6 years agor600/sb: schedule LDS ops in appropriate places.
Dave Airlie [Wed, 10 Jan 2018 04:41:02 +0000 (04:41 +0000)]
r600/sb: schedule LDS ops in appropriate places.

So LDS ops have to be SLOT_X,
and LDS OQ reads have read port restrictions so we try
and force those into only having one per slot and avoiding
bank swizzles.

Acked-By: Roland Scheidegger <sroland@vmware.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
6 years agor600/sb: hit the scheduler with a big hammer to avoid lds splits.
Dave Airlie [Wed, 10 Jan 2018 04:38:07 +0000 (04:38 +0000)]
r600/sb: hit the scheduler with a big hammer to avoid lds splits.

This tries to avoid an lds queue read getting scheduled separately
from an lds ret read, the non-sb code uses the same style of hammer,
this isn't foolproof.

We can do better, but it's a bit tricky, as you have to scan ahead
and either schedule more lds oq moves and more lds reads and that
could lead to you running out of space anyways.

Acked-By: Roland Scheidegger <sroland@vmware.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
6 years agor600/sb: adding lds oq tracking to the scheduler
Dave Airlie [Wed, 10 Jan 2018 04:36:37 +0000 (04:36 +0000)]
r600/sb: adding lds oq tracking to the scheduler

This adds support for tracking the lds oq read/writes
so can avoid scheduling other things in between.

This patch just adds the tracking and assert to show
problems.

Acked-By: Roland Scheidegger <sroland@vmware.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
6 years agor600/sb: add gcm support to avoid clause between lds read/queue read
Dave Airlie [Wed, 10 Jan 2018 04:30:23 +0000 (04:30 +0000)]
r600/sb: add gcm support to avoid clause between lds read/queue read

You have to schedule LDS_READ_RET _, x and MOV reg, LDS_OQ_A_POP
in the same basic block/clause. This makes sure once we've issues
and MOV we don't add another block until we balance it with an
LDS read.

Acked-By: Roland Scheidegger <sroland@vmware.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
6 years agor600/sb: handle lds special dest registers.
Dave Airlie [Wed, 10 Jan 2018 04:25:41 +0000 (04:25 +0000)]
r600/sb: handle lds special dest registers.

This adds lds to the geom emit handling

Acked-By: Roland Scheidegger <sroland@vmware.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
6 years agor600/sb: handle LDS operations in folding.
Dave Airlie [Wed, 10 Jan 2018 04:25:20 +0000 (04:25 +0000)]
r600/sb: handle LDS operations in folding.

Don't try and fold LDS using expressions.

Acked-By: Roland Scheidegger <sroland@vmware.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
6 years agor600/sb: add finalising for lds output queue special values.
Dave Airlie [Wed, 10 Jan 2018 04:22:28 +0000 (04:22 +0000)]
r600/sb: add finalising for lds output queue special values.

We need to convert these to the hw special registers.

Acked-By: Roland Scheidegger <sroland@vmware.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
6 years agor600/sb: add initial support for parsing lds operations.
Dave Airlie [Wed, 10 Jan 2018 04:20:52 +0000 (04:20 +0000)]
r600/sb: add initial support for parsing lds operations.

This handles parsing the LDS ops and queue accessess.

Acked-By: Roland Scheidegger <sroland@vmware.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
6 years agor600/sb: disable if conversion for hs
Dave Airlie [Wed, 10 Jan 2018 03:57:52 +0000 (03:57 +0000)]
r600/sb: disable if conversion for hs

This fixes bad interactions with the LDS special values.

Acked-By: Roland Scheidegger <sroland@vmware.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
6 years agor600/sb: lds ops have no dst register.
Dave Airlie [Wed, 10 Jan 2018 03:56:37 +0000 (03:56 +0000)]
r600/sb: lds ops have no dst register.

Although these are op3s they don't have a dst reg.

Acked-By: Roland Scheidegger <sroland@vmware.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
6 years agor600/sb: introduce special register values for lds support.
Dave Airlie [Wed, 10 Jan 2018 03:52:50 +0000 (03:52 +0000)]
r600/sb: introduce special register values for lds support.

For LDS read/write ordering we use the LDS_RW value, reads
will wait on previous writes.
For LDS read/read from LDS queue ordering we use the LDS_OQ
values, we define two for now, though initially we'll just
support OQA.

Also add the check for the lds oq values

Acked-By: Roland Scheidegger <sroland@vmware.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
6 years agor600/sb: update last_cf if alu is the last clause
Dave Airlie [Wed, 10 Jan 2018 03:46:50 +0000 (03:46 +0000)]
r600/sb: update last_cf if alu is the last clause

It's rare to have a final alu clause on normal shaders (exports)
but tess shaders write to LDS as their output, so we see some
alu clauses, and the CF_END get put in the wrong place.

This makes sure to update last_cf correctly.

Acked-By: Roland Scheidegger <sroland@vmware.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
6 years agor600/sb: start adding GDS support
Dave Airlie [Thu, 7 Dec 2017 02:14:45 +0000 (02:14 +0000)]
r600/sb: start adding GDS support

This adds support for GDS ops to sb backend.

This seems to work for atomics and tess factor writes.

Acked-By: Roland Scheidegger <sroland@vmware.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
6 years agor600/sb: add tess/compute initial state registers.
Dave Airlie [Thu, 7 Dec 2017 03:31:41 +0000 (03:31 +0000)]
r600/sb: add tess/compute initial state registers.

This stops them being optimised out.

Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
6 years agor600/sb: fix a bug emitting ar load from a constant.
Dave Airlie [Wed, 10 Jan 2018 03:41:57 +0000 (03:41 +0000)]
r600/sb: fix a bug emitting ar load from a constant.

Some tess shaders were doing MOVA_INT _, c0.x on cayman, and then
hitting an assert in sb_bc_finalize.cpp:translate_kcache.

This makes sure the toplevel kcache tracker gets updated,
and the clause gets fixed up.

Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Cc: <mesa-stable@lists.freedesktop.org>
Signed-off-by: Dave Airlie <airlied@redhat.com>
6 years agor600/shader: only emit add instruction if param has a value.
Dave Airlie [Wed, 10 Jan 2018 02:56:15 +0000 (02:56 +0000)]
r600/shader: only emit add instruction if param has a value.

Just saves a pointless a = a + 0;

Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
6 years agor600: emit 0 gds_op for tf write.
Dave Airlie [Wed, 10 Jan 2018 02:54:33 +0000 (02:54 +0000)]
r600: emit 0 gds_op for tf write.

This field is ignored for tf writes so should be 0.

Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>