[PR87833] x86: Put -fPIC and -shared the last to create offload image

On x86, since -fPIC and -shared should be used to create offload image,
we put them the last to properly create offload image.

2019-11-11  H.J. Lu  <hjl.tools@gmail.com>

PR target/87833
* config/i386/intelmic-mkoffload.c (prepare_target_image): Put
-fPIC and -shared the last to create offload image.

From-SVN: r278041

Assert 'offset2' instead of 'offset' in 'gcc/gimplify.c:gimplify_scan_omp_clauses'

... to fix a long-time typo/copy'n'past-o.

gcc/
* gimplify.c (gimplify_scan_omp_clauses): Assert 'offset2' instead
of 'offset'.

From-SVN: r278038

[build] Properly track GCC language configure fragments

The 'gcc/configure' script sources all 'gcc/*/config-lang.in' files, but fails
to emit such dependency information into the build machinery.  That means,
currently, when something gets changed in a 'gcc/*/config-lang.in' file, this
is not noticed, and doesn't propagate through the build machinery.

Handling of configure fragments is modelled in the same way as it already
exists for Makefile fragments.

gcc/
* Makefile.in (LANG_CONFIGUREFRAGS): Define.
(config.status): Use/depend on it.
* configure.ac (all_lang_configurefrags): Track, 'AC_SUBST'.
* configure: Regenerate.

From-SVN: r278035

rs6000: Refine small loop unroll in loop_unroll_adjust hook

In this patch, loop unroll adjust hook is introduced for powerpc.  We
can do target related heuristic adjustment in this hook.  In this patch,
-funroll-loops is enabled for small loops at O2 and above with an option
-munroll-small-loops to guard the small loops unrolling, and it works
fine with -flto.

gcc/
2019-11-11  Jiufu Guo  <guojiufu@linux.ibm.com>

PR tree-optimization/88760
* gcc/config/rs6000/rs6000.opt (-munroll-only-small-loops): New option.
* gcc/common/config/rs6000/rs6000-common.c
(rs6000_option_optimization_table) [OPT_LEVELS_2_PLUS_SPEED_ONLY]:
Turn on -funroll-loops and -munroll-only-small-loops.
[OPT_LEVELS_ALL]: Turn off -fweb and -frename-registers.
* config/rs6000/rs6000.c (rs6000_option_override_internal): Remove
set of PARAM_MAX_UNROLL_TIMES and PARAM_MAX_UNROLLED_INSNS.
Turn off -munroll-only-small-loops for explicit -funroll-loops.
(TARGET_LOOP_UNROLL_ADJUST): Add loop unroll adjust hook.
(rs6000_loop_unroll_adjust): Define it.  Use -munroll-only-small-loops.

gcc.testsuite/
2019-11-11  Jiufu Guo  <guojiufu@linux.ibm.com>

PR tree-optimization/88760
* gcc.dg/pr59643.c: Update back to r277550.

From-SVN: r278034

[rs6000] Make load cost a bit more in vectorization cost

To align with rs6000_insn_cost costing more for load type insns,
this patch is to make load insns cost more in vectorization cost
function.  The latency of load insns is about twice that of
"simple" instructions; 2 vs. 1 on older cores, and 4 (or so) vs.
2 on newer cores.  Considering that the result of load usually
is used somehow later (true-dep) but store won't, we keep the
store as before.

The SPEC2017 performance evaluation on Power8 shows 525.x264_r
+9.56%, 511.povray_r +2.08%, 527.cam4_r 1.16% gains, no
significant degradation, SPECINT geomean +0.88%, SPECFP geomean
+0.26%.

The SPEC2017 performance evaluation on Power9 shows no significant
improvement or degradation, SPECINT geomean +0.04%, SPECFP geomean
+0.04%.

The SPEC2006 performance evaluation on Power8 shows 454.calculix
+4.41% gain but 416.gamess -1.19% and 453.povray -3.83% degradation.
I looked into the two degradation bmks, the degradation were NOT
due to hotspot changes by vectorization, were all side effects.
SPECINT geomean +0.10%, SPECFP geomean no changed considering
the degradation.

gcc/ChangeLog

2019-11-11  Kewen Lin  <linkw@gcc.gnu.org>

    * config/rs6000/rs6000.c (rs6000_builtin_vectorization_cost): Make
    scalar_load, vector_load, unaligned_load and vector_gather_load cost
    more to conform hardware latency and insn cost settings.

From-SVN: r278033

Daily bump.

From-SVN: r278032

[Darwin, machopic 11/n] A flag to indicate synbols should be linker-visible.

Some of the solution to PR71767 is incomplete, and we need finer-grained
control over whether symbols need to be made linker-visible.  This is a
preparation patch, providing the flag.

gcc/ChangeLog:

2019-11-10  Iain Sandoe  <iain@sandoe.co.uk>

* config/darwin.h (MACHO_SYMBOL_FLAG_LINKER_VIS): New.
(MACHO_SYMBOL_LINKER_VIS_P): New.

From-SVN: r278028

Don't print warning when moving to static with -fno-automatic

As part of PR 91413, GFortran now prints a warning when a variable is
moved from the stack to static storage. However, when the user
explicitly specifies that all local variables should be put in static
storage with the -fno-automatic option, don't print this warning.

Regtested on x86_64-pc-linux-gnu, committed as obvious.

gcc/fortran/ChangeLog:

2019-11-10  Janne Blomqvist  <jb@gcc.gnu.org>

PR fortran/91413
* trans-decl.c (gfc_finish_var_decl): Don't print warning when
-fno-automatic is enabled.

From-SVN: r278027

Implement D1957R0, T* to bool should be considered narrowing.

This paper was delayed until the February meeting in Prague so that we could
get a better idea of what the impact on existing code would actually be.  To
that end, I'm implementing it now.

* typeck2.c (check_narrowing): Treat pointer->bool as a narrowing
conversion with -std=c++2a.

From-SVN: r278026

re PR fortran/92123 ([F2018/array-descriptor]  Scalar allocatable/pointer with array descriptor (via bind(C)): ICE with select rank or error scalar variable with POINTER or ALLOCATABLE in procedure with BIND(C) is not yet supported)

2019-11-10  Paul Thomas  <pault@gcc.gnu.org>

PR fortran/92123
*decl.c (gfc_verify_c_interop_param): Remove error asserting
that pointer or allocatable variables in a bind C procedure are
not supported. Delete some trailing spaces.
* trans-stmt.c (trans_associate_var): Correct the attempt to
treat scalar pointer or allocatable temporaries as if they are
array descriptors.

2019-11-10  Paul Thomas  <pault@gcc.gnu.org>

PR fortran/92123
* gfortran.dg/bind_c_procs_3.f90 : New test.
* gfortran.dg/ISO_Fortran_binding_15.c : New test.
* gfortran.dg/ISO_Fortran_binding_15.f90 : Additional source.

From-SVN: r278025

[LRA] Do not use eliminable registers for spilling

The liveness of eliminable hard registers is not tracked by LRA between
basic blocks, so they should not be used as spill registers as LRA may
decide to allocate them to pseudos while the spilled value is still live.

2019-11-10  Kwok Cheung Yeung  <kcy@codesourcery.com>

gcc/
* lra-spills.c (assign_spill_hard_regs): Do not spill into
registers in eliminable_regset.

From-SVN: r278024

Manually CSE sreal frequency calculations

* ipa-inline.c (compute_uninlined_call_time,
compute_inlined_call_time): Take edge frequency as
parameter rather than computing it by itself.
(big_speedup_p, edge_badness): Manually CSE sreal
frequency calculations.

From-SVN: r278023

Short circuit case where profiles are same.

        * profile-count.c (profile_count::to_sreal_scale): Short circuit
case where profiles are same.

From-SVN: r278022

* cgraph.c (cgraph_edge::maybe_hot_p): Do not use sreal_frequency.

From-SVN: r278021

ipa-prop.c (ipa_propagate_indirect_call_infos): Remove ipa edge args summaries of inlined edge unless...

* ipa-prop.c (ipa_propagate_indirect_call_infos): Remove ipa edge
args summaries of inlined edge unless it holds info about
described reference.

From-SVN: r278020

Switch www.hboehm.info to https

* doc/xml/manual/using.xml: Switch www.hboehm.info to https.

From-SVN: r278019

rs6000: Allow any CC mode in movcc

Sometimes combine wants to do a move in CCFPmode, but we don't currently
handle moves in any CC mode other than CCmode.  Fix that oversight.

* config/rs6000/rs6000.md (CC_any): New mode iterator.
(*movcc_internal1): Rename to...
(*movcc_<mode> for CC_any): ... this.  Support moves of all CC modes.

From-SVN: r278017

cgraph.h (struct cgraph_node): Add ipcp_clone flag.

* cgraph.h (struct cgraph_node): Add ipcp_clone flag.
(cgraph_node::create_virtual_clone): Copy it.
* ipa-cp.c (ipcp_versionable_function_p): Watch for missing
summaries.
(ignore_edge_p): If caller has ipa-cp disabled, skip the edge, too.
(ipcp_verify_propagated_values): Do not verify nodes where ipcp
is disabled.
(propagate_constants_across_call): If callee is not analyzed, give up.
(propagate_constants_topo): Lower to bottom latties of all callees of
functions with ipa-cp disabled.
(ipcp_propagate_stage): Skip functions with ipa-cp disabled.
(cgraph_edge_brings_value_p): Check for availability first.
(create_specialized_node): Set ipcp_clone.
(ipcp_store_bits_results): Check that info is present.
* ipa-fnsummary.c (evaluate_properties_for_edge): Do not analyze
thunks.
(ipa_call_context::duplicate_from, ipa_call_context::equal_to): Be
conservative when callee summary is missing.
(remap_edge_summaries): Lookup call summary only when needed.
* ipa-icf.c (sem_function::param_used_p): Be ready for missing summary.
* ipa-prpo.c (ipa_alloc_node_params, ipa_initialize_node_params):
Use get_create.
(ipa_analyze_node): Use get_create.
(propagate_controlled_uses): Do not propagate when function is not
analyzed.
(ipa_propagate_indirect_call_infos): Remove summary of inline clone.
(ipa_read_node_info): Use get_create.
* ipa-prop.h (IPA_NODE_REF): Use get.
(IPA_NODE_REF_GET_CREATE): New.

From-SVN: r278016

Daily bump.

From-SVN: r278013

ipa-fnsummary.c (evaluate_properties_for_edge): Call IPA_NODE_REF on function symbol.

* ipa-fnsummary.c (evaluate_properties_for_edge): Call IPA_NODE_REF
on function symbol.
* gcc.dg/tree-ssa/pr46076.c: Make tested code hot.

From-SVN: r278009

tree.c (fld_incomplete_type_of): Clear TYPE_FINAL_P, TYPE_EMPTY_P, ENUM_IS_OPAQUE and ENUM_IS_SCOPED.

* tree.c (fld_incomplete_type_of): Clear TYPE_FINAL_P, TYPE_EMPTY_P,
ENUM_IS_OPAQUE and ENUM_IS_SCOPED.
(free_lang_data_in_binfo): Clear TREE_PUBLIC in BINFO
(free_lang_data_in_type): Clear ENUM_IS_OPAQUE and ENUM_IS_SCOPED.

From-SVN: r278008

ipa-inline-analysis.c (do_estimate_growth_1): Add support for capping the growth cumulated.

* ipa-inline-analysis.c (do_estimate_growth_1): Add support for
capping the growth cumulated.
(offline_size): Break out from ...
(estimate_growth): ... here.
(check_callers): Add N, OFFLINE and MIN_SIZE and KNOWN_EDGE
parameters.
(growth_likely_positive): Turn to ...
(growth_positive_p): Re-implement.
* ipa-inline.h (growth_likely_positive): Remove.
(growth_positive_p): Declare.
* ipa-inline.c (want_inline_small_function_p): Use
growth_positive_p.
(want_inline_function_to_all_callers_p): Likewise.

From-SVN: r278007

ipa-fnsummary.c (ipa_call_context::estimate_size_and_time): Fix calculation of min_size.

* ipa-fnsummary.c (ipa_call_context::estimate_size_and_time): Fix
calculation of min_size.
(ipa_update_overall_fn_summary): Likewise.

From-SVN: r278006

ipa-fnsummary.c (estimate_edge_size_and_time): Do not call estimate_edge_devirt_benefit when not computing hints...

* ipa-fnsummary.c (estimate_edge_size_and_time): Do not call
estimate_edge_devirt_benefit when not computing hints;
do not compute time when not asked for.
(estimate_calls_size_and_time): Pass NULL hints and time when
these are not computed; do not evaluate hint predicates when these are
not computed.
(ipa_merge_fn_summary_after_inlining): Do not re-evaluate edge
frequency.

From-SVN: r278005

re PR tree-optimization/92401 (ICE in fold_ternary_loc, at fold-const.c:11698)

PR tree-optimization/92401
* gimple-match-head.c (gimple_resimplify1): Call const_unop only
if res_op->code is an expression with code length 1.
* gimple-match-head.c (gimple_resimplify2): Call const_binop only
if res_op->code is an expression with code length 2.
* gimple-match-head.c (gimple_resimplify3): Call fold_ternary only
if res_op->code is an expression with code length 3.

* g++.dg/opt/pr92401.C: New test.

From-SVN: r278004

Commit symbol for external BLAS routine when translating MATMUL to *GEMM.

2019-11-09  Thomas Koenig  <tkoenig@gcc.gnu.org>

PR fortran/92321
* frontend-passes.c (call_external_blas): Commit symbol for
external BLAS routine.

2019-11-09  Thomas Koenig  <tkoenig@gcc.gnu.org>

PR fortran/92321
* gfortran.dg/matmul_blas_2.f90: New test.

From-SVN: r278003

[Darwin, machopic 10/n] Rework X86 mcount stub code.

When a stub is used to call the mcount function, the code is already
marking it as used unconditionally;  This is the only use of the so-
called validation outside darwin.{h,c}.  This moves the 'validation'
into darwin.c which is a step towards making validation routine local.

gcc/

2019-11-09  Iain Sandoe  <iain@sandoe.co.uk>

* config/darwin.c (machopic_mcount_stub_name): Validate the
symbol stub name when it is created.
* config/i386/darwin.h (FUNCTION_PROFILER): Remove the symbol
stub validation.

From-SVN: r278000

Daily bump.

From-SVN: r277999

symtab.c: Fix comment typos.

* symtab.c: Fix comment typos.
* cgraphunit.c: Likewise.
* cgraph.h: Likewise.
* cgraphclones.c: Likewise.
* cgraph.c: Likewise.
* varpool.c: Likewise.
* tree-ssa-strlen.c: Likewise.
* ipa-sra.c: Likewise.
(scan_expr_access, check_all_callers_for_issues): Fix typo
in a dump message.

From-SVN: r277995

dec_char_conversion_in_assignment_4.f90: Use dg-do compile instead of dg-do run.

* gfortran.dg/dec_char_conversion_in_assignment_4.f90: Use
dg-do compile instead of dg-do run.
* gfortran.dg/dec_char_conversion_in_data_3.f90: Likewise.

From-SVN: r277994

[Darwin] Add include guard to darwin-protos.h

The Darwin protos header is missing an include guard, this adds one.

gcc/ChangeLog:

2019-11-08  Iain Sandoe  <iain@sandoe.co.uk>

* config/darwin-protos.h: Add include quard.

From-SVN: r277993

PR c++/92215 - flawed diagnostic for bit-field with non-integral type.

I noticed that for code like

  struct S {
    int *foo : 3;
  };

we generate nonsensical

  r.C:2:8: error: function definition does not declare parameters
      2 |   int *foo : 3;

It talks about a function because after parsing the declspecs of 'foo' we don't
see either ':' or "name :", so we think it's not a bit-field decl.  So we parse
the declarator and since a ctor-initializer begins with a ':', we try to parse
it as a function body, generating the awful diagnostic.  With this patch, we
issue:

  r.C:2:8: error: bit-field ‘foo’ has non-integral type ‘int*’
      2 |   int *foo : 3;

* parser.c (cp_parser_member_declaration): Add a diagnostic for
bit-fields with non-integral types.

* g++.dg/diagnostic/bitfld4.C: New test.

From-SVN: r277991

PR c++/92058 - constinit malfunction in static data member.

* g++.dg/cpp2a/constinit15.C: New test.

From-SVN: r277990

Modify range_operator::fold_range() and wi_fold () to return via reference.

2019-11-08  Andrew MacLeod <amacleod@redhat.com>

* range-op.h (range_operator::fold_range): Return result in a
reference parameter instead of by value.
(range_operator::wi_fold): Same.
* range-op.cc (range_operator::wi_fold): Return result in a reference
parameter instead of by value.
(range_operator::fold_range): Same.
(value_range_from_overflowed_bounds): Same.
(value_range_with_overflow): Same
(create_possibly_reversed_range): Same.
(operator_equal::fold_range): Same.
(operator_not_equal::fold_range): Same.
(operator_lt::fold_range): Same.
(operator_le::fold_range): Same.
(operator_gt::fold_range): Same.
(operator_ge::fold_range): Same.
(operator_plus::wi_fold): Same.
(operator_plus::op1_range): Change call to fold_range.
(operator_plus::op2_range): Change call to fold_range.
(operator_minus::wi_fold): Return result via reference parameter.
(operator_minus::op1_range): Change call to fold_range.
(operator_minus::op2_range): Change call to fold_range.
(operator_min::wi_fold): Return result via reference parameter.
(operator_max::wi_fold): Same.
(cross_product_operator::wi_cross_product): Same.
(operator_mult::wi_fold): Same.
(operator_div::wi_fold): Same.
(operator_div op_floor_div): Fix whitespace.
(operator_exact_divide::op1_range): Change call to fold_range.
(operator_lshift::fold_range): Return result via reference parameter.
(operator_lshift::wi_fold): Same.
(operator_rshift::fold_range): Same.
(operator_rshift::wi_fold): Same.
(operator_cast::fold_range): Same.
(operator_cast::op1_range): Change calls to fold_range.
(operator_logical_and::fold_range): Return result via reference.
(wi_optimize_and_or): Adjust call to value_range_with_overflow.
(operator_bitwise_and::wi_fold): Return result via reference.
(operator_logical_or::fold_range): Same.
(operator_bitwise_or::wi_fold): Same.
(operator_bitwise_xor::wi_fold): Same.
(operator_trunc_mod::wi_fold): Same.
(operator_logical_not::fold_range): Same.
(operator_bitwise_not::fold_range): Same.
(operator_bitwise_not::op1_range): Change call to fold_range.
(operator_cst::fold_range): Return result via reference.
(operator_identity::fold_range): Same.
(operator_abs::wi_fold): Same.
(operator_absu::wi_fold): Same.
(operator_negate::fold_range): Same.
(operator_negate::op1_range): Change call to fold_range.
(operator_addr_expr::fold_range): Return result via reference.
(operator_addr_expr::op1_range): Change call to fold_range.
(operator_pointer_plus::wi_fold): Return result via reference.
(operator_pointer_min_max::wi_fold): Same.
(operator_pointer_and::wi_fold): Same.
(operator_pointer_or::wi_fold): Same.
(range_op_handler): Change call to fold_range.
(range_cast): Same.
* tree-vrp.c (range_fold_binary_symbolics_p): Change call to
fold_range.
(range_fold_unary_symbolics_p): Same.
(range_fold_binary_expr): Same.
(range_fold_unary_expr): Same.

From-SVN: r277979

* arith.c (character2representation): Change i type to size_t.

From-SVN: r277978

Use correct vector type in neutral_op_for_slp_reduction

With the new reduction vectype handling, neutral_op_for_slp_reduction
needs to know whether the caller is using STMT_VINFO_REDUC_VECTYPE
(for an epilogue value) or STMT_VINFO_VECTYPE (for a PHI argument).

This fixes various gcc.target/aarch64/sve/slp_* tests.

2019-11-08  Richard Sandiford  <richard.sandiford@arm.com>

gcc/
* tree-vect-loop.c (neutral_op_for_slp_reduction): Take the
vector type as an argument rather than reading it from the
stmt_vec_info.
(vect_create_epilog_for_reduction): Update accordingly.
(vectorizable_reduction): Likewise.
(vect_transform_cycle_phi): Likewise.

From-SVN: r277977

rs6000: Fix branch_comparison_operator

* config/rs6000/predicates.md (branch_comparison_operator): Allow only
the comparison codes that make sense for the mode used, and only the
codes that can be done with a single branch instruction.

From-SVN: r277976

Allow CHARACTER literals in assignments and data statements.

Allows character literals to used to assign values to non-character variables
in the same way that Hollerith constants are used. In addition character
literals can be used in data statements just like Hollerith constants.

Warnings of such use are output to discourage this usage as it is a non-standard
legacy feature and must be explicitly enabled.

Enabled by -fdec and -fdec-char-conversions.

Co-Authored-By: Jim MacArthur <jim.macarthur@codethink.co.uk>
From-SVN: r277975

[vect] PR 92351: When peeling for alignment make alignment of epilogues unknown

gcc/ChangeLog:
2019-11-08  Andre Vieira  <andre.simoesdiasvieira@arm.com>

PR tree-optimization/92351
* tree-vect-data-refs.c (vect_compute_data_ref_alignment): When we are
peeling the main loop for alignment, make sure to set the misalignment
of the epilogue's data references to DR_MISALIGNMENT_UNKNOWN.

gcc/testsuite/ChangeLog:
2019-11-08  Andre Vieira  <andre.simoesdiasvieira@arm.com>

PR tree-optimization/92351
* gcc.dg/vect/vect-peel-2.c: Disable epilogue vectorization and
split the source of this test to...
* gcc.dg/vect/vect-peel-2-src.c: ... This.
* gcc.dg/vect/vect-peel-2-epilogues.c: New test.

From-SVN: r277974

dbgcnt.def (ivopts_loop): Add.

2019-11-08  Richard Biener  <rguenther@suse.de>

* dbgcnt.def (ivopts_loop): Add.
* tree-ssa-loop-ivopts.c (tree_ssa_iv_optimize): Check
ivopts_loop before optimizing a loop.

From-SVN: r277973

re PR ipa/92409 (r277920 causes ICE in gcc.dg/cast-function-1.c)

2019-11-08  Richard Biener  <rguenther@suse.de>

PR ipa/92409
* tree-inline.c (declare_return_variable): Properly handle
type mismatches for the return slot.

From-SVN: r277972

overflow-1.c: Add -fno-pie to the options.

* gcc.target/sparc/overflow-1.c: Add -fno-pie to the options.
* gcc.target/sparc/overflow-2.c: Likewise.

From-SVN: r277969

re PR target/92095 (internal error with -O1 -mcpu=niagara2 -fPIE)

PR target/92095
* config/sparc/sparc-protos.h (output_load_pcrel_sym): Declare.
* config/sparc/sparc.c (sparc_cannot_force_const_mem): Revert latest
  change.
(got_helper_needed): New static variable.
(output_load_pcrel_sym): New function.
(get_pc_thunk_name): Remove after inlining...
(load_got_register): ...here.  Rework the initialization of the GOT
register and of the GOT helper.
(save_local_or_in_reg_p): Test the REGNO of the GOT register.
(sparc_file_end): Test got_helper_needed to decide whether the GOT
helper must be emitted.  Use output_asm_insn instead of fprintf.
(sparc_init_pic_reg): In PIC mode, always initialize the PIC register
if optimization is enabled.
* config/sparc/sparc.md (load_pcrel_sym<P:mode>): Emit the assembly
by calling output_load_pcrel_sym.

From-SVN: r277966

Fix code order in tree-sra.c:create_access

If get_ref_base_and_extent returns poly_int offsets or sizes,
tree-sra.c:create_access prevents SRA from being applied to the base.
However, we haven't verified by that point that we have a valid base
to disqualify.

This originally led to an ICE on the attached testcase, but it
no longer triggers there after the introduction of IPA SRA.

2019-11-08  Richard Sandiford  <richard.sandiford@arm.com>

gcc/
* tree-sra.c (create_access): Delay disqualifying the base
for poly_int values until we know we have a base.

gcc/testsuite/
* gcc.target/aarch64/sve/acle/general/inline_2.c: New test.

From-SVN: r277965

[vect] Disable vectorization of epilogues for loops with SIMDUID set

gcc/ChangeLog:
2019-11-08  Andre Vieira  <andre.simoesdiasvieira@arm.com>

* tree-vect-loop.c (vect_analyze_loop): Disable epilogue vectorization
for loops with SIMDUID set.  Enable epilogue vectorization for loops
with SIMDLEN set after finding a main loop with a VF that matches it.

From-SVN: r277964

re PR target/92038 (Extremely inefficient x86_64 code for trivally copyable types passed in registers.)

PR target/92038
* gimple-ssa-store-merging.c (find_constituent_stores): For return
value only, return non-NULL if there is a single non-clobber
constituent store even if there are constituent clobbers and return
one of clobber constituent stores if all constituent stores are
clobbers.
(split_group): Handle clobbers.
(imm_store_chain_info::output_merged_store): When computing
bzero_first, look after all clobbers at the start.  Don't count
clobber stmts in orig_num_stmts, except if the first orig store is
a clobber covering the whole area and split_stores cover the whole
area, consider equal number of stmts ok.  Punt if split_stores
contains only ->orig stores and their number plus number of original
clobbers is equal to original number of stmts.  For ->orig, look past
clobbers in the constituent stores.
(imm_store_chain_info::output_merged_stores): Don't remove clobber
stmts.
(rhs_valid_for_store_merging_p): Don't return false for clobber stmt
rhs.
(store_valid_for_store_merging_p): Allow clobber stmts.
(verify_clear_bit_region_be): Fix up a thinko in function comment.

* g++.dg/opt/store-merging-1.C: New test.
* g++.dg/opt/store-merging-2.C: New test.
* g++.dg/opt/store-merging-3.C: New test.

From-SVN: r277963

re PR middle-end/92384 (Empty class instances have different equal testing result among GCC versions)

PR c++/92384
* function.c (assign_parm_setup_block, assign_parm_setup_stack): Don't
copy TYPE_EMPTY_P arguments from data->entry_parm to data->stack_parm
slot.
(assign_parms): For TREE_ADDRESSABLE parms with TYPE_EMPTY_P type
force creation of a unique data.stack_parm slot.

* g++.dg/torture/pr92384.C: New test.

From-SVN: r277962

genmatch.c (expr::gen_transform): Use the resimplify member function instead of hard-coding the...

2019-11-08  Richard Biener  <rguenther@suse.de>

* genmatch.c (expr::gen_transform): Use the resimplify
member function instead of hard-coding the gimple_resimplifyN variant.
(dt_simplify::gen_1): Likewise.

From-SVN: r277961

Rename identifiers in a test-case.

2019-11-08  Martin Liska  <mliska@suse.cz>

* g++.dg/pr92339.C: Rename identifiers to something
more readable.

From-SVN: r277960

Handle POLY_INT_CST in copy_reference_ops_from_ref

2019-11-08  Richard Sandiford  <richard.sandiford@arm.com>

gcc/
* tree-ssa-sccvn.c (copy_reference_ops_from_ref): Handle
POLY_INT_CST.

gcc/testsuite/
* gcc.target/aarch64/sve/acle/general/deref_2.c: New test.
* gcc.target/aarch64/sve/acle/general/whilele_8.c: Likewise.
* gcc.target/aarch64/sve/acle/general/whilelt_4.c: Likewise.

From-SVN: r277959

re PR tree-optimization/92324 (ICE in expand_direct_optab_fn, at internal-fn.c:2890)

2019-11-08  Richard Biener  <rguenther@suse.de>

PR tree-optimization/92324
* tree-vect-loop.c (vect_create_epilog_for_reduction): Use
STMT_VINFO_REDUC_VECTYPE for all computations, inserting
sign-conversions as necessary.
(vectorizable_reduction): Reject conversions in the chain
that are not sign-conversions, base analysis on a non-converting
stmt and its operation sign.  Set STMT_VINFO_REDUC_VECTYPE.
* tree-vect-stmts.c (vect_stmt_relevant_p): Don't dump anything
for debug stmts.
* tree-vectorizer.h (_stmt_vec_info::reduc_vectype): New.
(STMT_VINFO_REDUC_VECTYPE): Likewise.

* gcc.dg/vect/pr92205.c: XFAIL.
* gcc.dg/vect/pr92324-1.c: New testcase.
* gcc.dg/vect/pr92324-2.c: Likewise.

From-SVN: r277958

Handle POLY_INT_CSTs in declare_return_value

SVE allows variable-length vectors to be returned by value,
which tripped the assert in declare_return_variable.

2019-11-08  Richard Sandiford  <richard.sandiford@arm.com>

gcc/
* tree-inline.c (declare_return_variable): Check for poly_int_tree_p
instead of INTEGER_CST.

gcc/testsuite/
* gcc.target/aarch64/sve/acle/general/inline_1.c: New test.

From-SVN: r277956

re PR tree-optimization/92324 (ICE in expand_direct_optab_fn, at internal-fn.c:2890)

2019-11-08  Richard Biener  <rguenther@suse.de>

PR tree-optimization/92324
* tree-vect-loop.c (vect_create_epilog_for_reduction): Use
STMT_VINFO_REDUC_VECTYPE for all computations, inserting
sign-conversions as necessary.
(vectorizable_reduction): Reject conversions in the chain
that are not sign-conversions, base analysis on a non-converting
stmt and its operation sign.  Set STMT_VINFO_REDUC_VECTYPE.
* tree-vect-stmts.c (vect_stmt_relevant_p): Don't dump anything
for debug stmts.
* tree-vectorizer.h (_stmt_vec_info::reduc_vectype): New.
(STMT_VINFO_REDUC_VECTYPE): Likewise.

* gcc.dg/vect/pr92205.c: XFAIL.
* gcc.dg/vect/pr92324-1.c: New testcase.
* gcc.dg/vect/pr92324-2.c: Likewise.

From-SVN: r277955

re PR target/92055 ([avr] Support 64-bit double)

PR target/92055
* config/avr/avr.opt (-mdouble=, -mlong-double=):
Fix a missing '-' when displaying these options in the
help screen.

From-SVN: r277954

[AArch64] Remove unused mode iterators

2019-11-08  Richard Sandiford  <richard.sandiford@arm.com>

gcc/
* config/aarch64/iterators.md (SVE_BH, SVE_BHS): Delete.

From-SVN: r277953

Make mklog more robust.

2019-11-08  Martin Liska  <mliska@suse.cz>

* mklog: The script fails for patches that contain:
'---param=foo=bar xyz'.

From-SVN: r277952

[AArch64] Don't handle bswap in aarch64_builtin_vectorized_function

aarch64_builtin_vectorized_function no longer needs to handle bswap*
since we have internal functions and optabs for all supported cases.

2019-11-08  Richard Sandiford  <richard.sandiford@arm.com>

gcc/
* config/aarch64/aarch64-builtins.c
(aarch64_builtin_vectorized_function): Remove bswap handling.

From-SVN: r277951

[C] Opt out of GNU vector extensions for built-in SVE types

The AArch64 port defines built-in SVE types at start-up under names
like __SVInt8_t.  These types are represented in the front end and
gimple as normal VECTOR_TYPEs and are code-generated as normal vectors.
However, we'd like to stop the frontends from treating them in the
same way as GNU-style ("vector_size") vectors, for several reasons:

(1) We allowed the GNU vector extensions to be mixed with Advanced SIMD
    vector types and it ended up causing a lot of confusion on big-endian
    targets.  Although SVE handles big-endian vectors differently from
    Advanced SIMD, there are still potential surprises; see the block
    comment near the head of aarch64-sve.md for details.

(2) One of the SVE vectors is a packed one-bit-per-element boolean vector.
    That isn't a combination the GNU vector extensions have supported
    before.  E.g. it means that vectors can no longer decompose to
    arrays for indexing, and that not all elements are individually
    addressable.  It also makes it less clear which order the initialiser
    should be in (lsb first, or bitfield ordering?).  We could define
    all that of course, but it seems a bit weird to go to the effort
    for this case when, given all the other reasons, we don't want the
    extensions anyway.

(3) The GNU vector extensions only provide full-vector operations,
    which is a very artifical limitation on a predicated architecture
    like SVE.

(4) The set of operations provided by the GNU vector extensions is
    relatively small, whereas the SVE intrinsics provide many more.

(5) It makes it easier to ensure that (with default options) code is
    portable between compilers without the GNU vector extensions having
    to become an official part of the SVE intrinsics spec.

(6) The length of the SVE types is usually not fixed at compile time,
    whereas the GNU vector extension is geared around fixed-length
    vectors.

    It's possible to specify the length of an SVE vector using the
    command-line option -msve-vector-bits=N, but in principle it should
    be possible to have functions compiled for different N in the same
    translation unit.  This isn't supported yet but would be very useful
    for implementing ifuncs.  Once mixing lengths in a translation unit
    is supported, the SVE types should represent the same type throughout
    the translation unit, just as GNU vector types do.

However, when -msve-vector-bits=N is in effect, we do allow conversions
between explicit GNU vector types of N bits and the corresponding SVE
types.  This doesn't undermine the intent of (5) because in this case
the use of GNU vector types is explicit and intentional.  It also doesn't
undermine the intent of (6) because converting between the types is just
a conditionally-supported operation.  In other words, the types still
represent the same types throughout the translation unit, it's just that
conversions between them are valid in cases where a certain precondition
is known to hold.  It's similar to the way that the SVE vector types are
defined throughout the translation unit but can only be used in functions
for which SVE is enabled.

The patch adds a new flag to tree_type_common to select this behaviour.
(We currently have 17 bits free.)  To avoid making the flag too specific
to vectors, I called it TYPE_INDIVISIBLE_P, to mean that the frontend
should not allow the components of the type to be accessed directly.
This could perhaps be useful in future for hiding the fact that a
type is an array, or for hiding the fields of a record or union.

The actual frontend changes are very simple, mostly just replacing
VECTOR_TYPE_P with gnu_vector_type_p in selected places.

One interesting case is:

  /* Need to convert condition operand into a vector mask.  */
  if (VECTOR_TYPE_P (TREE_TYPE (ifexp)))
    {
      tree vectype = TREE_TYPE (ifexp);
      tree elem_type = TREE_TYPE (vectype);
      tree zero = build_int_cst (elem_type, 0);
      tree zero_vec = build_vector_from_val (vectype, zero);
      tree cmp_type = build_same_sized_truth_vector_type (vectype);
      ifexp = build2 (NE_EXPR, cmp_type, ifexp, zero_vec);
    }

in build_conditional_expr.  This appears to be trying to support
elementwise conditions like "vec1 ? vec2 : vec3", which is something
the C++ frontend supports.  However, this code can never trigger AFAICT,
because "vec1" does not survive c_objc_common_truthvalue_conversion:

    case VECTOR_TYPE:
      error_at (location, "used vector type where scalar is required");
      return error_mark_node;

Even if it did, the operation should be a VEC_COND_EXPR rather
than a COND_EXPR.

I've therefore left that condition as-is, but added tests for the
"vec1 ? vec2 : vec3" case to make sure that we don't accidentally
allow it for SVE vectors in future.

2019-11-08  Richard Sandiford  <richard.sandiford@arm.com>

gcc/
* tree-core.h (tree_type_common::indivisible_p): New member variable.
* tree.h (TYPE_INDIVISIBLE_P): New macro.
* config/aarch64/aarch64-sve-builtins.cc (register_builtin_types):
Treat the vector types as indivisible.

gcc/c-family/
* c-common.h (gnu_vector_type_p): New function.
* c-common.c (c_build_vec_perm_expr): Require __builtin_shuffle
vectors to satisfy gnu_vector_type_p.
(c_build_vec_convert): Likewise __builtin_convertvector.
(convert_vector_to_array_for_subscript): Likewise when applying
implicit vector to array conversion.
(scalar_to_vector): Likewise when converting vector-scalar
operations to vector-vector operations.

gcc/c/
* c-convert.c (convert): Only handle vector conversions if one of
the types satisfies gnu_vector_type_p or if -flax-vector-conversions
allows it.
* c-typeck.c (build_array_ref): Only allow vector indexing if the
vectors satisfy gnu_vector_type_p.
(build_unary_op): Only allow unary operators to be applied to
vectors if they satisfy gnu_vector_type_p.
(digest_init): Only allow by-element initialization of vectors
if they satisfy gnu_vector_type_p.
(really_start_incremental_init): Likewise.
(push_init_level): Likewise.
(pop_init_level): Likewise.
(process_init_element): Likewise.
(build_binary_op): Only allow binary operators to be applied to
vectors if they satisfy gnu_vector_type_p.

gcc/testsuite/
* gcc.target/aarch64/sve/acle/general-c/gnu_vectors_1.c: New test.
* gcc.target/aarch64/sve/acle/general-c/gnu_vectors_2.c: Likewise.

From-SVN: r277950

Generalise gather and scatter optabs

The gather and scatter optabs required the vector offset to be
the integer equivalent of the vector mode being loaded or stored.
This patch generalises them so that the two vectors can have different
element sizes, although they still need to have the same number of
elements.

One consequence of this is that it's possible (if unlikely)
for two IFN_GATHER_LOADs to have the same arguments but different
return types.  E.g. the same scalar base and vector of 32-bit offsets
could be used to load 8-bit elements and to load 16-bit elements.
From just looking at the arguments, we could wrongly deduce that
they're equivalent.

I know we saw this happen at one point with IFN_WHILE_ULT,
and we dealt with it there by passing a zero of the return type
as an extra argument.  Doing the same here also makes the load
and store functions have the same argument assignment.

For now this patch should be a no-op, but later SVE patches take
advantage of the new flexibility.

2019-11-08  Richard Sandiford  <richard.sandiford@arm.com>

gcc/
* optabs.def (gather_load_optab, mask_gather_load_optab)
(scatter_store_optab, mask_scatter_store_optab): Turn into
conversion optabs, with the offset mode given explicitly.
* doc/md.texi: Update accordingly.
* config/aarch64/aarch64-sve-builtins-base.cc
(svld1_gather_impl::expand): Likewise.
(svst1_scatter_impl::expand): Likewise.
* internal-fn.c (gather_load_direct, scatter_store_direct): Likewise.
(expand_scatter_store_optab_fn): Likewise.
(direct_gather_load_optab_supported_p): Likewise.
(direct_scatter_store_optab_supported_p): Likewise.
(expand_gather_load_optab_fn): Likewise.  Expect the mask argument
to be argument 4.
(internal_fn_mask_index): Return 4 for IFN_MASK_GATHER_LOAD.
(internal_gather_scatter_fn_supported_p): Replace the offset sign
argument with the offset vector type.  Require the two vector
types to have the same number of elements but allow their element
sizes to be different.  Treat the optabs as conversion optabs.
* internal-fn.h (internal_gather_scatter_fn_supported_p): Update
prototype accordingly.
* optabs-query.c (supports_at_least_one_mode_p): Replace with...
(supports_vec_convert_optab_p): ...this new function.
(supports_vec_gather_load_p): Update accordingly.
(supports_vec_scatter_store_p): Likewise.
* tree-vectorizer.h (vect_gather_scatter_fn_p): Take a vec_info.
Replace the offset sign and bits parameters with a scalar type tree.
* tree-vect-data-refs.c (vect_gather_scatter_fn_p): Likewise.
Pass back the offset vector type instead of the scalar element type.
Allow the offset to be wider than the memory elements.  Search for
an offset type that the target supports, stopping once we've
reached the maximum of the element size and pointer size.
Update call to internal_gather_scatter_fn_supported_p.
(vect_check_gather_scatter): Update calls accordingly.
When testing a new scale before knowing the final offset type,
check whether the scale is supported for any signed or unsigned
offset type.  Check whether the target supports the source and
target types of a conversion before deciding whether to look
through the conversion.  Record the chosen offset_vectype.
* tree-vect-patterns.c (vect_get_gather_scatter_offset_type): Delete.
(vect_recog_gather_scatter_pattern): Get the scalar offset type
directly from the gs_info's offset_vectype instead.  Pass a zero
of the result type to IFN_GATHER_LOAD and IFN_MASK_GATHER_LOAD.
* tree-vect-stmts.c (check_load_store_masking): Update call to
internal_gather_scatter_fn_supported_p, passing the offset vector
type recorded in the gs_info.
(vect_truncate_gather_scatter_offset): Update call to
vect_check_gather_scatter, leaving it to search for a valid
offset vector type.
(vect_use_strided_gather_scatters_p): Convert the offset to the
element type of the gs_info's offset_vectype.
(vect_get_gather_scatter_ops): Get the offset vector type directly
from the gs_info.
(vect_get_strided_load_store_ops): Likewise.
(vectorizable_load): Pass a zero of the result type to IFN_GATHER_LOAD
and IFN_MASK_GATHER_LOAD.
* config/aarch64/aarch64-sve.md (gather_load<mode>): Rename to...
(gather_load<mode><v_int_equiv>): ...this.
(mask_gather_load<mode>): Rename to...
(mask_gather_load<mode><v_int_equiv>): ...this.
(scatter_store<mode>): Rename to...
(scatter_store<mode><v_int_equiv>): ...this.
(mask_scatter_store<mode>): Rename to...
(mask_scatter_store<mode><v_int_equiv>): ...this.

From-SVN: r277949

Fortran] PR91253 fix continuation-line handling with -pre_include

        PR fortran/91253
        * scanner.c (skip_fixed_comments): Move comment
        lines to next if block.
        (gfc_next_char_literal): Fix continue_line setting.
        (get_file): Remove bogus ATTRIBUTE_UNUSED.

From-SVN: r277948

[rs6000]Fix PR92132 by adding vec_cmp and vcond_mask supports

  To support full condition reduction vectorization, we have to define
  vec_cmp* and vcond_mask_*.  This patch is to add related expands.
  Also add the missing vector fp comparison RTL pattern supports
  like: ungt, unge, unlt, unle, ne, lt and le.

gcc/ChangeLog

2019-11-08  Kewen Lin  <linkw@gcc.gnu.org>

    PR target/92132
    * config/rs6000/predicates.md
    (signed_or_equality_comparison_operator): New predicate.
    (unsigned_or_equality_comparison_operator): Likewise.
    * config/rs6000/rs6000.md (one_cmpl<mode>2): Remove expand.
    (one_cmpl<mode>3_internal): Rename to one_cmpl<mode>2.
    * config/rs6000/vector.md
    (vcond_mask_<mode><mode> for VEC_I and VEC_I): New expand.
    (vec_cmp<mode><mode> for VEC_I and VEC_I): Likewise.
    (vec_cmpu<mode><mode> for VEC_I and VEC_I): Likewise.
    (vcond_mask_<mode><VEC_int> for VEC_F): New expand for float
    vector modes and same-size integer vector modes.
    (vec_cmp<mode><VEC_int> for VEC_F): Likewise.
    (vector_lt<mode> for VEC_F): New expand.
    (vector_le<mode> for VEC_F): Likewise.
    (vector_ne<mode> for VEC_F): Likewise.
    (vector_unge<mode> for VEC_F): Likewise.
    (vector_ungt<mode> for VEC_F): Likewise.
    (vector_unle<mode> for VEC_F): Likewise.
    (vector_unlt<mode> for VEC_F): Likewise.
    (vector_uneq<mode>): Expose name.
    (vector_ltgt<mode>): Likewise.
    (vector_unordered<mode>): Likewise.
    (vector_ordered<mode>): Likewise.

gcc/testsuite/ChangeLog

2019-11-08  Kewen Lin  <linkw@gcc.gnu.org>

    PR target/92132
    * gcc.target/powerpc/pr92132-fp-1.c: New test.
    * gcc.target/powerpc/pr92132-fp-2.c: New test.
    * gcc.target/powerpc/pr92132-int-1.c: New test.
    * gcc.target/powerpc/pr92132-int-2.c: New test.

From-SVN: r277947

Fix inefficient vector constructor.

Changelog
gcc/
PR target/92295
* config/i386/i386-expand.c (ix86_expand_vector_init_concat)
Enhance ix86_expand_vector_init_concat.

gcc/testsuite
* gcc.target/i386/pr92295.c: New test.

From-SVN: r277946

Handle removal of old-style function definitions in C2x.

C2x removes support for old-style function definitions with identifier
lists, changing () in function definitions to be equivalent to (void)
(while () in declarations that are not definitions still gives an
unprototyped type).

This patch updates GCC accordingly.  The new semantics for () are
implemented for C2x mode (meaning () in function definitions isn't
diagnosed by -Wold-style-definition in that mode).
-Wold-style-definition is enabled by default, and turned into a
pedwarn, for C2x.

Bootstrapped with no regressions on x86_64-pc-linux-gnu.

gcc:
* doc/invoke.texi (-Wold-style-definition): Document () not being
considered an old-style definition for C2x.

gcc/c:
* c-decl.c (grokparms): Convert () in a function definition to
(void) for C2x.
(store_parm_decls_oldstyle): Pedwarn for C2x.
(store_parm_decls): Update comment about () not generating a
prototype.

gcc/c-family:
* c.opt (Wold-style-definition): Initialize to -1.
* c-opts.c (c_common_post_options): Set warn_old_style_definition
to flag_isoc2x if not set explicitly.

gcc/testsuite:
* gcc.dg/c11-old-style-definition-1.c,
gcc.dg/c11-old-style-definition-2.c,
gcc.dg/c2x-old-style-definition-1.c,
gcc.dg/c2x-old-style-definition-2.c,
gcc.dg/c2x-old-style-definition-3.c,
gcc.dg/c2x-old-style-definition-4.c,
gcc.dg/c2x-old-style-definition-5.c,
gcc.dg/c2x-old-style-definition-6.c: New tests.

From-SVN: r277945

libsupc++: add <compare> to precompiled header

Also process it with Doxygen.

* doc/doxygen/user.cfg.in (INPUT): Add <compare> header.
* include/precompiled/stdc++.h: Include <compare> header.

From-SVN: r277944

libstdc++: define std::common_comparison_category for C++20

* libsupc++/compare (common_comparison_category)
(common_comparison_category_t): Define for C++20.
* testsuite/18_support/comparisons/common/1.cc: New test.

From-SVN: r277943

Add another test case to exercise the previous MODE_PARTIAL_INT change.

gcc/testsuite/
PR other/92090
* gcc.target/powerpc/pr92090-2.c: New test.

From-SVN: r277942

pa.md (memory_barrier): Revise to use ldcw barriers.

* config/pa/pa.md (memory_barrier): Revise to use ldcw barriers.
Enhance comment.
(memory_barrier_coherent, memory_barrier_64, memory_barrier_32): New
insn patterns using ldcw instruction.
(memory_barrier): Remove insn pattern using sync instruction.
* config/pa/pa.opt (coherent-ldcw): New option.
(ordered): New option.

From-SVN: r277941

Daily bump.

From-SVN: r277940

rs6000: Remove no longer correct assert

After the simplify-rtx patch, we can now be asked about conditions we
wouldn't be asked about before.  This is perfectly fine, except we
have a little over-eager assert.  Remove that one.

* config/rs6000/rs6000.c (validate_condition_mode): Don't assert for
valid conditions.

From-SVN: r277936

Expand C2x attribute parsing support and factor out from TM attributes.

There is one place in the C parser that already handles a subset of
the C2x [[]] attribute syntax: c_parser_transaction_attributes.

This patch factors C2x attribute parsing out of there, extending it to
cover the full C2x attribute syntax (although currently only called
from that one place in the parser - so this is another piece of
preparation for supporting C2x attributes in the places where C2x says
they are valid, not the patch that actually enables such support).
The new C2X attribute parsing code uses the same representation for
scoped attributes as C++ does, so requiring parse_tm_stmt_attr to
handle the scoped attributes representation (C++ currently
special-cases TM attributes "to avoid the pedwarn in C++98 mode"; in C
I'm using an argument to c_parser_std_attribute_specifier to disable
the pedwarn_c11 call in the TM case).

Parsing of arguments to known attributes is shared by GNU and C2x
attributes.  C2x specifies that unknown attributes are ignored (GCC
practice in such a case is to warn along with ignoring the attribute)
and gives a very general balanced-token-sequence syntax for arguments
to unknown attributes (known ones each have their own syntax which is
a subset of balanced-token-sequence), so support is added for parsing
and ignoring such balanced-token-sequences as arguments of unknown
attributes.

Some limited tests are added of different attribute usages in the TM
attribute case.  The cases that become valid in the TM case include
extra commas inside [[]], and an explicit "gnu" namespace, as the
extra commas have no semantic effect for C2x attributes, while
accepting the "gnu" namespace seems appropriate because the attribute
in question is accepted inside __attribute__ (()), which is considered
equivalent to the "gnu" namespace inside [[]].

Bootstrapped with no regressions on x86_64-pc-linux-gnu.

gcc/c:
* c-parser.c (c_parser_attribute_arguments): New function.
Factored out of c_parser_gnu_attribute.
(c_parser_gnu_attribute): Use c_parser_attribute_arguments.
(c_parser_balanced_token_sequence, c_parser_std_attribute)
(c_parser_std_attribute_specifier): New functions.
(c_parser_transaction_attributes): Use
c_parser_std_attribute_specifier.

gcc/c-family:
* c-attribs.c (parse_tm_stmt_attr): Handle scoped attributes.

gcc/testsuite:
* gcc.dg/tm/attrs-1.c: New test.
* gcc.dg/tm/props-5.c: New test.  Based on props-4.c.

From-SVN: r277935

spaceship-scalar1-neg.C: Change dg-do from run to compile.

* g++.dg/cpp2a/spaceship-scalar1-neg.C: Change dg-do from run to
compile.

From-SVN: r277934

ipa-utils.c (ipa_merge_profiles): Fix fprintf format string typo - mistmatch -> mismatch.

* ipa-utils.c (ipa_merge_profiles): Fix fprintf format string
typo - mistmatch -> mismatch.
* ipa-profile.c (ipa_profile): Likewise.
* ipa-devirt.c (compare_virtual_tables): Fix a comment typo
- mistmatch -> mismatch.
cp/
* init.c (build_vec_delete_1): Fix a comment typo - mist -> must.

From-SVN: r277933

libstdc++: make negative count safe with std::for_each_n

The Library Working Group have approved a change to std::for_each_n that
requires it to handle negative N gracefully, which we were not doing for
random access iterators.

* include/bits/stl_algo.h (for_each_n): Handle negative count.
* testsuite/25_algorithms/for_each/for_each_n_debug.cc: New test.

From-SVN: r277932

simplify-rtx: simplify_logical_relational_operation

This introduces simplify_logical_relational_operation.  Currently the
only thing implemented it can simplify is the IOR of two CONDs of the
same arguments.

* simplify-rtx.c (comparison_to_mask): New function.
(mask_to_comparison): New function.
(simplify_logical_relational_operation): New function.
(simplify_binary_operation_1): Call
simplify_logical_relational_operation.

From-SVN: r277931

[Darwin, X86, testsuite] Fix pr92258.c.

This test uses -masm=intel, which isn't supported by Darwin.  Add the
necessary dg-require-effective-target.

gcc/testsuite/ChangeLog:

2019-11-07  Iain Sandoe  <iain@sandoe.co.uk>

* gcc.target/i386/pr92258.c: Add dg-requires for masm_intel.

From-SVN: r277930

PR c++/91370 - Implement P1041R4 and P1139R2 - Stronger Unicode reqs

PR c++/91370 - Implement P1041R4 and P1139R2 - Stronger Unicode reqs
* charset.c (narrow_str_to_charconst): Add TYPE argument.  For
CPP_UTF8CHAR diagnose whenever number of chars is > 1, using
CPP_DL_ERROR instead of CPP_DL_WARNING.
(wide_str_to_charconst): For CPP_CHAR16 or CPP_CHAR32, use
CPP_DL_ERROR instead of CPP_DL_WARNING when multiple char16_t
or char32_t chars are needed.
(cpp_interpret_charconst): Adjust narrow_str_to_charconst caller.

* g++.dg/cpp1z/utf8-neg.C: Expect errors rather than -Wmultichar
warnings.
* g++.dg/ext/utf16-4.C: Expect errors rather than warnings.
* g++.dg/ext/utf32-4.C: Likewise.
* g++.dg/cpp2a/ucn2.C: New test.

From-SVN: r277929

Allow MODE_PARTIAL_INT modes for integer constant input operands.

gcc/
PR other/92090
* config/rs6000/predicates.md (input_operand): Allow MODE_PARTIAL_INT
modes for integer constants.

gcc/testsuite/
PR other/92090
* gcc.target/powerpc/pr92090.c: New test.

From-SVN: r277928

re PR lto/92406 (ICE in ipa_call_summary at ipa-fnsummary.h:253 with lto and pgo)

PR ipa/92406
* ipa-fnsummary.c (analyze_function_body): Use get_create to copy
summary.

From-SVN: r277927

optc-save-gen.awk: Generate cl_target_option_free and cl_optimization_option_free.

* optc-save-gen.awk: Generate cl_target_option_free
and cl_optimization_option_free.
* opth-en.awk: Declare cl_target_option_free
and cl_optimization_option_free.
* tree.c (free_node): Use it.

From-SVN: r277926

Implement D1959R0, remove weak_equality and strong_equality.

Shortly after I finished implementing the previous semantics, the
committee decided to remove the *_equality comparison categories, because
they were largely obsoleted by the earlier change that separated operator==
from its original dependency on operator<=>.

gcc/cp/
* method.c (enum comp_cat_tag, comp_cat_info): Remove *_equality.
(genericize_spaceship, common_comparison_type): Likewise.
* typeck.c (cp_build_binary_op): Move SPACESHIP_EXPR to be with the
relational operators, exclude other types no longer supported.
libstdc++-v3/
* libsupc++/compare: Remove strong_equality and weak_equality.

From-SVN: r277925

lto-streamer-in.c: Include alloc-pool.h.

* lto-streamer-in.c: Include alloc-pool.h.
(freeing_string_slot_hasher): Remove.
(string_slot_allocator): New object allocator.
(file_name_hash_table): Turn to hash_table<string_slot_hasher>.
(file_name_obstack): New obstack.
(canon_file_name): Allocate in obstack and allocator.
(lto_reader_init): Initialize obstack and allocator.
(lto_free_file_name_hash): New function.
* lto-streamer.h (lto_free_file_name_hash): New.
* lto.c (do_whole_program_analysis): Call lto_free_file_name_hash.

From-SVN: r277924

Loop split on semi-invariant conditional statement

2019-11-07  Feng Xue <fxue@os.amperecomputing.com>

        PR tree-optimization/89134
        * doc/invoke.texi (min-loop-cond-split-prob): Document new --params.
        * params.def: Add min-loop-cond-split-prob.
        * tree-ssa-loop-split.c (split_loop): Remove niter parameter, move some
        outside checks on loop into the function.
        (split_info): New class.
        (find_vdef_in_loop, get_control_equiv_head_block): New functions.
        (find_control_dep_blocks, vuse_semi_invariant_p): Likewise.
        (ssa_semi_invariant_p, loop_iter_phi_semi_invariant_p): Likewise.
        (control_dep_semi_invariant_p, stmt_semi_invariant_p_1): Likewise.
        (stmt_semi_invariant_p, branch_removable_p): Likewise.
        (get_cond_invariant_branch, compute_added_num_insns): Likewise.
        (get_cond_branch_to_split_loop, do_split_loop_on_cond): Likewise.
        (split_loop_on_cond): Likewise.
        (tree_ssa_split_loops): Add loop split on conditional statement.

2019-11-07  Feng Xue  <fxue@os.amperecomputing.com>

        PR tree-optimization/89134
        * gcc.dg/tree-ssa/loop-cond-split-1.c: New test.
        * g++.dg/tree-ssa/loop-cond-split-1.C: New test.
        * gcc.dg/torture/pr55107.c: Add -fno-split-loops.

From-SVN: r277923

IBM Z: Add pattern for load truth value of comparison into reg

The RTXs used to express an overflow condition check in add/sub/mul are
too complex for if conversion.  However, there is code in
noce_emit_store_flag which generates a simple CC compare as the base
for using a conditional load.  All we have to do is to provide a
pattern to store the truth value of a CC compare into a GPR.

Done with the attached patch.

2019-11-07  Andreas Krebbel  <krebbel@linux.ibm.com>

* config/s390/s390.md ("*cstorecc<mode>_z13"): New insn_and_split
pattern.

gcc/testsuite/ChangeLog:

2019-11-07  Andreas Krebbel  <krebbel@linux.ibm.com>

* gcc.target/s390/addsub-signed-overflow-1.c: Expect lochi
instructions to be used.
* gcc.target/s390/addsub-signed-overflow-2.c: Likewise.
* gcc.target/s390/mul-signed-overflow-1.c: Likewise.
* gcc.target/s390/mul-signed-overflow-2.c: Likewise.
* gcc.target/s390/vector/vec-scalar-cmp-1.c: Check for 32 and 64
bit variant of lochi.  Swap the values for the lochi's.
* gcc.target/s390/zvector/vec-cmp-1.c: Likewise.

From-SVN: r277922

re PR tree-optimization/92405 (ICE in vect_get_vec_def_for_stmt_copy, at tree-vect-stmts.c:1683)

2019-11-07  Richard Biener  <rguenther@suse.de>

PR tree-optimization/92405
* tree-vect-loop.c (vectorizable_reduction): Appropriately
restrict lane-reducing ops to single stmt chains.

From-SVN: r277921

Remove gimple_call_types_likely_match_p (PR 70929)

2019-11-07  Martin Jambor  <mjambor@suse.cz>

PR lto/70929
* cif-code.def (MISMATCHED_ARGUMENTS): Removed.
* cgraph.h (gimple_check_call_matching_types): Remove
* cgraph.c (gimple_check_call_args): Likewise.
(gimple_check_call_matching_types): Likewise.
(symbol_table::create_edge): Do not call
gimple_check_call_matching_types.
(cgraph_edge::make_direct): Likewise.
(cgraph_edge::redirect_call_stmt_to_callee): Likewise.
* value-prof.h (check_ic_target): Remove.
* value-prof.c (check_ic_target): Remove.
(gimple_ic_transform): Do nat call check_ic_target.
* auto-profile.c (function_instance::find_icall_target_map): Likewise.
(afdo_indirect_call): Likewise.
* ipa-prop.c (update_indirect_edges_after_inlining): Do not call
gimple_check_call_matching_types.
* ipa-inline.c (early_inliner): Likewise.

testsuite/
* g++.dg/lto/pr70929_[01].C: New test.
* gcc.dg/winline-10.c: Adjust for the fact that inlining happens.

From-SVN: r277920

[arm][6/X] Add support for __[us]sat16 intrinsics

This last patch adds the the __ssat16 and __usat16 intrinsics that perform
"clipping" to a particular bitwidth on packed SIMD values, setting the Q bit
as appropriate.

* config/arm/arm.md (arm_<simd32_op>): New define_expand.
(arm_<simd32_op><add_clobber_q_name>_insn): New define_insn.
* config/arm/arm_acle.h (__ssat16, __usat16): Define.
* config/arm/arm_acle_builtins.def: Define builtins for the above.
* config/arm/iterators.md (USSAT16): New int_iterator.
(simd32_op): Handle UNSPEC_SSAT16, UNSPEC_USAT16.
(sup): Likewise.
* config/arm/predicates.md (ssat16_imm): New predicate.
(usat16_imm): Likewise.
* config/arm/unspecs.md (UNSPEC_SSAT16, UNSPEC_USAT16): Define.

* gcc.target/arm/acle/simd32.c: Update test.

From-SVN: r277919

[arm][5/X] Implement Q-bit-setting SIMD32 intrinsics

This patch implements some more Q-setting intrinsics of the
multiply-accumulate
variety, but these are in the SIMD32 family in that they treat their
operands as packed SIMD values, but that's not important at the RTL level.

* config/arm/arm.md (arm_<simd32_op><add_clobber_q_name>_insn):
New define_insns.
(arm_<simd32_op>): New define_expands.
* config/arm/arm_acle.h (__smlad, __smladx, __smlsd, __smlsdx,
__smuad, __smuadx): Define.
* config/arm/arm_acle_builtins.def: Define builtins for the above.
* config/arm/iterators.md (SIMD32_TERNOP_Q): New int_iterator.
(SIMD32_BINOP_Q): Likewise.
(simd32_op): Handle the above.
* config/arm/unspecs.md: Define unspecs for the above.

* gcc.target/arm/acle/simd32.c: Update test.

From-SVN: r277918

[arm][4/X] Add initial support for GE-setting SIMD32 intrinsics

This patch adds in plumbing for the ACLE intrinsics that set the GE bits in
APSR.  These are special SIMD instructions in Armv6 that pack bytes or
halfwords into the 32-bit general-purpose registers and set the GE bits in
APSR to indicate if some of the "lanes" of the result have overflowed or
have some other instruction-specific property.
These bits can then be used by the SEL instruction (accessed through the
__sel intrinsic) to select lanes for further processing.

This situation is similar to the Q-setting intrinsics: we have to track
the GE fake register, detect when a function reads it through __sel and restrict
existing patterns that may generate GE-clobbering instruction from
straight-line C code when reading the GE bits matters.

* config/arm/aout.h (REGISTER_NAMES): Add apsrge.
* config/arm/arm.md (APSRGE_REGNUM): Define.
(arm_<simd32_op>): New define_insn.
(arm_sel): Likewise.
* config/arm/arm.h (FIXED_REGISTERS): Add entry for apsrge.
(CALL_USED_REGISTERS): Likewise.
(REG_ALLOC_ORDER): Likewise.
(FIRST_PSEUDO_REGISTER): Update value.
(ARM_GE_BITS_READ): Define.
* config/arm/arm.c (arm_conditional_register_usage): Clear
APSRGE_REGNUM from operand_reg_set.
(arm_ge_bits_access): Define.
* config/arm/arm-builtins.c (arm_check_builtin_call): Handle
ARM_BUIILTIN_sel.
* config/arm/arm-protos.h (arm_ge_bits_access): Declare prototype.
* config/arm/arm-fixed.md (add<mode>3): Convert to define_expand.
FAIL if ARM_GE_BITS_READ.
(*arm_add<mode>3): New define_insn.
(sub<mode>3): Convert to define_expand.  FAIL if ARM_GE_BITS_READ.
(*arm_sub<mode>3): New define_insn.
* config/arm/arm_acle.h (__sel, __sadd8, __ssub8, __uadd8, __usub8,
__sadd16, __sasx, __ssax, __ssub16, __uadd16, __uasx, __usax,
__usub16): Define.
* config/arm/arm_acle_builtins.def: Define builtins for the above.
* config/arm/iterators.md (SIMD32_GE): New int_iterator.
(simd32_op): Handle the above.
* config/arm/unspecs.md (UNSPEC_GE_SET): Define.
(UNSPEC_SEL, UNSPEC_SADD8, UNSPEC_SSUB8, UNSPEC_UADD8, UNSPEC_USUB8,
UNSPEC_SADD16, UNSPEC_SASX, UNSPEC_SSAX, UNSPEC_SSUB16, UNSPEC_UADD16,
UNSPEC_UASX, UNSPEC_USAX, UNSPEC_USUB16): Define.

* gcc.target/arm/acle/simd32.c: Update test.
* gcc.target/arm/acle/simd32_sel.c: New test.

From-SVN: r277917

[arm][3/X] Implement __smla* intrinsics (Q-setting)

This patch implements some more Q-setting intrinsics form the SMLA* group.
These can set the saturation bit on overflow in the accumulation step.
Like earlier, these have non-Q-setting RTL forms as well for when the
Q-bit read
is not needed.

* config/arm/arm.md (arm_smlabb_setq): New define_insn.
(arm_smlabb): New define_expand.
(*maddhisi4tb): Rename to...
(maddhisi4tb): ... This.
(*maddhisi4tt): Rename to...
(maddhisi4tt): ... This.
(arm_smlatb_setq): New define_insn.
(arm_smlatb): New define_expand.
(arm_smlatt_setq): New define_insn.
(arm_smlatt): New define_expand.
(arm_<smlaw_op><add_clobber_name>_insn): New define_insn.
(arm_<smlaw_op>): New define_expand.
* config/arm/arm_acle.h (__smlabb, __smlatb, __smlabt, __smlatt,
__smlawb, __smlawt): Define.
* config/arm_acle_builtins.def: Define builtins for the above.
* config/arm/iterators.md (SMLAWBT): New int_iterator.
(slaw_op): New int_attribute.
* config/arm/unspecs.md (UNSPEC_SMLAWB, UNSPEC_SMLAWT): Define.

* gcc.target/arm/acle/dsp_arith.c: Update test.

From-SVN: r277916

[arm][2/X] Implement __qadd, __qsub, __qdbl intrinsics

This patch implements some more Q-bit-setting intrinsics from ACLE.
With the plumbing from patch 1 in place they are a simple builtin->RTL
affair.

* config/arm/arm.md (arm_<ss_op>): New define_expand.
(arm_<ss_op><add_clobber_q_name>_insn): New define_insn.
* config/arm/arm_acle.h (__qadd, __qsub, __qdbl): Define.
* config/arm/arm_acle_builtins.def: Add builtins for qadd, qsub.
* config/arm/iterators.md (SSPLUSMINUS): New code iterator.
(ss_op): New code_attr.

* gcc.target/arm/acle/dsp_arith.c: New test.

From-SVN: r277915

[arm][1/X] Add initial support for saturation intrinsics

This patch adds the plumbing for and an implementation of the saturation
intrinsics from ACLE, in particular the __ssat, __usat intrinsics.
These intrinsics set the Q sticky bit in APSR if an overflow occurred.
ACLE allows the user to read that bit (within the same function, it's not
defined across function boundaries) using the __saturation_occurred
intrinsic
and reset it using __set_saturation_occurred.
Thus, if the user cares about the Q bit they would be using a flow such as:

__set_saturation_occurred (0); // reset the Q bit
...
__ssat (...) // Do some calculations involving __ssat
...
if (__saturation_occurred ()) // if Q bit set handle overflow
   ...

For the implementation this has a few implications:
* We must track the Q-setting side-effects of these instructions to make
sure
saturation reading/writing intrinsics are ordered properly.
This is done by introducing a new "apsrq" register (and associated
APSRQ_REGNUM) in a similar way to the "fake"" cc register.

* The RTL patterns coming out of these intrinsics can have two forms:
one where they set the APSRQ_REGNUM and one where they don't.
Which one is used depends on whether the function cares about reading the Q
flag. This is detected using the TARGET_CHECK_BUILTIN_CALL hook on the
__saturation_occurred, __set_saturation_occurred occurrences.
If no Q-flag read is present in the function we'll use the simpler
non-Q-setting form to allow for more aggressive scheduling and such.
If a Q-bit read is present then the Q-setting form is emitted.
To avoid adding two patterns for each intrinsic to the MD file we make
use of define_subst to auto-generate the Q-setting forms

* Some existing patterns already produce instructions that may clobber the
Q bit, but they don't model it (as we didn't care about that bit up till
now).
Since these patterns can be generated from straight-line C code they can
affect
the Q-bit reads from intrinsics. Therefore they have to be disabled when
a Q-bit read is present.  These are mostly patterns in arm-fixed.md that are
not very common anyway, but there are also a couple of widening
multiply-accumulate patterns in arm.md that can set the Q-bit during
accumulation.

There are more Q-setting intrinsics in ACLE, but these will be
implemented in
a more mechanical fashion once the infrastructure in this patch goes in.

* config/arm/aout.h (REGISTER_NAMES): Add apsrq.
* config/arm/arm.md (APSRQ_REGNUM): Define.
(add_setq): New define_subst.
(add_clobber_q_name): New define_subst_attr.
(add_clobber_q_pred): Likewise.
(maddhisi4): Change to define_expand.  Split into mult and add if
ARM_Q_BIT_READ.
(arm_maddhisi4): New define_insn.
(*maddhisi4tb): Disable for ARM_Q_BIT_READ.
(*maddhisi4tt): Likewise.
(arm_ssat): New define_expand.
(arm_usat): Likewise.
(arm_get_apsr): New define_insn.
(arm_set_apsr): Likewise.
(arm_saturation_occurred): New define_expand.
(arm_set_saturation): Likewise.
(*satsi_<SAT:code>): Rename to...
(satsi_<SAT:code><add_clobber_q_name>): ... This.
(*satsi_<SAT:code>_shift): Disable for ARM_Q_BIT_READ.
* config/arm/arm.h (FIXED_REGISTERS): Mark apsrq as fixed.
(CALL_USED_REGISTERS): Mark apsrq.
(FIRST_PSEUDO_REGISTER): Update value.
(REG_ALLOC_ORDER): Add APSRQ_REGNUM.
(machine_function): Add q_bit_access.
(ARM_Q_BIT_READ): Define.
* config/arm/arm.c (TARGET_CHECK_BUILTIN_CALL): Define.
(arm_conditional_register_usage): Clear APSRQ_REGNUM from
operand_reg_set.
(arm_q_bit_access): Define.
* config/arm/arm-builtins.c: Include stringpool.h.
(arm_sat_binop_imm_qualifiers,
arm_unsigned_sat_binop_unsigned_imm_qualifiers,
arm_sat_occurred_qualifiers, arm_set_sat_qualifiers): Define.
(SAT_BINOP_UNSIGNED_IMM_QUALIFIERS,
UNSIGNED_SAT_BINOP_UNSIGNED_IMM_QUALIFIERS, SAT_OCCURRED_QUALIFIERS,
SET_SAT_QUALIFIERS): Likewise.
(arm_builtins): Define ARM_BUILTIN_SAT_IMM_CHECK.
(arm_init_acle_builtins): Initialize __builtin_sat_imm_check.
Handle 0 argument expander.
(arm_expand_acle_builtin): Handle ARM_BUILTIN_SAT_IMM_CHECK.
(arm_check_builtin_call): Define.
* config/arm/arm.md (ssmulsa3, usmulusa3, usmuluha3,
arm_ssatsihi_shift, arm_usatsihi): Disable when ARM_Q_BIT_READ.
* config/arm/arm-protos.h (arm_check_builtin_call): Declare prototype.
(arm_q_bit_access): Likewise.
* config/arm/arm_acle.h (__ssat, __usat, __ignore_saturation,
__saturation_occurred, __set_saturation_occurred): Define.
* config/arm/arm_acle_builtins.def: Define builtins for ssat, usat,
saturation_occurred, set_saturation_occurred.
* config/arm/unspecs.md (UNSPEC_Q_SET): Define.
(UNSPEC_APSR_READ): Likewise.
(VUNSPEC_APSR_WRITE): Likewise.
* config/arm/arm-fixed.md (ssadd<mode>3): Convert to define_expand.
(*arm_ssadd<mode>3): New define_insn.
(sssub<mode>3): Convert to define_expand.
(*arm_sssub<mode>3): New define_insn.
(ssmulsa3): Convert to define_expand.
(*arm_ssmulsa3): New define_insn.
(usmulusa3): Convert to define_expand.
(*arm_usmulusa3): New define_insn.
(ssmulha3): FAIL if ARM_Q_BIT_READ.
(arm_ssatsihi_shift, arm_usatsihi): Disable for ARM_Q_BIT_READ.
* config/arm/iterators.md (qaddsub_clob_q): New mode attribute.

* gcc.target/arm/acle/saturation.c: New test.
* gcc.target/arm/acle/sat_no_smlatb.c: Likewise.
* lib/target-supports.exp (check_effective_target_arm_qbit_ok_nocache):
Define..
(check_effective_target_arm_qbit_ok): Likewise.
(add_options_for_arm_qbit): Likewise.

From-SVN: r277914

Clear version_info_node in delete_function_version.

2019-11-07  Martin Liska  <mliska@suse.cz>

PR c++/92354
* cgraph.c (delete_function_version): Clear global
variable version_info_node if equal to deleted
function.
2019-11-07  Martin Liska  <mliska@suse.cz>

PR c++/92354
* g++.target/i386/pr92354.C: New test.

From-SVN: r277913

Add CONSTRUCTOR_NO_CLEARING to operand_equal_p.

2019-11-07  Martin Liska  <mliska@suse.cz>

* fold-const.c (operand_compare::operand_equal_p): Add comparison
of CONSTRUCTOR_NO_CLEARING.
(operand_compare::hash_operand): Likewise.

From-SVN: r277912

Update LOCAL_PATCHES.

From-SVN: r277911

Reapply all revisions mentioned in LOCAL_PATCHES.

2019-11-07  Martin Liska  <mliska@suse.cz>

* all source files: Reapply all revisions mentioned in LOCAL_PATCHES.

From-SVN: r277910

Libsanitizer: merge from trunk

2019-11-07  Martin Liska  <mliska@suse.cz>

* merge.sh: Update to use llvm-project git repository.
* all source files: Merge from upstream
82588e05cc32bb30807e480abd4e689b0dee132a.

From-SVN: r277909

Support 64-bit double and 64-bit long double configurations.

gcc/
Support 64-bit double and 64-bit long double configurations.

PR target/92055
* config.gcc (tm_defines) [avr]: Set from --with-double=,
--with-long-double=.
* config/avr/t-multilib: Remove.
* config/avr/t-avr: Output of genmultilib.awk is now fully
dynamically generated and no more part of the repo.
(HAVE_DOUBLE_MULTILIB, HAVE_LONG_DOUBLE_MULTILIB): New variables.
Pass them down to...
* config/avr/genmultilib.awk: ...here and handle them.
* gcc/config/avr/avr.opt (-mdouble=, avr_double). New option and var.
(-mlong-double=, avr_long_double). New option and var.
* common/config/avr/avr-common.c (opts.h, diagnostic.h): Include.
(TARGET_OPTION_OPTIMIZATION_TABLE) <-mdouble=, -mlong-double=>:
Set default as requested by --with-double=
(TARGET_HANDLE_OPTION): Define to this...
(avr_handle_option): ...new hook worker.
* config/avr/avr.h (DOUBLE_TYPE_SIZE): Define to avr_double.
(LONG_DOUBLE_TYPE_SIZE): Define to avr_long_double.
(avr_double_lib): New proto for spec function.
(EXTRA_SPEC_FUNCTIONS) <double-lib>: Add.
(DRIVER_SELF_SPECS): Call %:double-lib.
* config/avr/avr.c (avr_option_override): Assert
sizeof(long double) >= sizeof(double) for the target.
* config/avr/avr-c.c (avr_cpu_cpp_builtins)
[__HAVE_DOUBLE_MULTILIB__, __HAVE_LONG_DOUBLE_MULTILIB__]
[__HAVE_DOUBLE64__, __HAVE_DOUBLE32__, __DEFAULT_DOUBLE__=]
[__HAVE_LONG_DOUBLE64__, __HAVE_LONG_DOUBLE32__]
[__HAVE_LONG_DOUBLE_IS_DOUBLE__, __DEFAULT_LONG_DOUBLE__=]:
New built-in define depending on --with-double=, --with-long-double=.
* config/avr/driver-avr.c (avr_double_lib): New spec function.
* doc/invoke.tex (AVR Options) <-mdouble=,-mlong-double=>: Doc.
* doc/install.texi (Cross-Compiler-Specific Options)
<--with-double=, --with-long-double=>: Doc.

libgcc/
Support 64-bit double and 64-bit long double configurations.

PR target/92055
* config/avr/t-avr (HOST_LIBGCC2_CFLAGS): Only add -DF=SF if
long double is a 32-bit type.
* config/avr/t-avrlibc: Copy double64 and long-double64
multilib(s) from the vanilla one.
* config/avr/t-copy-libgcc: New Makefile snip.

From-SVN: r277908

dbgcnt.def (gimple_unroll): New.

2019-11-07  Richard Biener  <rguenther@suse.de>

* dbgcnt.def (gimple_unroll): New.
* tree-ssa-loop-ivcanon.c (try_unroll_loop_completely): Check
gimple_unroll debug counter before applying transform.
(try_peel_loop): Likewise.

From-SVN: r277907

Adjust pr92163.c test to require effective target fopenacc.

2019-11-07  Prathamesh Kulkarni  <prathamesh.kulkarni@linaro.org>

testsuite/
* gcc.dg/tree-ssa/pr92163.c: Add dg-require-effective-target fopenacc.

From-SVN: r277906

re PR libfortran/90374 (Fortran 2018: Support d0.d, e0.d, es0.d, en0.d, g0.d and ew.d e0 edit descriptors for output)

2019-11-06  Jerry DeLisle  <jvdelisle@gcc.ngu.org>

PR fortran/90374
* io.c (check_format): Allow zero width for D, E, EN, and ES
specifiers as default and when -std=F2018 is given. Retain
existing errors when using the -fdec family of flags.

* libgfortran/io/format.c (parse_format_list): Relax format checking for
zero width as default and when -std=f2018.
io/format.h (format_token): Move definition to io.h.
io/io.h (format_token): Add definition here to allow access to
this definition at higher levels. Rename the declaration of
write_real_g0 to write_real_w0 and add a new format_token
argument, allowing higher level functions to pass in the
token for handling of g0 vs the other zero width specifiers.
io/transfer.c (formatted_transfer_scalar_write): Add checks for
zero width and call write_real_w0 to handle it.
io/write.c (write_real_g0): Remove.
(write_real_w0): Add new, same as previous write_real_g0 except
check format token to handle the g0 case.

* gfortran.dg/fmt_error_10.f: Modify for new constraints.
* gfortran.dg/fmt_error_7.f: Add dg-options "-std=f95".
* gfortran.dg/fmt_error_9.f: Modify for new constraints.
* gfortran.dg/fmt_zero_width.f90: New test.

From-SVN: r277905