nmigen.git
5 years agotracer: factor out get_src_loc().
whitequark [Fri, 28 Dec 2018 01:31:24 +0000 (01:31 +0000)]
tracer: factor out get_src_loc().

5 years agolib.coding: fix tests to actually run, and fix code to fix tests.
whitequark [Thu, 27 Dec 2018 21:45:55 +0000 (21:45 +0000)]
lib.coding: fix tests to actually run, and fix code to fix tests.

5 years agohdl.dsl: add support for fsm.ongoing().
whitequark [Thu, 27 Dec 2018 16:02:31 +0000 (16:02 +0000)]
hdl.dsl: add support for fsm.ongoing().

5 years agohdl.mem: add missing __all__.
whitequark [Wed, 26 Dec 2018 17:15:54 +0000 (17:15 +0000)]
hdl.mem: add missing __all__.

5 years agocompat.genlib.coding: fix import.
Jean-François Nguyen [Wed, 26 Dec 2018 14:29:48 +0000 (15:29 +0100)]
compat.genlib.coding: fix import.

5 years agolib.coding: port from Migen.
whitequark [Wed, 26 Dec 2018 13:19:34 +0000 (13:19 +0000)]
lib.coding: port from Migen.

5 years agolib.cdc: add tests for MultiReg.
whitequark [Wed, 26 Dec 2018 12:58:30 +0000 (12:58 +0000)]
lib.cdc: add tests for MultiReg.

5 years agohdl.dsl: forbid m.next= inside of FSM but outside of FSM state, too.
whitequark [Wed, 26 Dec 2018 12:42:43 +0000 (12:42 +0000)]
hdl.dsl: forbid m.next= inside of FSM but outside of FSM state, too.

5 years agohdl.dsl: provide generated values for FSMs.
whitequark [Wed, 26 Dec 2018 12:39:05 +0000 (12:39 +0000)]
hdl.dsl: provide generated values for FSMs.

5 years agohdl.ir: add an API for retrieving generated values, like FSM signal.
whitequark [Wed, 26 Dec 2018 12:35:27 +0000 (12:35 +0000)]
hdl.ir: add an API for retrieving generated values, like FSM signal.

This is useful for tests.

5 years agoexamples: add an FSM usage example (UART receiver).
whitequark [Wed, 26 Dec 2018 10:10:27 +0000 (10:10 +0000)]
examples: add an FSM usage example (UART receiver).

5 years agohdl.dsl: add signal decoder to FSM state signal.
whitequark [Wed, 26 Dec 2018 09:45:12 +0000 (09:45 +0000)]
hdl.dsl: add signal decoder to FSM state signal.

5 years agohdl.dsl: implement FSM.
whitequark [Wed, 26 Dec 2018 08:55:04 +0000 (08:55 +0000)]
hdl.dsl: implement FSM.

5 years agoback.rtlil: clarify $verilog_initial_trigger behavior. NFC.
whitequark [Wed, 26 Dec 2018 06:45:57 +0000 (06:45 +0000)]
back.rtlil: clarify $verilog_initial_trigger behavior. NFC.

5 years agoback.rtlil: unbreak d47c1f8a.
whitequark [Mon, 24 Dec 2018 19:11:07 +0000 (19:11 +0000)]
back.rtlil: unbreak d47c1f8a.

5 years agohdl.mem: allow omitting memory simulation logic.
whitequark [Mon, 24 Dec 2018 09:31:51 +0000 (09:31 +0000)]
hdl.mem: allow omitting memory simulation logic.

Trying to transform very large arrays is slow.

5 years agoback.rtlil: use one $meminit cell, not one per word.
whitequark [Mon, 24 Dec 2018 09:30:47 +0000 (09:30 +0000)]
back.rtlil: use one $meminit cell, not one per word.

This is *far* more efficient.

5 years agohdl.xfrm, back.rtlil: implement and use LHSGroupFilter.
whitequark [Mon, 24 Dec 2018 02:17:28 +0000 (02:17 +0000)]
hdl.xfrm, back.rtlil: implement and use LHSGroupFilter.

This is a refactoring to simplify reusing the filtering code in
simulation, and separate that concern from backends in general.

5 years agohdl.xfrm: implement SwitchCleaner, for pruning empty switches.
whitequark [Mon, 24 Dec 2018 02:02:59 +0000 (02:02 +0000)]
hdl.xfrm: implement SwitchCleaner, for pruning empty switches.

5 years agoback.rtlil: always output negative values as two's complement.
whitequark [Mon, 24 Dec 2018 01:38:32 +0000 (01:38 +0000)]
back.rtlil: always output negative values as two's complement.

- is valid in RTLIL but means something entirely different.

5 years agoback.rtlil: emit dummy logic to work around Verilog deficiencies.
whitequark [Sun, 23 Dec 2018 10:14:05 +0000 (10:14 +0000)]
back.rtlil: emit dummy logic to work around Verilog deficiencies.

5 years agoback.rtlil: do not translate empty fragments.
whitequark [Sun, 23 Dec 2018 09:20:02 +0000 (09:20 +0000)]
back.rtlil: do not translate empty fragments.

The resulting Verilog confuses some frontends.

5 years agoback.rtlil: only translate switch tests once.
whitequark [Sun, 23 Dec 2018 07:17:33 +0000 (07:17 +0000)]
back.rtlil: only translate switch tests once.

This seems to affect synthesis with Yosys but only marginally.
It is mostly a speed and readability improvement.

5 years agocli: generate: guess file type from extension.
whitequark [Sun, 23 Dec 2018 07:13:17 +0000 (07:13 +0000)]
cli: generate: guess file type from extension.

5 years agoback.rtlil: fix swapped operands in mux codegen.
whitequark [Sun, 23 Dec 2018 06:47:38 +0000 (06:47 +0000)]
back.rtlil: fix swapped operands in mux codegen.

5 years agocli: new module, for basic design generaton/simulation.
whitequark [Sat, 22 Dec 2018 23:56:02 +0000 (23:56 +0000)]
cli: new module, for basic design generaton/simulation.

5 years agohdl.xfrm: avoid cycles in union-find graph in LHSGroupAnalyzer.
whitequark [Sat, 22 Dec 2018 22:19:14 +0000 (22:19 +0000)]
hdl.xfrm: avoid cycles in union-find graph in LHSGroupAnalyzer.

5 years agocompat.genlib.fsm: fix naming for non-Signal LHS.
whitequark [Sat, 22 Dec 2018 22:00:58 +0000 (22:00 +0000)]
compat.genlib.fsm: fix naming for non-Signal LHS.

5 years agohdl.ir: flatten hierarchy based on memory accesses, too.
whitequark [Sat, 22 Dec 2018 21:43:46 +0000 (21:43 +0000)]
hdl.ir: flatten hierarchy based on memory accesses, too.

5 years agohdl.ir: factor out _merge_subfragment. NFC.
whitequark [Sat, 22 Dec 2018 19:04:35 +0000 (19:04 +0000)]
hdl.ir: factor out _merge_subfragment. NFC.

5 years agoback.rtlil: split processes as finely as possible.
whitequark [Sat, 22 Dec 2018 10:03:16 +0000 (10:03 +0000)]
back.rtlil: split processes as finely as possible.

This makes simulation work correctly (by introducing delta cycles,
and therefore, making the overall Verilog simulation deterministic)
at the price of pessimizing mux trees generated by Yosys and Synplify
frontends, sometimes severely.

5 years agoback.rtlil: remove useless condition. NFC.
whitequark [Sat, 22 Dec 2018 07:24:15 +0000 (07:24 +0000)]
back.rtlil: remove useless condition. NFC.

5 years agohdl.xfrm: implement LHSGroupAnalyzer.
whitequark [Sat, 22 Dec 2018 06:50:32 +0000 (06:50 +0000)]
hdl.xfrm: implement LHSGroupAnalyzer.

5 years agohdl.xfrm: Abstract*Transformer→*Visitor
whitequark [Sat, 22 Dec 2018 06:03:38 +0000 (06:03 +0000)]
hdl.xfrm: Abstract*Transformer→*Visitor

5 years agoback.rtlil: always initialize the entire memory.
whitequark [Sat, 22 Dec 2018 05:27:42 +0000 (05:27 +0000)]
back.rtlil: always initialize the entire memory.

This avoids reading 'x from the memory in simulation. In general,
FPGA memories can only be initialized in block granularity, and
zero-initializing is cheap, so this is not a significant issue with
resource consumption.

5 years agocompat: use nicer names for next_value/next_value_ce signals.
whitequark [Sat, 22 Dec 2018 02:05:49 +0000 (02:05 +0000)]
compat: use nicer names for next_value/next_value_ce signals.

5 years agohdl.mem: allow changing init value after creating memory.
whitequark [Sat, 22 Dec 2018 01:09:03 +0000 (01:09 +0000)]
hdl.mem: allow changing init value after creating memory.

5 years agoback.verilog: do not rename internal signals.
whitequark [Sat, 22 Dec 2018 00:53:40 +0000 (00:53 +0000)]
back.verilog: do not rename internal signals.

_0_ is not really any better than \$13, and the latter at least has
continuity between nMigen, RTLIL and Verilog.

5 years agocompat: fix confusing naming for memory port address signal.
whitequark [Sat, 22 Dec 2018 00:53:05 +0000 (00:53 +0000)]
compat: fix confusing naming for memory port address signal.

5 years agohdl.ir: fix port propagation between siblings, in the other direction.
whitequark [Sat, 22 Dec 2018 00:31:31 +0000 (00:31 +0000)]
hdl.ir: fix port propagation between siblings, in the other direction.

5 years agocompat: do not finalize native submodules twice.
whitequark [Sat, 22 Dec 2018 00:02:31 +0000 (00:02 +0000)]
compat: do not finalize native submodules twice.

5 years agohdl.mem: use more informative signal naming for ports.
whitequark [Fri, 21 Dec 2018 23:55:02 +0000 (23:55 +0000)]
hdl.mem: use more informative signal naming for ports.

5 years agohdl.ir: fix port propagation between siblings.
whitequark [Fri, 21 Dec 2018 23:53:18 +0000 (23:53 +0000)]
hdl.ir: fix port propagation between siblings.

5 years agocompat: provide verilog.convert shim.
whitequark [Fri, 21 Dec 2018 13:53:06 +0000 (13:53 +0000)]
compat: provide verilog.convert shim.

5 years agohdl.ir: do not flatten instances or collect ports from their statements.
whitequark [Fri, 21 Dec 2018 13:52:18 +0000 (13:52 +0000)]
hdl.ir: do not flatten instances or collect ports from their statements.

This results in absurd behavior for memories.

5 years agocompat: provide Memory shim.
whitequark [Fri, 21 Dec 2018 13:15:52 +0000 (13:15 +0000)]
compat: provide Memory shim.

5 years agohdl.mem: ensure transparent read port model has correct latency.
whitequark [Fri, 21 Dec 2018 13:01:08 +0000 (13:01 +0000)]
hdl.mem: ensure transparent read port model has correct latency.

5 years agoback.pysim: handle out of bounds ArrayProxy indexes.
whitequark [Fri, 21 Dec 2018 12:32:08 +0000 (12:32 +0000)]
back.pysim: handle out of bounds ArrayProxy indexes.

5 years agoback.pysim: give numeric names to unnamed subfragments in VCD.
whitequark [Fri, 21 Dec 2018 12:29:33 +0000 (12:29 +0000)]
back.pysim: give numeric names to unnamed subfragments in VCD.

5 years agohdl.mem: use different naming for array signals.
whitequark [Fri, 21 Dec 2018 12:26:49 +0000 (12:26 +0000)]
hdl.mem: use different naming for array signals.

It looks like [] is confusing gtkwave somehow.

5 years agohdl.mem: add simulation model for memory.
whitequark [Fri, 21 Dec 2018 11:00:42 +0000 (11:00 +0000)]
hdl.mem: add simulation model for memory.

5 years agoback.pysim: fix an issue with too few funclet slots.
whitequark [Fri, 21 Dec 2018 10:25:28 +0000 (10:25 +0000)]
back.pysim: fix an issue with too few funclet slots.

5 years agohdl.mem: add tests for all error conditions.
whitequark [Fri, 21 Dec 2018 06:07:16 +0000 (06:07 +0000)]
hdl.mem: add tests for all error conditions.

5 years agohdl.mem: tie rdport.en high for asynchronous or transparent ports.
whitequark [Fri, 21 Dec 2018 04:22:16 +0000 (04:22 +0000)]
hdl.mem: tie rdport.en high for asynchronous or transparent ports.

5 years agoback.rtlil: more consistent prefixing for subfragment port wires.
whitequark [Fri, 21 Dec 2018 04:21:11 +0000 (04:21 +0000)]
back.rtlil: more consistent prefixing for subfragment port wires.

5 years agohdl.ir: correctly handle named output and inout ports.
whitequark [Fri, 21 Dec 2018 04:03:03 +0000 (04:03 +0000)]
hdl.ir: correctly handle named output and inout ports.

5 years agoback.rtlil: implement memories.
whitequark [Fri, 21 Dec 2018 01:55:59 +0000 (01:55 +0000)]
back.rtlil: implement memories.

5 years agohdl.mem: implement memories.
whitequark [Fri, 21 Dec 2018 01:53:32 +0000 (01:53 +0000)]
hdl.mem: implement memories.

5 years agoback.rtlil: explicitly pad constants with zeroes.
whitequark [Fri, 21 Dec 2018 01:51:18 +0000 (01:51 +0000)]
back.rtlil: explicitly pad constants with zeroes.

I'm not sure what exactly RTLIL does when a constant isn't as long
as its bit width, and there's no reason to keep the ambiguity.

5 years agoback.rtlil: fix translation of Cat.
whitequark [Fri, 21 Dec 2018 01:48:02 +0000 (01:48 +0000)]
back.rtlil: fix translation of Cat.

5 years agoir: allow non-Signals in Instance ports.
whitequark [Thu, 20 Dec 2018 23:38:01 +0000 (23:38 +0000)]
ir: allow non-Signals in Instance ports.

5 years agosetup: update pyvcd dependency, for var_type="string".
whitequark [Wed, 19 Dec 2018 17:17:25 +0000 (17:17 +0000)]
setup: update pyvcd dependency, for var_type="string".

5 years agocompat: import genlib.record from Migen.
whitequark [Tue, 18 Dec 2018 20:04:22 +0000 (20:04 +0000)]
compat: import genlib.record from Migen.

5 years agocompat: add wrappers for Slice.stop, Cat.l, _ArrayProxy.choices.
whitequark [Tue, 18 Dec 2018 20:02:32 +0000 (20:02 +0000)]
compat: add wrappers for Slice.stop, Cat.l, _ArrayProxy.choices.

5 years agohdl.ast: Cat.{operands→parts}
whitequark [Tue, 18 Dec 2018 19:15:44 +0000 (19:15 +0000)]
hdl.ast: Cat.{operands→parts}

5 years agoback.pysim: implement *.
whitequark [Tue, 18 Dec 2018 18:02:21 +0000 (18:02 +0000)]
back.pysim: implement *.

5 years agotest.sim: add tests for sync functionality and errors.
whitequark [Tue, 18 Dec 2018 17:53:50 +0000 (17:53 +0000)]
test.sim: add tests for sync functionality and errors.

5 years agoback.pysim: eliminate most dictionary lookups.
whitequark [Tue, 18 Dec 2018 15:28:27 +0000 (15:28 +0000)]
back.pysim: eliminate most dictionary lookups.

This makes the Glasgow testsuite about 30% faster.

5 years agohdl.ast, hdl.xfrm: various microoptimizations to speed up pysim.
whitequark [Tue, 18 Dec 2018 15:06:02 +0000 (15:06 +0000)]
hdl.ast, hdl.xfrm: various microoptimizations to speed up pysim.

5 years agoback.pysim: use arrays instead of dicts for signal values.
whitequark [Tue, 18 Dec 2018 05:19:12 +0000 (05:19 +0000)]
back.pysim: use arrays instead of dicts for signal values.

This makes the Glasgow testsuite about 40% faster.

5 years agoback.pysim: naming. NFC.
whitequark [Tue, 18 Dec 2018 04:46:36 +0000 (04:46 +0000)]
back.pysim: naming. NFC.

5 years agoback.pysim: fix an off-by-1 in add_sync_process().
whitequark [Tue, 18 Dec 2018 04:43:04 +0000 (04:43 +0000)]
back.pysim: fix an off-by-1 in add_sync_process().

5 years agoback.pysim: trigger processes waiting on Tick() exactly at clock edge.
whitequark [Tue, 18 Dec 2018 04:37:39 +0000 (04:37 +0000)]
back.pysim: trigger processes waiting on Tick() exactly at clock edge.

5 years agoback.pysim: continue running simulator processes until they suspend.
whitequark [Tue, 18 Dec 2018 03:05:16 +0000 (03:05 +0000)]
back.pysim: continue running simulator processes until they suspend.

5 years agoTravis: cache Yosys installation explicitly.
whitequark [Mon, 17 Dec 2018 23:46:46 +0000 (23:46 +0000)]
Travis: cache Yosys installation explicitly.

5 years agofhdl.ir: add black-box fragments, fragment parameters, and Instance.
whitequark [Mon, 17 Dec 2018 22:55:30 +0000 (22:55 +0000)]
fhdl.ir: add black-box fragments, fragment parameters, and Instance.

5 years agoTravis: build and cache Yosys.
whitequark [Mon, 17 Dec 2018 15:51:55 +0000 (15:51 +0000)]
Travis: build and cache Yosys.

5 years agohdl, back: add and use SignalSet/SignalDict.
whitequark [Mon, 17 Dec 2018 17:21:12 +0000 (17:21 +0000)]
hdl, back: add and use SignalSet/SignalDict.

5 years agohdl.ast: factor out _MappedKeyDict, _MappedKeySet. NFC.
whitequark [Mon, 17 Dec 2018 17:13:08 +0000 (17:13 +0000)]
hdl.ast: factor out _MappedKeyDict, _MappedKeySet. NFC.

5 years agoback.rtlil: update for Yosys master.
whitequark [Mon, 17 Dec 2018 15:50:43 +0000 (15:50 +0000)]
back.rtlil: update for Yosys master.

5 years agoback.rtlil: implement Array.
whitequark [Mon, 17 Dec 2018 01:15:23 +0000 (01:15 +0000)]
back.rtlil: implement Array.

5 years agoback.rtlil: implement Part.
whitequark [Mon, 17 Dec 2018 01:05:08 +0000 (01:05 +0000)]
back.rtlil: implement Part.

5 years agoback.rtlil: handle reset_less domains.
whitequark [Sun, 16 Dec 2018 23:52:47 +0000 (23:52 +0000)]
back.rtlil: handle reset_less domains.

5 years agohdl.dsl: add clock domain support.
whitequark [Sun, 16 Dec 2018 23:51:24 +0000 (23:51 +0000)]
hdl.dsl: add clock domain support.

5 years agohdl.dsl: cleanup. NFC.
whitequark [Sun, 16 Dec 2018 23:44:00 +0000 (23:44 +0000)]
hdl.dsl: cleanup. NFC.

5 years agoback.rtlil: extract _StatementCompiler. NFC.
whitequark [Sun, 16 Dec 2018 22:26:58 +0000 (22:26 +0000)]
back.rtlil: extract _StatementCompiler. NFC.

5 years agoback.rtlil: simplify. NFC.
whitequark [Sun, 16 Dec 2018 21:00:00 +0000 (21:00 +0000)]
back.rtlil: simplify. NFC.

5 years agoback.rtlil: properly escape strings in attributes.
whitequark [Sun, 16 Dec 2018 20:27:15 +0000 (20:27 +0000)]
back.rtlil: properly escape strings in attributes.

5 years agoREADME: mention Yosys requirement.
whitequark [Sun, 16 Dec 2018 18:09:01 +0000 (18:09 +0000)]
README: mention Yosys requirement.

5 years agoback.rtlil: prepare for Yosys sigspec slicing improvements.
whitequark [Sun, 16 Dec 2018 18:03:14 +0000 (18:03 +0000)]
back.rtlil: prepare for Yosys sigspec slicing improvements.

See YosysHQ/yosys#741.

5 years agocompat.fhdl.structure: only convert to bool in If/Elif if necessary.
whitequark [Sun, 16 Dec 2018 17:41:42 +0000 (17:41 +0000)]
compat.fhdl.structure: only convert to bool in If/Elif if necessary.

5 years agoback.rtlil: avoid illegal slices.
whitequark [Sun, 16 Dec 2018 17:41:11 +0000 (17:41 +0000)]
back.rtlil: avoid illegal slices.

Not sure what to do with {} [] on LHS yet--fix Yosys?

5 years agoback.rtlil: use slicing to match shape when reducing width.
whitequark [Sun, 16 Dec 2018 16:20:45 +0000 (16:20 +0000)]
back.rtlil: use slicing to match shape when reducing width.

5 years agoback.rtlil: don't emit a slice if all bits are used.
whitequark [Sun, 16 Dec 2018 16:05:38 +0000 (16:05 +0000)]
back.rtlil: don't emit a slice if all bits are used.

5 years agoback.rtlil: reorganize value compiler into LHS/RHS.
whitequark [Sun, 16 Dec 2018 13:30:20 +0000 (13:30 +0000)]
back.rtlil: reorganize value compiler into LHS/RHS.

This also implements Cat on LHS.

5 years agoback.rtlil: fix naming. NFC.
whitequark [Sun, 16 Dec 2018 11:26:31 +0000 (11:26 +0000)]
back.rtlil: fix naming. NFC.

5 years agohdl.xfrm: separate AST traversal from AST identity mapping.
whitequark [Sun, 16 Dec 2018 11:24:23 +0000 (11:24 +0000)]
hdl.xfrm: separate AST traversal from AST identity mapping.

This is useful because backends don't generally want or need AST
identity mapping (unlike all other transforms) and when adding a new
node, it results in confusing type errors.

5 years agocompat.fhdl: reexport Array.
whitequark [Sun, 16 Dec 2018 10:38:25 +0000 (10:38 +0000)]
compat.fhdl: reexport Array.

5 years agoback.pysim: implement LHS for Part, Slice, Cat, ArrayProxy.
whitequark [Sun, 16 Dec 2018 10:31:42 +0000 (10:31 +0000)]
back.pysim: implement LHS for Part, Slice, Cat, ArrayProxy.

5 years agotest.sim: generalize assertOperator. NFC.
whitequark [Sat, 15 Dec 2018 21:08:29 +0000 (21:08 +0000)]
test.sim: generalize assertOperator. NFC.