mesa.git
8 years agoi965: Remove pointers to non-existing atoms
Topi Pohjolainen [Fri, 22 Apr 2016 09:33:26 +0000 (12:33 +0300)]
i965: Remove pointers to non-existing atoms

Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
8 years agoradeonsi: Implement ddx/ddy on VI using ds_bpermute
Tom Stellard [Fri, 15 Apr 2016 23:42:10 +0000 (23:42 +0000)]
radeonsi: Implement ddx/ddy on VI using ds_bpermute

The ds_bpermute instruction allows threads to transfer data directly
to or from the vgprs of other threads.  These instructions use the LDS
hardware to transfer data, but do not read or write LDS memory.

DDX BEFORE:                        |  DDX AFTER:
                                   |
v_mbcnt_lo_u32_b32_e64 v2, -1, 0   |  v_mbcnt_lo_u32_b32_e64 v2, -1, 0
v_mbcnt_hi_u32_b32_e64 v2, -1, v2  |  v_mbcnt_hi_u32_b32_e64 v2, -1, v2
v_lshlrev_b32_e32 v4, 2, v2        |  v_and_b32_e32 v2, 60, v2
v_and_b32_e32 v2, 60, v2           |  v_lshlrev_b32_e32 v2, 2, v2
v_lshlrev_b32_e32 v3, 2, v2        |  ds_bpermute_b32 v3, v2, v0
s_mov_b32 m0, -1                   |  ds_bpermute_b32 v0, v2, v0 offset:4
ds_write_b32 v4, v0                |  s_waitcnt lgkmcnt(0)
s_waitcnt lgkmcnt(0)               |
v_or_b32_e32 v0, 1, v2             |
v_lshlrev_b32_e32 v0, 2, v0        |
ds_read_b32 v1, v3                 |
ds_read_b32 v0, v0                 |
s_waitcnt lgkmcnt(0)               |
                                   |
LDS: 1 blocks                      |  LDS: 0 blocks

Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
Acked-by: Marek Olšák <marek.olsak@amd.com>
8 years agoradeonsi: Use llvm.amdgcn.mbcnt.* intrinsics instead of llvm.SI.tid
Tom Stellard [Fri, 15 Apr 2016 22:53:38 +0000 (22:53 +0000)]
radeonsi: Use llvm.amdgcn.mbcnt.* intrinsics instead of llvm.SI.tid

We're trying to move to more of the new style intrinsics with include
the correct target name, and map directly to ISA instructions.

v2:
  - Only do this with LLVM 3.8 and newer.

Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
8 years agoradeonsi: Set range metadata on calls to llvm.SI.tid
Tom Stellard [Mon, 18 Apr 2016 18:33:43 +0000 (14:33 -0400)]
radeonsi: Set range metadata on calls to llvm.SI.tid

The range metadata tells LLVM the range of expected values for this intrinsic,
so it can do some additional optimizations on the result.

Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
8 years agoradeonsi: Create a helper function for computing the thread id
Tom Stellard [Mon, 18 Apr 2016 17:10:10 +0000 (13:10 -0400)]
radeonsi: Create a helper function for computing the thread id

Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
8 years agoi965: Disable KHR_texture_compression_astc_hdr on Gen9
Nanley Chery [Wed, 13 Apr 2016 00:34:49 +0000 (17:34 -0700)]
i965: Disable KHR_texture_compression_astc_hdr on Gen9

Although Gen9 samples from most HDR ASTC surfaces of correctly,
there currently are no software workarounds to fix the incorrect
sampling that occurs in others of certain color endpoint modes.

With this change, we are no longer failing the 14 tests from:
   dEQP-GLES3.functional.texture.compressed.astc.endpoint_value_hdr_cem_15.*

Signed-off-by: Nanley Chery <nanley.g.chery@intel.com>
Acked-by: Kenneth Graunke <kenneth@whitecape.org>
8 years agoswr: [rasterizer memory] Constify load tiles
Tim Rowley [Tue, 12 Apr 2016 23:24:18 +0000 (17:24 -0600)]
swr: [rasterizer memory] Constify load tiles

Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
8 years agoswr: [rasterizer core] CompleteDrawContext changes for gcc
Tim Rowley [Wed, 13 Apr 2016 01:28:50 +0000 (19:28 -0600)]
swr: [rasterizer core] CompleteDrawContext changes for gcc

Add explicit inline and non-inline versions of CompleteDrawContext
to make gcc happy.

Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
8 years agoswr: [rasterizer] Small cleanups
Tim Rowley [Wed, 6 Apr 2016 21:23:14 +0000 (15:23 -0600)]
swr: [rasterizer] Small cleanups

Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
8 years agoswr: [rasterizer scripts] Knob scripts tweaks
Tim Rowley [Wed, 6 Apr 2016 18:30:14 +0000 (12:30 -0600)]
swr: [rasterizer scripts] Knob scripts tweaks

Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
8 years agoswr: [rasterizer] Interpolation utility functions
Tim Rowley [Tue, 5 Apr 2016 22:33:02 +0000 (16:33 -0600)]
swr: [rasterizer] Interpolation utility functions

v2: use _mm_cmpunord_ps for vIsNaN

Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
8 years agoswr: [rasterizer core] TemplateArgUnroller
Tim Rowley [Tue, 5 Apr 2016 02:00:13 +0000 (20:00 -0600)]
swr: [rasterizer core] TemplateArgUnroller

Switch boolean template arguments to typename template arguments of type
std::integral_constant<bool, VALUE>.

This allows the template argument unroller to easily be extended to enums.

Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
8 years agoswr: [rasterizer core] Arena: make most allocated blocks the same size
Tim Rowley [Mon, 4 Apr 2016 23:16:35 +0000 (17:16 -0600)]
swr: [rasterizer core] Arena: make most allocated blocks the same size

Reduces sorting cost

Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
8 years agoswr: [rasterizer core] Fix global arena allocator bug
Tim Rowley [Mon, 4 Apr 2016 20:33:26 +0000 (14:33 -0600)]
swr: [rasterizer core] Fix global arena allocator bug

- Plus some minor code refactoring

Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
8 years agoswr: [rasterizer core] Fix thread binding for 32-bit windows
Tim Rowley [Mon, 4 Apr 2016 18:42:00 +0000 (12:42 -0600)]
swr: [rasterizer core] Fix thread binding for 32-bit windows

Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
8 years agoswr: [rasterizer fetch] Add support for fetching non-uniform component formats
Tim Rowley [Mon, 4 Apr 2016 05:54:50 +0000 (23:54 -0600)]
swr: [rasterizer fetch] Add support for fetching non-uniform component formats

For example, R10G10B10A2_UNORM.

Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
8 years agoswr: [rasterizer core] Use CS spill/fill size in core
Tim Rowley [Mon, 4 Apr 2016 05:20:58 +0000 (23:20 -0600)]
swr: [rasterizer core] Use CS spill/fill size in core

Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
8 years agoswr: fix memory leaks from vs/fs compilation
Tim Rowley [Thu, 21 Apr 2016 00:42:16 +0000 (19:42 -0500)]
swr: fix memory leaks from vs/fs compilation

v2: varient -> variant

Reviewed by: George Kyriazis <George.Kyriazis@intel.com>

8 years agoswr: fix clang warnings
Tim Rowley [Thu, 21 Apr 2016 16:50:40 +0000 (11:50 -0500)]
swr: fix clang warnings

v2: use alternate logic version in swr_check_render_cond

Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
8 years agofreedreno/a4xx: fix encoding of blend color state
Rob Clark [Fri, 22 Apr 2016 18:44:53 +0000 (14:44 -0400)]
freedreno/a4xx: fix encoding of blend color state

Fixes a whole bunch of dEQP-GLES3.functional.fragment_ops.random.* (now
they all pass)

Signed-off-by: Rob Clark <robclark@freedesktop.org>
8 years agofreedreno: update generated headers
Rob Clark [Fri, 22 Apr 2016 18:38:46 +0000 (14:38 -0400)]
freedreno: update generated headers

Pull in RB_BLEND_* fixes.

Signed-off-by: Rob Clark <robclark@freedesktop.org>
8 years agovc4: Make sure we recompile when sample_mask changes.
Eric Anholt [Thu, 21 Apr 2016 00:00:13 +0000 (17:00 -0700)]
vc4: Make sure we recompile when sample_mask changes.

Part of fixing piglit EXT_framebuffer_multisample/sample-coverage inverted
(there is also a bug with RCL tiled blits)

Cc: "11.1 11.2" <mesa-stable@lists.freedesktop.org>
8 years agovc4: Fix validation of full res tile offset if used for non-MSAA.
Eric Anholt [Mon, 14 Dec 2015 19:14:13 +0000 (11:14 -0800)]
vc4: Fix validation of full res tile offset if used for non-MSAA.

There's no reason we couldn't do non-MSAA full resolution tile buffer
load/stores, but we would have claimed buffer overflow was being
attempted.  Nothing does this currently.

8 years agovc4: Only do MSAA FB operations if the FB is MSAA.
Eric Anholt [Mon, 18 Apr 2016 23:57:53 +0000 (16:57 -0700)]
vc4: Only do MSAA FB operations if the FB is MSAA.

I noticed this as a problem with ET:QW traces emitting coverage code when
the framebuffer was supposed to be single sampled.

8 years agovc4: Fix tests for format supported with nr_samples == 1.
Eric Anholt [Wed, 20 Apr 2016 23:31:28 +0000 (16:31 -0700)]
vc4: Fix tests for format supported with nr_samples == 1.

This was a bug from the MSAA enabling.  Tests for surfaces with
nr_samples==1 instead of 0 (generally GL renderbuffers) would incorrectly
fail out.

Fixes the ARB_framebuffer_sRGB piglit tests other than srgb_conformance.

Cc: "11.1 11.2" <mesa-stable@lists.freedesktop.org>
8 years agovc4: Don't try to blit from MSAA surfaces with mismatched width to dst.
Eric Anholt [Wed, 20 Apr 2016 21:11:04 +0000 (14:11 -0700)]
vc4: Don't try to blit from MSAA surfaces with mismatched width to dst.

I had made the previous blit fix non-MSAA only because I was thinking
about how the hardware infers stride from the RENDERING_CONFIG packet.
However, I'm also inferring the stride for both MSAA src and dst in
vc4_render_cl.c from the width argument in the ioctl.

Fixes 15 EXT_framebuffer_multisample piglit tests.

8 years agoi965: Disable channel expressions for scalar GS, TCS, TES.
Kenneth Graunke [Wed, 20 Apr 2016 10:32:24 +0000 (03:32 -0700)]
i965: Disable channel expressions for scalar GS, TCS, TES.

On Broadwell, I get the following shader-db statistics:

Tessellation Control Shaders:

   total instructions in shared programs: 57327 -> 57012 (-0.55%)
   instructions in affected programs: 27334 -> 27019 (-1.15%)
   helped: 45
   HURT: 0

   total cycles in shared programs: 265692 -> 255188 (-3.95%)
   cycles in affected programs: 263122 -> 252618 (-3.99%)
   helped: 184
   HURT: 26

Tessellation Evaluation Shaders:

   total instructions in shared programs: 23236 -> 23157 (-0.34%)
   instructions in affected programs: 2791 -> 2712 (-2.83%)
   helped: 27
   HURT: 0

   total cycles in shared programs: 151858 -> 149704 (-1.42%)
   cycles in affected programs: 151858 -> 149704 (-1.42%)
   helped: 101
   HURT: 114

Geometry Shaders:

   Orbital Explorer goes from 6442 -> 6356 instructions.
   Two Shadow of Mordor shaders increase by a single instruction.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Matt Turner <mattst88@gmail.com>
8 years agoi965/blorp: Add support for 2x msaa
Topi Pohjolainen [Sat, 16 Apr 2016 17:03:34 +0000 (20:03 +0300)]
i965/blorp: Add support for 2x msaa

Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
8 years agoi965/blorp: Add support for encoding/decoding interleaved 2x msaa
Topi Pohjolainen [Sun, 17 Apr 2016 07:57:24 +0000 (10:57 +0300)]
i965/blorp: Add support for encoding/decoding interleaved 2x msaa

Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
8 years agoi965: don't lower mod() in glsl ir
Samuel Iglesias Gonsálvez [Tue, 12 Apr 2016 11:55:21 +0000 (13:55 +0200)]
i965: don't lower mod() in glsl ir

NIR will lower it in nir_opt_algebraic.

No change in shader-db.

Signed-off-by: Samuel Iglesias Gonsálvez <siglesias@igalia.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
8 years agoglsl: fix cross validation for explicit locations on structs and arrays
Timothy Arceri [Wed, 23 Dec 2015 23:33:45 +0000 (10:33 +1100)]
glsl: fix cross validation for explicit locations on structs and arrays

Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
8 years agoradeonsi: implement TGSI_SEMANTIC_HELPER_INVOCATION
Nicolai Hähnle [Sat, 16 Apr 2016 18:00:12 +0000 (13:00 -0500)]
radeonsi: implement TGSI_SEMANTIC_HELPER_INVOCATION

Depends on LLVM support introduced in r267102.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
8 years agoswr: ignore generated files in rasterizer
Ilia Mirkin [Fri, 15 Apr 2016 18:30:19 +0000 (14:30 -0400)]
swr: ignore generated files in rasterizer

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Tim Rowley <timothy.o.rowley@intel.com>
8 years agonvc0: fix retrieving query results into buffer for timestamps
Ilia Mirkin [Fri, 22 Apr 2016 04:01:56 +0000 (00:01 -0400)]
nvc0: fix retrieving query results into buffer for timestamps

The timestamps are stored in a funny place, and even though they are a
64-bit result, are not stored with is64bit. Account for that when
retrieving the query result into a resource.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Cc: "11.2" <mesa-stable@lists.freedesktop.org>
8 years agoi965/surface_state: Use libisl functions for image format lowering
Jason Ekstrand [Sat, 16 Apr 2016 20:25:24 +0000 (13:25 -0700)]
i965/surface_state: Use libisl functions for image format lowering

This lets us delete some redundant code and keep all of the
image_load_store format lowering logic in one place: libisl.

Reviewed-by: Chad Versace <chad.versace@intel.com>
8 years agoi965/fs_surface_builder: Use isl instead of mesa for format info
Jason Ekstrand [Sat, 16 Apr 2016 04:55:02 +0000 (21:55 -0700)]
i965/fs_surface_builder: Use isl instead of mesa for format info

Reviewed-by: Chad Versace <chad.versace@intel.com>
8 years agoi965/fs_surface_builder: Add a helper for converting GL to ISL formats
Jason Ekstrand [Fri, 15 Apr 2016 23:38:18 +0000 (16:38 -0700)]
i965/fs_surface_builder: Add a helper for converting GL to ISL formats

Reviewed-by: Chad Versace <chad.versace@intel.com>
8 years agoi965/fs_surface_builder: Explicitly handle FORMAT_NONE in num_image_coordinates
Jason Ekstrand [Wed, 4 Nov 2015 23:12:19 +0000 (15:12 -0800)]
i965/fs_surface_builder: Explicitly handle FORMAT_NONE in num_image_coordinates

Previously, we were relying on has_matching_typed_format returning true for
MESA_FORMAT_NONE which, in turn, relied on _mesa_get_format_bytes returning
1 for MESA_FORMAT_NONE.  When we switch to ISL, this behaviour will no
longer be something we can rely on.

Reviewed-by: Chad Versace <chad.versace@intel.com>
8 years agoi965/fs_surface_builder: Take a GL format enum instead of mesa_format
Jason Ekstrand [Fri, 15 Apr 2016 23:36:59 +0000 (16:36 -0700)]
i965/fs_surface_builder: Take a GL format enum instead of mesa_format

Reviewed-by: Chad Versace <chad.versace@intel.com>
8 years agoisl/format: Add a get_num_channels helper
Jason Ekstrand [Sat, 16 Apr 2016 04:36:21 +0000 (21:36 -0700)]
isl/format: Add a get_num_channels helper

Reviewed-by: Chad Versace <chad.versace@intel.com>
8 years agoisl/format: Add more isl_format_has_type_channel functions
Jason Ekstrand [Sat, 16 Apr 2016 04:31:47 +0000 (21:31 -0700)]
isl/format: Add more isl_format_has_type_channel functions

Reviewed-by: Chad Versace <chad.versace@intel.com>
8 years agoisl/format: Break the guts of has_[us]int_channel into a helper
Jason Ekstrand [Sat, 16 Apr 2016 04:25:00 +0000 (21:25 -0700)]
isl/format: Break the guts of has_[us]int_channel into a helper

Reviewed-by: Chad Versace <chad.versace@intel.com>
8 years agoanv/image: Use the has_matching_typed_storage_image_format helper from isl
Jason Ekstrand [Sat, 16 Apr 2016 00:08:18 +0000 (17:08 -0700)]
anv/image: Use the has_matching_typed_storage_image_format helper from isl

Reviewed-by: Chad Versace <chad.versace@intel.com>
8 years agoisl: Add a helper for determining when a typed load/store can be used
Jason Ekstrand [Sat, 16 Apr 2016 00:05:24 +0000 (17:05 -0700)]
isl: Add a helper for determining when a typed load/store can be used

Reviewed-by: Chad Versace <chad.versace@intel.com>
8 years agoisl: Take a devinfo in lower_storage_image_format instead of an isl_device
Jason Ekstrand [Fri, 15 Apr 2016 23:53:31 +0000 (16:53 -0700)]
isl: Take a devinfo in lower_storage_image_format instead of an isl_device

We want to call this function from the shader compiler and having a full
isl_device available at that point isn't practical.

Reviewed-by: Chad Versace <chad.versace@intel.com>
8 years agoisl: Don't use designated initializers in the header
Jason Ekstrand [Fri, 15 Apr 2016 23:32:33 +0000 (16:32 -0700)]
isl: Don't use designated initializers in the header

C++ doesn't support designated initializers and g++ in particular doesn't
handle them when the struct gets complicated, i.e. has a union.

Reviewed-by: Chad Versace <chad.versace@intel.com>
8 years agoisl: Include c99_compat.h
Jason Ekstrand [Fri, 15 Apr 2016 23:31:21 +0000 (16:31 -0700)]
isl: Include c99_compat.h

We need the restrict keyword in isl.h

Reviewed-by: Chad Versace <chad.versace@intel.com>
8 years agoi965: Add a dependency on libisl
Jason Ekstrand [Fri, 15 Apr 2016 22:32:18 +0000 (15:32 -0700)]
i965: Add a dependency on libisl

To avoid build issues, ensure that you're running `make' at the top level
and/or you've executed `make clean' beforehand.

Reviewed-by: Chad Versace <chad.versace@intel.com>
8 years agoradeon: handle query buffer allocation and mapping failures
Nicolai Hähnle [Wed, 20 Apr 2016 14:11:16 +0000 (09:11 -0500)]
radeon: handle query buffer allocation and mapping failures

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=94984
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
8 years agoradeon: wire end_query return value to sw/hw_end
Nicolai Hähnle [Wed, 20 Apr 2016 14:43:09 +0000 (09:43 -0500)]
radeon: wire end_query return value to sw/hw_end

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
8 years agost/mesa: check return value of begin/end_query
Nicolai Hähnle [Wed, 20 Apr 2016 14:37:06 +0000 (09:37 -0500)]
st/mesa: check return value of begin/end_query

They can only indicate out of memory conditions, since the other error
conditions are caught earlier.

v2: fix error message in EndQuery

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
8 years agogallium: add bool return to pipe_context::end_query
Nicolai Hähnle [Wed, 20 Apr 2016 14:22:48 +0000 (09:22 -0500)]
gallium: add bool return to pipe_context::end_query

Even when begin_query succeeds, there can still be failures in query handling.
For example for radeon, additional buffers may have to be allocated when
queries span multiple command buffers.

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
8 years agoi965: Always use Y-tiled buffers on SKL+
Ben Widawsky [Fri, 22 Apr 2016 03:14:58 +0000 (20:14 -0700)]
i965: Always use Y-tiled buffers on SKL+

Starting with Skylake, the display engine is capable of scanning out from
Y-tiled buffers. As such, we can and should use Y-tiling for better efficiency.
This also has the added benefit of being able to fast clear the winsys buffer.

Note that the buffer allocation done for mipmaps will already never allocate an
X-tiled buffer for GEN9.

This has an almost universal positive impact on benchmarks, some improving by as
much as 20%.

Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
8 years agosoftpipe: fix a warning due to an incorrect enum comparison
Marek Olšák [Sat, 16 Apr 2016 11:47:44 +0000 (13:47 +0200)]
softpipe: fix a warning due to an incorrect enum comparison

no change in behavior, because both are defined the same

Acked-by: Jose Fonseca <jfonseca@vmware.com>
8 years agogallium: remove helpers converting to/from TGSI_PROCESSOR_*
Marek Olšák [Sat, 16 Apr 2016 12:48:34 +0000 (14:48 +0200)]
gallium: remove helpers converting to/from TGSI_PROCESSOR_*

Acked-by: Jose Fonseca <jfonseca@vmware.com>
8 years agogallium: use PIPE_SHADER_* everywhere, remove TGSI_PROCESSOR_*
Marek Olšák [Sat, 16 Apr 2016 12:41:57 +0000 (14:41 +0200)]
gallium: use PIPE_SHADER_* everywhere, remove TGSI_PROCESSOR_*

Acked-by: Jose Fonseca <jfonseca@vmware.com>
8 years agogallium: merge PIPE_SWIZZLE_* and UTIL_FORMAT_SWIZZLE_*
Marek Olšák [Sat, 16 Apr 2016 12:05:47 +0000 (14:05 +0200)]
gallium: merge PIPE_SWIZZLE_* and UTIL_FORMAT_SWIZZLE_*

Use PIPE_SWIZZLE_* everywhere.
Use X/Y/Z/W/0/1 instead of RED, GREEN, BLUE, ALPHA, ZERO, ONE.
The new enum is called pipe_swizzle.

Acked-by: Jose Fonseca <jfonseca@vmware.com>
8 years agogallium: use enums in p_shader_tokens.h (v2)
Marek Olšák [Sat, 16 Apr 2016 11:35:08 +0000 (13:35 +0200)]
gallium: use enums in p_shader_tokens.h (v2)

Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> (v1)
Reviewed-by: Roland Scheidegger <sroland@vmware.com> (v1)
Acked-by: Jose Fonseca <jfonseca@vmware.com> (v1)
v2: name enums

8 years agogallium: use enums in p_defines.h (v2)
Marek Olšák [Sat, 16 Apr 2016 11:35:08 +0000 (13:35 +0200)]
gallium: use enums in p_defines.h (v2)

and remove number assignments which are consecutive

Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> (v1)
Reviewed-by: Roland Scheidegger <sroland@vmware.com> (v1)
Acked-by: Jose Fonseca <jfonseca@vmware.com> (v1)
v2: name enums

8 years agoradeonsi: remove the shader parameter from si_set_ring_buffer
Marek Olšák [Thu, 21 Apr 2016 15:52:29 +0000 (17:52 +0200)]
radeonsi: remove the shader parameter from si_set_ring_buffer

not used anymore

this is a follow-up to the RW buffer cleanup.

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
8 years agoradeonsi: decrease GS copy shader user SGPRs to 2
Marek Olšák [Tue, 19 Apr 2016 13:57:53 +0000 (15:57 +0200)]
radeonsi: decrease GS copy shader user SGPRs to 2

const buffers are no longer used since the clip plane const buffer was
moved to RW buffers

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
8 years agoradeonsi: shorten slot masks to 32 bits
Marek Olšák [Tue, 19 Apr 2016 00:21:25 +0000 (02:21 +0200)]
radeonsi: shorten slot masks to 32 bits

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
8 years agoradeonsi: clean up shader resource limit definitions
Marek Olšák [Tue, 19 Apr 2016 00:14:53 +0000 (02:14 +0200)]
radeonsi: clean up shader resource limit definitions

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
8 years agoradeonsi: move default tess level constant buffer to RW buffers
Marek Olšák [Tue, 19 Apr 2016 00:09:55 +0000 (02:09 +0200)]
radeonsi: move default tess level constant buffer to RW buffers

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
8 years agoradeonsi: move sample positions constant buffer to RW buffers
Marek Olšák [Mon, 18 Apr 2016 23:53:03 +0000 (01:53 +0200)]
radeonsi: move sample positions constant buffer to RW buffers

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
8 years agoradeonsi: move clip plane constant buffer to RW buffers
Marek Olšák [Mon, 18 Apr 2016 23:48:39 +0000 (01:48 +0200)]
radeonsi: move clip plane constant buffer to RW buffers

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
8 years agoradeonsi: rework polygon stippling to use constant buffer instead of texture
Marek Olšák [Mon, 18 Apr 2016 23:19:54 +0000 (01:19 +0200)]
radeonsi: rework polygon stippling to use constant buffer instead of texture

add it to the RW_BUFFERS descriptor array

now the slot masks don't have to have 64 bits

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
8 years agoradeonsi: generalize si_set_constant_buffer
Marek Olšák [Mon, 18 Apr 2016 21:09:55 +0000 (23:09 +0200)]
radeonsi: generalize si_set_constant_buffer

this will be used in the next commit

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
8 years agoradeonsi: make RW buffer descriptor array global, not per shader stage
Marek Olšák [Mon, 18 Apr 2016 20:41:48 +0000 (22:41 +0200)]
radeonsi: make RW buffer descriptor array global, not per shader stage

v2: also simplify invalidation of RW buffer bindings (squashed)

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
8 years agoradeonsi: rename and rearrange RW buffer slots
Marek Olšák [Mon, 18 Apr 2016 20:16:54 +0000 (22:16 +0200)]
radeonsi: rename and rearrange RW buffer slots

- use an enum
- use a unique slot number regardless of the shader stage
  (the per-stage slots will go away for RW buffers)

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
8 years agogallivm: fix bogus argument order to lp_build_sample_mipmap function
Roland Scheidegger [Thu, 21 Apr 2016 00:52:35 +0000 (02:52 +0200)]
gallivm: fix bogus argument order to lp_build_sample_mipmap function

Screwed up since 0753b135f6e83b171d8a1b08aea967374f3542bc.

(Only an issue with different min/mag filters, and then only in some cases,
which is probably why it went unnoticed for quite a while.
The effect should have simply been nearest mip filter instead of linear, iff
min was nearest, mag was linear, and all pixels hit the mignifying path.)

Fixes a bunch of dEQP failures.

Reviewed-by: Jose Fonseca <jfonseca@vmware.com>
Cc: "11.1 11.2" <mesa-stable@lists.freedesktop.org>
8 years agoi965: Fix clear code for ignoring colormask for XRGB formats on Gen9+.
Kenneth Graunke [Wed, 20 Apr 2016 23:55:33 +0000 (16:55 -0700)]
i965: Fix clear code for ignoring colormask for XRGB formats on Gen9+.

In commit cda886a4851ab767fba40e8474d6fa8190347e4f, Neil made us stop
advertising RGBX formats on Gen9+, as the hardware apparently no longer
has working fast clear support for those formats.  Instead, we just
fall back to RGBA formats, and use SCS to override alpha to 1.0.

This is fine, but had one unintended side effect: it made us fall back
to slow clears when the color mask disables alpha.  Normally, we ignore
the color mask for non-existent channels.  This includes alpha for XRGB
formats as writing garbage to the X channel is harmless.  But, now that
we use RGBA, we think there's a real alpha channel, and can't do the
optimization.

To hack around this, check if _BaseFormat is GL_RGB and ignore alpha.

Improves WebGL Aquarium performance on Skylake GT3e by about 50%
by letting it use repclears instead of slow clears.

Cc: mesa-stable@lists.freedesktop.org
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Ben Widawsky <ben@bwidawsk.net>
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
8 years agoi965/blorp: Improve precission of blitting coordinates when clipping
Iago Toral Quiroga [Wed, 29 Jul 2015 14:01:21 +0000 (16:01 +0200)]
i965/blorp: Improve precission of blitting coordinates when clipping

We do this in two steps: first we clip the dst rect and adjust the src
rect accordingly. Then we do it the other way around. In both passes
the adjustment part involves multiplying by a scale factor that can lead
to a small precision loss. This is breaking a few dEQP tests.

Specifically, the problem happens when we need to clip the same coordinate
twice. For example, if srcX0 and dstX0 need both to be clipped we want to
avoid the situation where we clip srcX0 first, then adjust dstX0 accordingly
but then we realize that the resulting dstX0 still needs to be clipped, so
we clip dstX0 and adjust srcX0 again. Each of these two passes can lead
to precission loss. What we want to do here is detect the rect that leads
to the largest clip (accounting for the scale factor involved), clip that
rect and adjust the other one. With this we ensure that the adjusted
coordinate does not need to be clipped again and we can skip a second pass,
improving precision.

Fixes the following 4 dEQP tests:
dEQP-GLES3.functional.fbo.blit.rect.out_of_bounds_reverse_src_x_nearest
dEQP-GLES3.functional.fbo.blit.rect.out_of_bounds_reverse_src_x_linear
dEQP-GLES3.functional.fbo.blit.rect.out_of_bounds_reverse_dst_x_nearest
dEQP-GLES3.functional.fbo.blit.rect.out_of_bounds_reverse_dst_x_linear

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Tested-by: Mark Janes <mark.a.janes@intel.com>
8 years agoradeonsi: Add config parameter to si_shader_apply_scratch_relocs.
Bas Nieuwenhuizen [Thu, 21 Apr 2016 16:12:48 +0000 (18:12 +0200)]
radeonsi: Add config parameter to si_shader_apply_scratch_relocs.

shader->config is not updated for compute kernels.

Signed-off-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
8 years agoglsl: Relax GLSL 1.10 float suffix error to a warning.
Matt Turner [Wed, 20 Apr 2016 19:29:23 +0000 (12:29 -0700)]
glsl: Relax GLSL 1.10 float suffix error to a warning.

Float suffixes are allowed in all subsequent GLSL specifications, and
it's obvious what the user meant if they specify one. Accept it with a
warning to avoid breaking applications, like Planeshift (although it
looks like between 0.6.1 and 0.6.3 they might have removed the suffixes
from their shaders).

Reviewed-by: Lars Hamre <chemecse@gmail.com>
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
8 years agoi965/fs: Readd opt_drop_redundant_mov_to_flags().
Matt Turner [Wed, 20 Apr 2016 21:22:53 +0000 (14:22 -0700)]
i965/fs: Readd opt_drop_redundant_mov_to_flags().

This reverts commit b449366587b5f3f64c6fb45fe22c39e4bc8a4309.

I removed the pass thinking that it was now not useful, but that was not
true. I believe I ran shader-db on HSW and saw no results, but HSW does
not use the unlit centroid workaround code and as a result does not emit
redundant MOV_DISPATCH_TO_FLAGS instructions.

On IVB, the shader-db results are:

total instructions in shared programs: 6650806 -> 6646303 (-0.07%)
instructions in affected programs: 106893 -> 102390 (-4.21%)
helped: 793

total cycles in shared programs: 56195538 -> 56103720 (-0.16%)
cycles in affected programs: 873048 -> 781230 (-10.52%)
helped: 553
HURT: 209

On SNB, the shader-db results are:

total instructions in shared programs: 7173074 -> 7168541 (-0.06%)
instructions in affected programs: 119757 -> 115224 (-3.79%)
helped: 799

total cycles in shared programs: 98128032 -> 98072938 (-0.06%)
cycles in affected programs: 1437104 -> 1382010 (-3.83%)
helped: 454
HURT: 237

Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
8 years agoi965/blorp: Do not emit pma stall on gen9+
Topi Pohjolainen [Thu, 21 Apr 2016 09:31:37 +0000 (12:31 +0300)]
i965/blorp: Do not emit pma stall on gen9+

This was left out from the original gen8 upload introduction.

Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
8 years agoswr: add PIPE_CAP_FRAMEBUFFER_NO_ATTACHMENT to get_param
Tim Rowley [Thu, 21 Apr 2016 16:10:29 +0000 (11:10 -0500)]
swr: add PIPE_CAP_FRAMEBUFFER_NO_ATTACHMENT to get_param

Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
8 years agoi965: automake: remove gratuitous "+" during variable assignment
Emil Velikov [Thu, 21 Apr 2016 15:48:34 +0000 (16:48 +0100)]
i965: automake: remove gratuitous "+" during variable assignment

There is not initial assignment, thus appending to it does not work.

Fixes: b27c85c4c08 "i965: add build rule for brw_nir_trig_workarounds.c"
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
8 years agogbm: add GBM_FORMAT_XBGR8888 format support
Rob Herring [Tue, 19 Apr 2016 19:38:41 +0000 (14:38 -0500)]
gbm: add GBM_FORMAT_XBGR8888 format support

Add GBM_FORMAT_XBGR8888/__DRI_IMAGE_FORMAT_XBGR8888 format support which
is needed for Android.

Signed-off-by: Rob Herring <robh@kernel.org>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
8 years agost/dri: add 32-bit RGBX/RGBA formats
Rob Herring [Wed, 20 Apr 2016 22:39:54 +0000 (17:39 -0500)]
st/dri: add 32-bit RGBX/RGBA formats

Add support for 32-bit RGBX/RGBA formats which are preferred for Android.

Signed-off-by: Rob Herring <robh@kernel.org>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
8 years agodri/common: add MESA_FORMAT_R8G8B8{A8, X8}_UNORM formats as supported configs
Rob Herring [Tue, 19 Apr 2016 19:38:39 +0000 (14:38 -0500)]
dri/common: add MESA_FORMAT_R8G8B8{A8, X8}_UNORM formats as supported configs

Add MESA_FORMAT_R8G8B8A8_UNORM and MESA_FORMAT_R8G8B8X8_UNORM formats as
these are the preferred formats for Android.

Signed-off-by: Rob Herring <robh@kernel.org>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
8 years agoi965: add build rule for brw_nir_trig_workarounds.c on Android
Rob Herring [Tue, 19 Apr 2016 19:51:02 +0000 (14:51 -0500)]
i965: add build rule for brw_nir_trig_workarounds.c on Android

Commit bfd17c76c126 ("i965: Port INTEL_PRECISE_TRIG=1 to NIR.") added a
generated file brw_nir_trig_workarounds.c which broke the Android build.
Add the necessary makefiles to the Android build.

Cc: Kenneth Graunke <kenneth@whitecape.org>
Signed-off-by: Rob Herring <robh@kernel.org>
Tested-by: Chih-Wei Huang <cwhuang@linux.org.tw>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
8 years agoglsl: android: add back missing generated glcpp include path
Rob Herring [Thu, 14 Apr 2016 19:40:56 +0000 (14:40 -0500)]
glsl: android: add back missing generated glcpp include path

Commit 4db8f15a2576 ("glsl: move the android build scripts a level up")
dropped a generated include path for glcpp. Add it back adjusting for the
new location.

Signed-off-by: Rob Herring <robh@kernel.org>
Tested-by: Chih-Wei Huang <cwhuang@linux.org.tw>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
8 years agoloader: add a libdrm case for loader_get_device_name_for_fd
Jonathan Gray [Mon, 21 Dec 2015 05:39:55 +0000 (16:39 +1100)]
loader: add a libdrm case for loader_get_device_name_for_fd

Use dev_node_from_fd() with HAVE_LIBDRM to provide an implmentation
of loader_get_device_name_for_fd() for non-linux systems that
use libdrm but don't have udev or sysfs.

Signed-off-by: Jonathan Gray <jsg@jsg.id.au>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
8 years agoi965/tiled_memcpy: don't unconditionally use __builtin_bswap32
Jonathan Gray [Tue, 19 Apr 2016 02:31:20 +0000 (12:31 +1000)]
i965/tiled_memcpy: don't unconditionally use __builtin_bswap32

Use the defines Mesa configure sets to indicate presence of the bswap32
builtins.  This lets i965 work on OpenBSD again after the changes that
were made in 0a5d8d9af42fd77fce1492d55f958da97816961a.

Signed-off-by: Jonathan Gray <jsg@jsg.id.au>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
8 years agoegl/x11: authenticate before doing chipset id ioctls
Jonathan Gray [Tue, 19 Apr 2016 02:29:36 +0000 (12:29 +1000)]
egl/x11: authenticate before doing chipset id ioctls

For systems without udev or sysfs that use drm ioctls in the loader
drm authentication must take place earlier or the loader will fail
"MESA-LOADER: failed to get param for i915".

Patch from Mark Kettenis.

Cc: "11.2 11.1" <mesa-stable@lists.freedesktop.org>
Signed-off-by: Mark Kettenis <kettenis@openbsd.org>
Signed-off-by: Jonathan Gray <jsg@jsg.id.au>
[Emil Velikov: remove gratuitous white-space]
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
8 years agogallium/radeon: Silence possibly uninitialized variable warning.
Bas Nieuwenhuizen [Thu, 21 Apr 2016 11:23:36 +0000 (13:23 +0200)]
gallium/radeon: Silence possibly uninitialized variable warning.

Signed-off-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
8 years agowinsys/amdgpu: Silence possibly uninitialized variable warning.
Bas Nieuwenhuizen [Thu, 21 Apr 2016 11:22:08 +0000 (13:22 +0200)]
winsys/amdgpu: Silence possibly uninitialized variable warning.

Signed-off-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
8 years agoradeonsi: Enable loading into CE RAM.
Bas Nieuwenhuizen [Wed, 20 Apr 2016 23:22:02 +0000 (01:22 +0200)]
radeonsi: Enable loading into CE RAM.

We need to enable a bit in the CONTEXT_CONTROL packet for the
loads to work.

v2: Style issues.

Signed-off-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
8 years agoradeonsi: Use defines for CONTEXT_CONTROL instead of magic values.
Bas Nieuwenhuizen [Wed, 20 Apr 2016 23:19:28 +0000 (01:19 +0200)]
radeonsi: Use defines for CONTEXT_CONTROL instead of magic values.

v2: Use field names provided by Nicolai.
v3: Updated to use CONTEXT_CONTROL prefix.

Signed-off-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
8 years agowinsys/amdgpu: fix preamble IB size
Thomas Hindoe Paaboel Andersen [Wed, 20 Apr 2016 20:34:02 +0000 (22:34 +0200)]
winsys/amdgpu: fix preamble IB size

The missing break caused the IB size to be overwritten with
the size of IB_CONST.

This was introduced in: 7201230582e060aa2eb79c825d3188b437ef7bb8

Signed-off-by: Marek Olšák <marek.olsak@amd.com>
8 years agoi965/blorp: Reduce the urb size requirement for vertex buffer
Topi Pohjolainen [Tue, 19 Apr 2016 17:08:55 +0000 (20:08 +0300)]
i965/blorp: Reduce the urb size requirement for vertex buffer

Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
8 years agoi965/blorp: Reduce the size of vertex buffer
Topi Pohjolainen [Tue, 19 Apr 2016 16:57:43 +0000 (19:57 +0300)]
i965/blorp: Reduce the size of vertex buffer

Previously the vertex buffer consisted of eight floats per vertex
of which six where constants. These can be as easily provided by
vertex fetcher as it is capable of filling vertex elements with
constant one and zero. This reduces the size of the vertex buffer
from 3 * 8 * 4 = 96 to 3 * 2 * 4 = 24 bytes.

Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
8 years agoi965/blorp: Do not tricker urb re-configuration unnecessarily
Topi Pohjolainen [Fri, 15 Apr 2016 11:03:18 +0000 (14:03 +0300)]
i965/blorp: Do not tricker urb re-configuration unnecessarily

Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
8 years agoi965/blorp: Skip re-emitting urb config whenever possible
Topi Pohjolainen [Fri, 15 Apr 2016 10:39:48 +0000 (13:39 +0300)]
i965/blorp: Skip re-emitting urb config whenever possible

Otherwise clearing with blorp will regress performance in some
synthetic test cases.

v2: Used vsize >= 2 instead of vsize > 0, and updated the comment.
    Review by Ken in one of the earlier patches revealed this.

Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
8 years agoi965/blorp: Prepare to switch from compute pipeline
Topi Pohjolainen [Fri, 15 Apr 2016 07:43:05 +0000 (10:43 +0300)]
i965/blorp: Prepare to switch from compute pipeline

Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
8 years agoi965/blorp: Skip uploading state/options not needed for clears
Topi Pohjolainen [Mon, 11 Apr 2016 21:18:45 +0000 (00:18 +0300)]
i965/blorp: Skip uploading state/options not needed for clears

In case there is no source it means the program does a simple
clear or a resolve. In such case there is no need to program
sampling state or enable pixel kill in fragment shader.

Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
8 years agoi965/blorp: Re-introduce clear programs
Topi Pohjolainen [Fri, 1 Apr 2016 12:57:54 +0000 (15:57 +0300)]
i965/blorp: Re-introduce clear programs

This partially reverts 2f28a0dc23165123cf1e8b5942acad37878edd8a

Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
8 years agoi965/meta: Move check for srgb into is_color_fast_clear_compatible()
Topi Pohjolainen [Wed, 6 Apr 2016 08:38:59 +0000 (11:38 +0300)]
i965/meta: Move check for srgb into is_color_fast_clear_compatible()

Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>