Eddie Hung [Thu, 12 Dec 2019 00:26:26 +0000 (16:26 -0800)]
Preserve size of $genval$-s in for loops
Eddie Hung [Thu, 12 Dec 2019 00:26:19 +0000 (16:26 -0800)]
Add testcase
Eddie Hung [Wed, 11 Dec 2019 21:02:07 +0000 (13:02 -0800)]
Fix bitwidth mismatch; suppresses iverilog warning
David Shah [Wed, 11 Dec 2019 08:46:10 +0000 (08:46 +0000)]
Merge pull request #1564 from ZirconiumX/intel_housekeeping
Intel housekeeping
Dan Ravensloft [Tue, 10 Dec 2019 13:40:32 +0000 (13:40 +0000)]
synth_intel: a10gx -> arria10gx
Dan Ravensloft [Tue, 10 Dec 2019 13:31:45 +0000 (13:31 +0000)]
synth_intel: cyclone10 -> cyclone10lp
Eddie Hung [Tue, 10 Dec 2019 01:38:48 +0000 (17:38 -0800)]
Merge pull request #1545 from YosysHQ/eddie/ice40_wrapcarry_attr
Preserve SB_CARRY name and attributes when using $__ICE40_CARRY_WRAPPER
Eddie Hung [Mon, 9 Dec 2019 22:29:29 +0000 (14:29 -0800)]
ice40_opt to restore attributes/name when unwrapping
Eddie Hung [Mon, 9 Dec 2019 22:28:54 +0000 (14:28 -0800)]
ice40_wrapcarry -unwrap to preserve 'src' attribute
Eddie Hung [Mon, 9 Dec 2019 22:20:35 +0000 (14:20 -0800)]
unmap $__ICE40_CARRY_WRAPPER in test
Eddie Hung [Mon, 9 Dec 2019 21:27:09 +0000 (13:27 -0800)]
-unwrap to create $lut not SB_LUT4 for opt_lut
Eddie Hung [Mon, 9 Dec 2019 20:45:22 +0000 (12:45 -0800)]
Sensitive to direct inst of $__ICE40_CARRY_WRAPPER; recreate SB_LUT4
Eddie Hung [Mon, 9 Dec 2019 19:48:28 +0000 (11:48 -0800)]
ice40_wrapcarry to really preserve attributes via -unwrap option
Eddie Hung [Sat, 7 Dec 2019 07:04:04 +0000 (23:04 -0800)]
Merge pull request #1555 from antmicro/fix-macc-xilinx-test
tests: arch: xilinx: Change order of arguments in macc.sh
Eddie Hung [Sat, 7 Dec 2019 01:27:47 +0000 (17:27 -0800)]
Drop keep=0 attributes on SB_CARRY
Jan Kowalewski [Fri, 6 Dec 2019 08:01:16 +0000 (09:01 +0100)]
tests: arch: xilinx: Change order of arguments in macc.sh
Clifford Wolf [Thu, 5 Dec 2019 16:24:24 +0000 (08:24 -0800)]
Merge pull request #1551 from whitequark/manual-cell-operands
Clarify semantics of comb cells, in particular shifts
Eddie Hung [Thu, 5 Dec 2019 15:01:18 +0000 (07:01 -0800)]
Merge SB_CARRY+SB_LUT4's attributes when creating $__ICE40_CARRY_WRAPPER
Eddie Hung [Thu, 5 Dec 2019 15:01:02 +0000 (07:01 -0800)]
Add WIP test for unwrapping $__ICE40_CARRY_WRAPPER
whitequark [Wed, 4 Dec 2019 11:59:36 +0000 (11:59 +0000)]
kernel: require \B_SIGNED=0 on $shl, $sshl, $shr, $sshr.
Before this commit, these cells would accept any \B_SIGNED and in
case of \B_SIGNED=1, would still treat the \B input as unsigned.
Also fix the Verilog frontend to never emit such constructs.
whitequark [Wed, 4 Dec 2019 11:06:05 +0000 (11:06 +0000)]
manual: document behavior of many comb cells more precisely.
Marcin Kościelnicki [Wed, 4 Dec 2019 08:44:00 +0000 (09:44 +0100)]
xilinx: Add tristate buffer mapping. (#1528)
Fixes #1225.
Marcin Kościelnicki [Wed, 4 Dec 2019 07:44:08 +0000 (08:44 +0100)]
iopadmap: Refactor and fix tristate buffer mapping. (#1527)
The previous code for rerouting wires when inserting tristate buffers
was overcomplicated and didn't handle all cases correctly (in
particular, only cell connections were rewired — internal connections
were not).
Marcin Kościelnicki [Wed, 4 Dec 2019 05:31:09 +0000 (06:31 +0100)]
xilinx: Add models for LUTRAM cells. (#1537)
Eddie Hung [Tue, 3 Dec 2019 22:51:39 +0000 (14:51 -0800)]
Check SB_CARRY name also preserved
Eddie Hung [Tue, 3 Dec 2019 22:49:10 +0000 (14:49 -0800)]
$__ICE40_CARRY_WRAPPER to use _TECHMAP_REPLACE_ for SB_CARRY to preserve
name and attr
Eddie Hung [Tue, 3 Dec 2019 22:48:39 +0000 (14:48 -0800)]
ice40_opt to ignore (* keep *) -ed cells
Eddie Hung [Tue, 3 Dec 2019 22:48:11 +0000 (14:48 -0800)]
ice40_wrapcarry to preserve SB_CARRY's attributes
Eddie Hung [Tue, 3 Dec 2019 22:48:00 +0000 (14:48 -0800)]
Add testcase
Clifford Wolf [Tue, 3 Dec 2019 16:43:18 +0000 (08:43 -0800)]
Merge pull request #1524 from pepijndevos/gowindffinit
Gowin: add and test DFF init values
Pepijn de Vos [Tue, 3 Dec 2019 15:56:15 +0000 (16:56 +0100)]
update test
Pepijn de Vos [Tue, 3 Dec 2019 14:12:25 +0000 (15:12 +0100)]
Use -match-init to not synth contradicting init values
David Shah [Mon, 2 Dec 2019 10:20:21 +0000 (10:20 +0000)]
Merge pull request #1542 from YosysHQ/dave/abc9-loop-fix
abc9: Fix breaking of SCCs
Clifford Wolf [Mon, 2 Dec 2019 00:30:48 +0000 (16:30 -0800)]
Merge pull request #1539 from YosysHQ/mwk/ilang-bounds-check
read_ilang: do bounds checking on bit indices
David Shah [Sun, 1 Dec 2019 20:44:56 +0000 (20:44 +0000)]
abc9: Fix breaking of SCCs
Signed-off-by: David Shah <dave@ds0.me>
Miodrag Milanović [Fri, 29 Nov 2019 16:33:41 +0000 (17:33 +0100)]
Merge pull request #1540 from YosysHQ/mwk/xilinx-bufpll
xilinx: Add missing blackbox cell for BUFPLL.
Marcin Kościelnicki [Fri, 29 Nov 2019 15:55:29 +0000 (15:55 +0000)]
xilinx: Add missing blackbox cell for BUFPLL.
Eddie Hung [Thu, 28 Nov 2019 05:55:56 +0000 (21:55 -0800)]
Revert "Fold loop"
This reverts commit
a30d5e1cc35791a98b2269c5e587c566fe8b0a35.
Marcin Kościelnicki [Wed, 27 Nov 2019 21:24:39 +0000 (22:24 +0100)]
read_ilang: do bounds checking on bit indices
Eddie Hung [Wed, 27 Nov 2019 16:00:22 +0000 (08:00 -0800)]
Merge pull request #1536 from YosysHQ/eddie/xilinx_dsp_muladd
xilinx_dsp: consider sign and zero-extension when packing post-multiplier adder
Clifford Wolf [Wed, 27 Nov 2019 10:25:23 +0000 (11:25 +0100)]
Merge pull request #1501 from YosysHQ/dave/mem_copy_attr
memory_collect: Copy attr from RTLIL::Memory to cell
Clifford Wolf [Wed, 27 Nov 2019 10:23:16 +0000 (11:23 +0100)]
Merge pull request #1534 from YosysHQ/mwk/opt_share-fix
opt_share: Fix handling of fine cells.
Eddie Hung [Wed, 27 Nov 2019 09:04:29 +0000 (01:04 -0800)]
Merge pull request #1535 from YosysHQ/eddie/write_xaiger_improve
write_xaiger improvements
Eddie Hung [Wed, 27 Nov 2019 07:08:14 +0000 (23:08 -0800)]
No need for -abc9
Marcin Kościelnicki [Tue, 26 Nov 2019 23:46:21 +0000 (00:46 +0100)]
opt_share: Fix handling of fine cells.
Fixes #1525.
Eddie Hung [Wed, 27 Nov 2019 06:59:05 +0000 (22:59 -0800)]
latch -> box
Eddie Hung [Wed, 27 Nov 2019 06:51:16 +0000 (22:51 -0800)]
Add citation
Eddie Hung [Wed, 27 Nov 2019 05:26:53 +0000 (21:26 -0800)]
Check for either sign or zero extension for postAdd packing
Eddie Hung [Wed, 27 Nov 2019 06:41:35 +0000 (22:41 -0800)]
Remove notes
Eddie Hung [Mon, 25 Nov 2019 23:43:37 +0000 (15:43 -0800)]
Fold loop
Eddie Hung [Mon, 25 Nov 2019 23:42:07 +0000 (15:42 -0800)]
Do not sigmap keep bits inside write_xaiger
Eddie Hung [Wed, 27 Nov 2019 03:03:02 +0000 (19:03 -0800)]
xaiger: do not promote output wires
Eddie Hung [Wed, 27 Nov 2019 05:26:30 +0000 (21:26 -0800)]
Add testcase derived from fastfir_dynamictaps benchmark
Marcin Kościelnicki [Tue, 26 Nov 2019 04:04:28 +0000 (05:04 +0100)]
xilinx: Add simulation models for IOBUF and OBUFT.
Marcin Kościelnicki [Sun, 24 Nov 2019 15:05:45 +0000 (16:05 +0100)]
clkbufmap: Add support for inverters in clock path.
Marcin Kościelnicki [Sun, 24 Nov 2019 13:17:46 +0000 (14:17 +0100)]
xilinx: Use INV instead of LUT1 when applicable
Pepijn de Vos [Mon, 25 Nov 2019 13:50:34 +0000 (14:50 +0100)]
attempt to fix formatting
Pepijn de Vos [Mon, 25 Nov 2019 13:33:21 +0000 (14:33 +0100)]
gowin: add and test dff init values
Eddie Hung [Sat, 23 Nov 2019 06:45:40 +0000 (22:45 -0800)]
Merge pull request #1520 from pietrmar/fix-1463
coolrunner2: remove spurious log_pop() call, fixes #1463
Martin Pietryka [Sat, 23 Nov 2019 05:18:23 +0000 (06:18 +0100)]
coolrunner2: remove spurious log_pop() call, fixes #1463
This was causing a segmentation fault because there is no accompanying
log_push() call so header_count.size() became -1.
Signed-off-by: Martin Pietryka <martin@pietryka.at>
Clifford Wolf [Fri, 22 Nov 2019 17:11:58 +0000 (18:11 +0100)]
Merge pull request #1517 from YosysHQ/clifford/optmem
Add "opt_mem" pass
Clifford Wolf [Fri, 22 Nov 2019 17:10:34 +0000 (18:10 +0100)]
Merge pull request #1515 from YosysHQ/clifford/svastuff
Add Verific/SVA support for "always" and "nexttime" properties
Clifford Wolf [Fri, 22 Nov 2019 15:58:49 +0000 (16:58 +0100)]
Add "opt_mem" pass
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Clifford Wolf [Fri, 22 Nov 2019 15:11:56 +0000 (16:11 +0100)]
Add Verific support for SVA nexttime properties
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Clifford Wolf [Fri, 22 Nov 2019 15:00:07 +0000 (16:00 +0100)]
Improve handling of verific primitives in "verific -import -V" mode
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Clifford Wolf [Fri, 22 Nov 2019 14:52:21 +0000 (15:52 +0100)]
Add Verific SVA support for "always" properties
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Clifford Wolf [Fri, 22 Nov 2019 14:32:29 +0000 (15:32 +0100)]
Merge pull request #1511 from YosysHQ/dave/always
sv: Error checking for always_comb, always_latch and always_ff
Marcin Kościelnicki [Fri, 22 Nov 2019 11:15:33 +0000 (12:15 +0100)]
gowin: Remove show command from tests.
Marcin Kościelnicki [Fri, 22 Nov 2019 11:10:57 +0000 (12:10 +0100)]
gowin: Add missing .gitignore entries
David Shah [Fri, 22 Nov 2019 12:46:19 +0000 (12:46 +0000)]
Update CHANGELOG and README
Signed-off-by: David Shah <dave@ds0.me>
David Shah [Thu, 21 Nov 2019 21:06:28 +0000 (21:06 +0000)]
sv: Add tests for SV always types
Signed-off-by: David Shah <dave@ds0.me>
David Shah [Thu, 21 Nov 2019 20:46:41 +0000 (20:46 +0000)]
proc_dlatch: Add error handling for incorrect always_(ff|latch|comb) usage
Signed-off-by: David Shah <dave@ds0.me>
David Shah [Thu, 21 Nov 2019 20:27:19 +0000 (20:27 +0000)]
sv: Correct parsing of always_comb, always_ff and always_latch
Signed-off-by: David Shah <dave@ds0.me>
Clifford Wolf [Wed, 20 Nov 2019 12:49:27 +0000 (13:49 +0100)]
Merge pull request #1507 from YosysHQ/clifford/verificfixes
Some fixes in our Verific integration
Clifford Wolf [Wed, 20 Nov 2019 11:56:31 +0000 (12:56 +0100)]
Correctly treat empty modules as blackboxes in Verific
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Clifford Wolf [Wed, 20 Nov 2019 11:54:10 +0000 (12:54 +0100)]
Do not rename VHDL entities to "entity(impl)" when they are top modules
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Clifford Wolf [Tue, 19 Nov 2019 16:29:27 +0000 (17:29 +0100)]
Merge pull request #1449 from pepijndevos/gowin
Improvements for gowin support
Pepijn de Vos [Tue, 19 Nov 2019 14:53:44 +0000 (15:53 +0100)]
Remove dff init altogether
The hardware does not actually support it.
In reality it is always initialised to its reset value.
Marcin Kościelnicki [Mon, 18 Nov 2019 07:19:53 +0000 (08:19 +0100)]
Fix #1462, #1480.
Marcin Kościelnicki [Mon, 18 Nov 2019 02:47:56 +0000 (03:47 +0100)]
xilinx: Add simulation models for MULT18X18* and DSP48A*.
This adds simulation models for the following primitives:
- MULT18X18 and MULT18X18S (Virtex 2*, Spartan 3)
- MULT18X18SIO (Spartan 3E, Spartan 3A)
- DSP48A (Spartan 3A DSP) — implemented in terms of DSP48A1
- DSP48A1 (Spartan 6)
David Shah [Mon, 18 Nov 2019 13:58:03 +0000 (13:58 +0000)]
memory_collect: Copy attr from RTLIL::Memory to cell
Signed-off-by: David Shah <dave@ds0.me>
Pepijn de Vos [Mon, 18 Nov 2019 13:25:46 +0000 (14:25 +0100)]
add help for nowidelut and abc9 options
Clifford Wolf [Mon, 18 Nov 2019 09:53:14 +0000 (10:53 +0100)]
Merge pull request #1497 from YosysHQ/mwk/extract-fa-fix
Fix #1496.
whitequark [Mon, 18 Nov 2019 09:37:14 +0000 (09:37 +0000)]
Merge pull request #1494 from whitequark/write_verilog-extmem
write_verilog: add -extmem option, to write split memory init files
Marcin Kościelnicki [Mon, 18 Nov 2019 03:16:48 +0000 (04:16 +0100)]
Fix #1496.
whitequark [Fri, 15 Nov 2019 03:11:46 +0000 (03:11 +0000)]
write_verilog: add -extmem option, to write split memory init files.
Some toolchains (in particular Quartus) are pathologically slow if
a large amount of assignments in `initial` blocks are used.
Clifford Wolf [Sun, 17 Nov 2019 09:42:30 +0000 (10:42 +0100)]
Merge pull request #1492 from YosysHQ/dave/wreduce-fix-arst
wreduce: Don't trim zeros or sext when not matching ARST_VALUE
Pepijn de Vos [Sat, 16 Nov 2019 11:43:17 +0000 (12:43 +0100)]
Merge branch 'master' of https://github.com/YosysHQ/yosys into gowin
David Shah [Fri, 15 Nov 2019 21:03:11 +0000 (21:03 +0000)]
ecp5: Use new autoname pass for better cell/net names
Signed-off-by: David Shah <dave@ds0.me>
David Shah [Thu, 14 Nov 2019 18:43:15 +0000 (18:43 +0000)]
wreduce: Don't trim zeros or sext when not matching ARST_VALUE
Signed-off-by: David Shah <dave@ds0.me>
Clifford Wolf [Thu, 14 Nov 2019 17:03:44 +0000 (18:03 +0100)]
Merge pull request #1490 from YosysHQ/clifford/autoname
Add "autoname" pass and use it in "synth_ice40"
Clifford Wolf [Thu, 14 Nov 2019 11:10:12 +0000 (12:10 +0100)]
Merge pull request #1444 from btut/feature/python_wrappers/globals_and_streams
Python Wrappers: Expose global variables and allow logging to python streams
Clifford Wolf [Thu, 14 Nov 2019 11:07:25 +0000 (12:07 +0100)]
Merge pull request #1465 from YosysHQ/dave/ice40_timing_sim
ice40: Support for post-place-and-route timing simulations
Clifford Wolf [Thu, 14 Nov 2019 10:57:53 +0000 (11:57 +0100)]
Merge branch 'makaimann-label-bads-btor'
Clifford Wolf [Thu, 14 Nov 2019 10:57:38 +0000 (11:57 +0100)]
Use cell name for btor bad state props when it is a public name
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Clifford Wolf [Thu, 14 Nov 2019 10:52:41 +0000 (11:52 +0100)]
Merge branch 'label-bads-btor' of https://github.com/makaimann/yosys into makaimann-label-bads-btor
Clifford Wolf [Wed, 13 Nov 2019 12:41:16 +0000 (13:41 +0100)]
Add "autoname" pass and use it in "synth_ice40"
Signed-off-by: Clifford Wolf <clifford@clifford.at>
whitequark [Wed, 13 Nov 2019 11:57:17 +0000 (11:57 +0000)]
Merge pull request #1488 from whitequark/flowmap-fixes
flowmap: fix a few crashes
Clifford Wolf [Wed, 13 Nov 2019 11:34:27 +0000 (12:34 +0100)]
Merge pull request #1486 from YosysHQ/clifford/fsmdetectfix
Bugfix in fsm_detect
Clifford Wolf [Tue, 12 Nov 2019 16:31:30 +0000 (17:31 +0100)]
Update fsm_detect bugfix
Signed-off-by: Clifford Wolf <clifford@clifford.at>