bugzilla-daemon [Thu, 14 May 2020 18:42:58 +0000 (18:42 +0000)]
[libre-riscv-dev] [Bug 305] Create Pipelined ALU similar to alu_hier.py
Jacob Lifshay [Thu, 14 May 2020 18:28:24 +0000 (11:28 -0700)]
Re: [libre-riscv-dev] daily kan-ban update 14may2020
bugzilla-daemon [Thu, 14 May 2020 17:29:15 +0000 (17:29 +0000)]
[libre-riscv-dev] [Bug 305] Create Pipelined ALU similar to alu_hier.py
bugzilla-daemon [Thu, 14 May 2020 17:14:34 +0000 (17:14 +0000)]
[libre-riscv-dev] [Bug 305] Create Pipelined ALU similar to alu_hier.py
bugzilla-daemon [Thu, 14 May 2020 16:54:25 +0000 (16:54 +0000)]
[libre-riscv-dev] [Bug 305] Create Pipelined ALU similar to alu_hier.py
Luke Kenneth Casson Leighton [Thu, 14 May 2020 16:44:16 +0000 (17:44 +0100)]
Re: [libre-riscv-dev] daily kan-ban update 14may2020
bugzilla-daemon [Thu, 14 May 2020 16:35:21 +0000 (16:35 +0000)]
[libre-riscv-dev] [Bug 305] Create Pipelined ALU similar to alu_hier.py
bugzilla-daemon [Thu, 14 May 2020 16:21:38 +0000 (16:21 +0000)]
[libre-riscv-dev] [Bug 305] Create Pipelined ALU similar to alu_hier.py
bugzilla-daemon [Thu, 14 May 2020 16:17:37 +0000 (16:17 +0000)]
[libre-riscv-dev] [Bug 305] Create Pipelined ALU similar to alu_hier.py
Tobias Platen [Thu, 14 May 2020 15:49:35 +0000 (17:49 +0200)]
Re: [libre-riscv-dev] daily kan-ban update 14may2020
bugzilla-daemon [Thu, 14 May 2020 15:34:27 +0000 (15:34 +0000)]
[libre-riscv-dev] [Bug 305] Create Pipelined ALU similar to alu_hier.py
bugzilla-daemon [Thu, 14 May 2020 14:59:21 +0000 (14:59 +0000)]
[libre-riscv-dev] [Bug 310] Function Units to cover multiple tasks
bugzilla-daemon [Thu, 14 May 2020 14:48:35 +0000 (14:48 +0000)]
[libre-riscv-dev] [Bug 305] Create Pipelined ALU similar to alu_hier.py
bugzilla-daemon [Thu, 14 May 2020 14:47:48 +0000 (14:47 +0000)]
[libre-riscv-dev] [Bug 310] Function Units to cover multiple tasks
Luke Kenneth Casson Leighton [Thu, 14 May 2020 14:43:33 +0000 (15:43 +0100)]
Re: [libre-riscv-dev] daily kan-ban update 14may2020
bugzilla-daemon [Thu, 14 May 2020 14:37:25 +0000 (14:37 +0000)]
[libre-riscv-dev] [Bug 305] Create Pipelined ALU similar to alu_hier.py
bugzilla-daemon [Thu, 14 May 2020 14:37:25 +0000 (14:37 +0000)]
[libre-riscv-dev] [Bug 310] Function Units to cover multiple tasks
bugzilla-daemon [Thu, 14 May 2020 14:37:09 +0000 (14:37 +0000)]
[libre-riscv-dev] [Bug 310] New: Function Units to cover multiple tasks
Michael Nolan [Thu, 14 May 2020 14:23:37 +0000 (10:23 -0400)]
Re: [libre-riscv-dev] daily kan-ban update 14may2020
Luke Kenneth Casson Leighton [Thu, 14 May 2020 10:54:07 +0000 (11:54 +0100)]
[libre-riscv-dev] daily kan-ban update 14may2020
bugzilla-daemon [Thu, 14 May 2020 00:20:45 +0000 (00:20 +0000)]
[libre-riscv-dev] [Bug 305] Create Pipelined ALU similar to alu_hier.py
Luke Kenneth Casson Leighton [Wed, 13 May 2020 22:20:16 +0000 (23:20 +0100)]
[libre-riscv-dev] popcount and parity
Luke Kenneth Casson Leighton [Wed, 13 May 2020 22:02:47 +0000 (23:02 +0100)]
Re: [libre-riscv-dev] daily kan-ban update 13may2020
bugzilla-daemon [Wed, 13 May 2020 21:54:27 +0000 (21:54 +0000)]
[libre-riscv-dev] [Bug 305] Create Pipelined ALU similar to alu_hier.py
Luke Kenneth Casson Leighton [Wed, 13 May 2020 19:54:06 +0000 (20:54 +0100)]
Re: [libre-riscv-dev] teaching the benefits of using nmigen over VHDL/Verilog
Jacob Lifshay [Wed, 13 May 2020 19:02:41 +0000 (12:02 -0700)]
Re: [libre-riscv-dev] teaching the benefits of using nmigen over VHDL/Verilog
bugzilla-daemon [Wed, 13 May 2020 18:57:54 +0000 (18:57 +0000)]
[libre-riscv-dev] [Bug 305] Create Pipelined ALU similar to alu_hier.py
Michael Nolan [Wed, 13 May 2020 18:51:48 +0000 (14:51 -0400)]
Re: [libre-riscv-dev] teaching the benefits of using nmigen over VHDL/Verilog
bugzilla-daemon [Wed, 13 May 2020 18:48:32 +0000 (18:48 +0000)]
[libre-riscv-dev] [Bug 305] Create Pipelined ALU similar to alu_hier.py
bugzilla-daemon [Wed, 13 May 2020 18:46:13 +0000 (18:46 +0000)]
[libre-riscv-dev] [Bug 305] Create Pipelined ALU similar to alu_hier.py
Luke Kenneth Casson Leighton [Wed, 13 May 2020 18:41:14 +0000 (19:41 +0100)]
Re: [libre-riscv-dev] note on memory operation requirements for linux
Luke Kenneth Casson Leighton [Wed, 13 May 2020 18:18:06 +0000 (19:18 +0100)]
Re: [libre-riscv-dev] teaching the benefits of using nmigen over VHDL/Verilog
Cole Poirier [Wed, 13 May 2020 18:07:07 +0000 (11:07 -0700)]
Re: [libre-riscv-dev] daily kan-ban update 13may2020
bugzilla-daemon [Wed, 13 May 2020 17:58:39 +0000 (17:58 +0000)]
[libre-riscv-dev] [Bug 291] HDL Workflow and Coriolis2 chroot automated setup scripts
Jacob Lifshay [Wed, 13 May 2020 17:49:55 +0000 (10:49 -0700)]
[libre-riscv-dev] teaching the benefits of using nmigen over VHDL/Verilog
bugzilla-daemon [Wed, 13 May 2020 17:29:36 +0000 (17:29 +0000)]
[libre-riscv-dev] [Bug 305] Create Pipelined ALU similar to alu_hier.py
bugzilla-daemon [Wed, 13 May 2020 17:27:26 +0000 (17:27 +0000)]
[libre-riscv-dev] [Bug 309] investigate OpenTITAN
bugzilla-daemon [Wed, 13 May 2020 17:22:53 +0000 (17:22 +0000)]
[libre-riscv-dev] [Bug 305] Create Pipelined ALU similar to alu_hier.py
bugzilla-daemon [Wed, 13 May 2020 16:46:39 +0000 (16:46 +0000)]
[libre-riscv-dev] [Bug 305] Create Pipelined ALU similar to alu_hier.py
bugzilla-daemon [Wed, 13 May 2020 16:44:23 +0000 (16:44 +0000)]
[libre-riscv-dev] [Bug 309] investigate OpenTITAN
bugzilla-daemon [Wed, 13 May 2020 16:21:23 +0000 (16:21 +0000)]
[libre-riscv-dev] [Bug 309] investigate OpenTITAN
Luke Kenneth Casson Leighton [Wed, 13 May 2020 15:03:21 +0000 (16:03 +0100)]
Re: [libre-riscv-dev] daily kan-ban update 13may2020
Tobias Platen [Wed, 13 May 2020 14:43:41 +0000 (16:43 +0200)]
Re: [libre-riscv-dev] daily kan-ban update 13may2020
Luke Kenneth Casson Leighton [Wed, 13 May 2020 14:33:53 +0000 (15:33 +0100)]
Re: [libre-riscv-dev] daily kan-ban update 13may2020
Tobias Platen [Wed, 13 May 2020 13:56:47 +0000 (15:56 +0200)]
Re: [libre-riscv-dev] daily kan-ban update 13may2020
bugzilla-daemon [Wed, 13 May 2020 12:57:37 +0000 (12:57 +0000)]
[libre-riscv-dev] [Bug 309] New: investigate OpenTITAN
Luke Kenneth Casson Leighton [Wed, 13 May 2020 10:28:25 +0000 (11:28 +0100)]
[libre-riscv-dev] daily kan-ban update 13may2020
bugzilla-daemon [Wed, 13 May 2020 09:38:44 +0000 (09:38 +0000)]
[libre-riscv-dev] [Bug 238] POWER Compressed Formal Standard writeup
bugzilla-daemon [Wed, 13 May 2020 09:38:44 +0000 (09:38 +0000)]
[libre-riscv-dev] [Bug 308] POWER variable-length encoding scheme needed
bugzilla-daemon [Wed, 13 May 2020 09:37:52 +0000 (09:37 +0000)]
[libre-riscv-dev] [Bug 308] New: POWER variable-length encoding scheme needed
bugzilla-daemon [Wed, 13 May 2020 09:19:25 +0000 (09:19 +0000)]
[libre-riscv-dev] [Bug 291] HDL Workflow and Coriolis2 chroot automated setup scripts
Benjamin Herrenschmidt [Wed, 13 May 2020 01:41:00 +0000 (11:41 +1000)]
Re: [libre-riscv-dev] [OpenPOWER-HDL-Cores] little-endian only power cores and spec compliance
Luke Kenneth Casson Leighton [Wed, 13 May 2020 09:11:44 +0000 (10:11 +0100)]
Re: [libre-riscv-dev] [OpenPOWER-HDL-Cores] little-endian only power cores and spec compliance
Luke Kenneth Casson Leighton [Wed, 13 May 2020 08:17:20 +0000 (09:17 +0100)]
Re: [libre-riscv-dev] more compatible alternative to BE instructions on LE processor
Luke Kenneth Casson Leighton [Wed, 13 May 2020 08:09:08 +0000 (09:09 +0100)]
Re: [libre-riscv-dev] more compatible alternative to BE instructions on LE processor
Lauri Kasanen [Wed, 13 May 2020 06:29:53 +0000 (09:29 +0300)]
Re: [libre-riscv-dev] more compatible alternative to BE instructions on LE processor
Jacob Lifshay [Wed, 13 May 2020 02:56:45 +0000 (19:56 -0700)]
[libre-riscv-dev] more compatible alternative to BE instructions on LE processor
Jacob Lifshay [Wed, 13 May 2020 02:27:26 +0000 (19:27 -0700)]
Re: [libre-riscv-dev] little-endian only power cores and spec compliance
bugzilla-daemon [Wed, 13 May 2020 02:00:18 +0000 (02:00 +0000)]
[libre-riscv-dev] [Bug 291] HDL Workflow and Coriolis2 chroot automated setup scripts
Hugh Blemings [Wed, 13 May 2020 01:22:01 +0000 (11:22 +1000)]
Re: [libre-riscv-dev] [OpenPOWER-HDL-Cores] little-endian only power cores and spec compliance
bugzilla-daemon [Wed, 13 May 2020 01:19:01 +0000 (01:19 +0000)]
[libre-riscv-dev] [Bug 291] HDL Workflow and Coriolis2 chroot automated setup scripts
bugzilla-daemon [Wed, 13 May 2020 01:05:04 +0000 (01:05 +0000)]
[libre-riscv-dev] [Bug 305] Create Pipelined ALU similar to alu_hier.py
bugzilla-daemon [Wed, 13 May 2020 00:16:35 +0000 (00:16 +0000)]
[libre-riscv-dev] [Bug 291] HDL Workflow and Coriolis2 chroot automated setup scripts
bugzilla-daemon [Wed, 13 May 2020 00:15:00 +0000 (00:15 +0000)]
[libre-riscv-dev] [Bug 291] HDL Workflow and Coriolis2 chroot automated setup scripts
bugzilla-daemon [Wed, 13 May 2020 00:09:29 +0000 (00:09 +0000)]
[libre-riscv-dev] [Bug 291] HDL Workflow and Coriolis2 chroot automated setup scripts
bugzilla-daemon [Tue, 12 May 2020 22:03:35 +0000 (22:03 +0000)]
[libre-riscv-dev] [Bug 307] look at installing a kan-ban board on top of bugzilla
bugzilla-daemon [Tue, 12 May 2020 22:02:08 +0000 (22:02 +0000)]
[libre-riscv-dev] [Bug 305] Create Pipelined ALU similar to alu_hier.py
bugzilla-daemon [Tue, 12 May 2020 21:58:07 +0000 (21:58 +0000)]
[libre-riscv-dev] [Bug 307] look at installing a kan-ban board on top of bugzilla
bugzilla-daemon [Tue, 12 May 2020 21:33:32 +0000 (21:33 +0000)]
[libre-riscv-dev] [Bug 305] Create Pipelined ALU similar to alu_hier.py
bugzilla-daemon [Tue, 12 May 2020 20:56:08 +0000 (20:56 +0000)]
[libre-riscv-dev] [Bug 307] look at installing a kan-ban board on top of bugzilla
bugzilla-daemon [Tue, 12 May 2020 19:41:04 +0000 (19:41 +0000)]
[libre-riscv-dev] [Bug 291] HDL Workflow and Coriolis2 chroot automated setup scripts
Luke Kenneth Casson Leighton [Tue, 12 May 2020 15:56:28 +0000 (16:56 +0100)]
Re: [libre-riscv-dev] PowerISA 3.1 (Power10) spec released
Hendrik Boom [Tue, 12 May 2020 15:11:53 +0000 (11:11 -0400)]
Re: [libre-riscv-dev] PowerISA 3.1 (Power10) spec released
Luke Kenneth Casson Leighton [Tue, 12 May 2020 15:03:51 +0000 (16:03 +0100)]
Re: [libre-riscv-dev] daily kan-ban update 12may2020
Luke Kenneth Casson Leighton [Tue, 12 May 2020 14:53:34 +0000 (15:53 +0100)]
Re: [libre-riscv-dev] daily kan-ban update 12may2020
Luke Kenneth Casson Leighton [Tue, 12 May 2020 14:46:33 +0000 (15:46 +0100)]
Re: [libre-riscv-dev] PowerISA 3.1 (Power10) spec released
Yehowshua [Tue, 12 May 2020 14:42:58 +0000 (10:42 -0400)]
Re: [libre-riscv-dev] daily kan-ban update 12may2020
Michael Nolan [Tue, 12 May 2020 14:28:58 +0000 (10:28 -0400)]
Re: [libre-riscv-dev] daily kan-ban update 12may2020
Tobias Platen [Tue, 12 May 2020 14:00:08 +0000 (16:00 +0200)]
Re: [libre-riscv-dev] daily kan-ban update 12may2020
Hendrik Boom [Tue, 12 May 2020 13:55:32 +0000 (09:55 -0400)]
Re: [libre-riscv-dev] PowerISA 3.1 (Power10) spec released
bugzilla-daemon [Tue, 12 May 2020 12:14:24 +0000 (12:14 +0000)]
[libre-riscv-dev] [Bug 304] Define minimum viable interface set for 180nm ASIC
bugzilla-daemon [Tue, 12 May 2020 12:13:06 +0000 (12:13 +0000)]
[libre-riscv-dev] [Bug 304] Define minimum viable interface set for 180nm ASIC
bugzilla-daemon [Tue, 12 May 2020 12:12:39 +0000 (12:12 +0000)]
[libre-riscv-dev] [Bug 304] Define minimum viable interface set for 180nm ASIC
bugzilla-daemon [Tue, 12 May 2020 12:12:39 +0000 (12:12 +0000)]
[libre-riscv-dev] [Bug 303] define peripheral set for 180nm ASIC
bugzilla-daemon [Tue, 12 May 2020 12:11:22 +0000 (12:11 +0000)]
[libre-riscv-dev] [Bug 303] define peripheral set for 180nm ASIC
bugzilla-daemon [Tue, 12 May 2020 12:11:08 +0000 (12:11 +0000)]
[libre-riscv-dev] [Bug 303] define peripheral set for 180nm ASIC
Luke Kenneth Casson Leighton [Tue, 12 May 2020 10:45:22 +0000 (11:45 +0100)]
[libre-riscv-dev] daily kan-ban update 12may2020
Luke Kenneth Casson Leighton [Tue, 12 May 2020 10:06:52 +0000 (11:06 +0100)]
Re: [libre-riscv-dev] daily kan-ban update 11may2020
bugzilla-daemon [Tue, 12 May 2020 10:03:52 +0000 (10:03 +0000)]
[libre-riscv-dev] [Bug 305] Create Pipelined ALU similar to alu_hier.py
bugzilla-daemon [Tue, 12 May 2020 09:24:33 +0000 (09:24 +0000)]
[libre-riscv-dev] [Bug 305] Create Pipelined ALU similar to alu_hier.py
Luke Kenneth Casson Leighton [Tue, 12 May 2020 09:09:33 +0000 (10:09 +0100)]
Re: [libre-riscv-dev] PowerISA 3.1 (Power10) spec released
Lauri Kasanen [Tue, 12 May 2020 08:50:42 +0000 (11:50 +0300)]
Re: [libre-riscv-dev] PowerISA 3.1 (Power10) spec released
Luke Kenneth Casson Leighton [Tue, 12 May 2020 08:33:52 +0000 (09:33 +0100)]
Re: [libre-riscv-dev] PowerISA 3.1 (Power10) spec released
Luke Kenneth Casson Leighton [Tue, 12 May 2020 08:23:52 +0000 (09:23 +0100)]
Re: [libre-riscv-dev] little-endian only power cores and spec compliance
Lauri Kasanen [Tue, 12 May 2020 08:23:14 +0000 (11:23 +0300)]
Re: [libre-riscv-dev] PowerISA 3.1 (Power10) spec released
Luke Kenneth Casson Leighton [Tue, 12 May 2020 08:11:04 +0000 (09:11 +0100)]
Re: [libre-riscv-dev] learning from a failed business
Luke Kenneth Casson Leighton [Tue, 12 May 2020 08:07:09 +0000 (09:07 +0100)]
Re: [libre-riscv-dev] little-endian only power cores and spec compliance
Luke Kenneth Casson Leighton [Tue, 12 May 2020 07:56:15 +0000 (08:56 +0100)]
Re: [libre-riscv-dev] PowerISA 3.1 (Power10) spec released
Luke Kenneth Casson Leighton [Tue, 12 May 2020 07:50:09 +0000 (08:50 +0100)]
Re: [libre-riscv-dev] PowerISA 3.1 (Power10) spec released
Jacob Lifshay [Tue, 12 May 2020 07:46:22 +0000 (00:46 -0700)]
Re: [libre-riscv-dev] little-endian only power cores and spec compliance
projects / libre-riscv-dev.git / log