mesa.git
8 years agoi965: Allocate URB space for HS and DS stages when required.
Chris Forbes [Tue, 9 Sep 2014 09:30:48 +0000 (21:30 +1200)]
i965: Allocate URB space for HS and DS stages when required.

v2: (by Ken, incorporating feedback from Matt Turner):
- Rewrite the push constant allocation code to be clearer.
- Only apply the minimum VS entries workaround on Gen 8.

v3: (by Ken)
- Fix a bug in v2 where we failed to allocate the full push constant
  space when the number of enabled stages didn't divide the available
  push constant space evenly.  (Any left over space is now allocated
  to the PS, as it was in v1.)
- Fix an off-by-one error in v2's number of enabled stages calculation.
- Use DIV_ROUND_UP for nicer formatting.
- Line wrapping fixes.

Signed-off-by: Chris Forbes <chrisf@ijw.co.nz>
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Kristian Høgsberg <krh@bitplanet.net>
8 years agodocs: mark input/output block locations as DONE
Timothy Arceri [Sun, 13 Dec 2015 05:06:44 +0000 (16:06 +1100)]
docs: mark input/output block locations as DONE

Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
8 years agoglsl: add support for explicit locations inside interface blocks
Timothy Arceri [Mon, 30 Nov 2015 23:34:18 +0000 (10:34 +1100)]
glsl: add support for explicit locations inside interface blocks

This change also adds explicit location support for structs and interfaces which
is currently missing in Mesa but is allowed with SSO and GLSL 1.50+.

Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
8 years agoglsl: simplify interface matching
Timothy Arceri [Wed, 2 Dec 2015 06:53:19 +0000 (17:53 +1100)]
glsl: simplify interface matching

This makes the code easier to follow, should be more efficient
and will makes it easier to add matching via explicit locations
in the following patch.

This patch also replaces the hash table with the newer
resizable hash table this should be more suitable as the table
is likely to only contain a small number of entries.

Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
8 years agodraw: remove clip_vertex from vertex header
Roland Scheidegger [Fri, 11 Dec 2015 23:50:54 +0000 (00:50 +0100)]
draw: remove clip_vertex from vertex header

vertex header had both clip_pos and clip_vertex.
We only really need one (clip_pos) because the draw llvm shader would
overwrite the position output from the vs with the viewport transformed.
However, we don't really need the second one, which was only really used
for gl_ClipVertex - if the shader didn't have that the values were just
duplicated to both clip_pos and clip_vertex. So, just use this from the vs
output instead when we actually need it.
Also change clip debug to output both the data from clip_pos and the
clipVertex output (if available).
Makes some things more complex, some things less complex, but seems more
easy to understand what clipping actually does (and what values it uses
to do its magic).

Reviewed-by: Brian Paul <brianp@vmware.com
Reviewed-by: Jose Fonseca <jfonseca@vmware.com>
8 years agodraw: use clip_pos, not clip_vertex for the fake guardband xy point clipping
Roland Scheidegger [Fri, 11 Dec 2015 22:41:55 +0000 (23:41 +0100)]
draw: use clip_pos, not clip_vertex for the fake guardband xy point clipping

Seems obvious now this should use the data from position and not clip_vertex
(albeit might not really make a difference).

Reviewed-by: Brian Paul <brianp@vmware.com
Reviewed-by: Jose Fonseca <jfonseca@vmware.com>
8 years agodraw: rename vertex header members
Roland Scheidegger [Fri, 11 Dec 2015 22:29:59 +0000 (23:29 +0100)]
draw: rename vertex header members

clip -> clip_vertex and pre_clip_pos -> clip_pos.
Looks more obvious to me what these values actually represent (so use
something resembling the vs output names).

Reviewed-by: Brian Paul <brianp@vmware.com
Reviewed-by: Jose Fonseca <jfonseca@vmware.com>
8 years agodraw: don't pretend have_clipdist is per-vertex
Roland Scheidegger [Fri, 11 Dec 2015 22:14:30 +0000 (23:14 +0100)]
draw: don't pretend have_clipdist is per-vertex

This is just for code cleanup, conceptually the have_clipdist really
isn't per-vertex state, so don't put it there (just dependent on the
shader). Even though there wasn't really any overhead associated with
this, we shouldn't store random shader information in the vertex header.

Reviewed-by: Brian Paul <brianp@vmware.com
Reviewed-by: Jose Fonseca <jfonseca@vmware.com>
8 years agodraw: use position not clipVertex output for xyz view volume clipping
Roland Scheidegger [Fri, 11 Dec 2015 21:49:01 +0000 (22:49 +0100)]
draw: use position not clipVertex output for xyz view volume clipping

I'm pretty sure this should use position (i.e. pre_clip_pos) and not
the output from clipVertex. Albeit piglit doesn't care. It is what we
use in the clip test, and it is what every other driver does (as they
don't even have clipVertex output and lower the additional planes to
clip distances).

Reviewed-by: Brian Paul <brianp@vmware.com
Reviewed-by: Jose Fonseca <jfonseca@vmware.com>
8 years agoi965: Use DIV_ROUND_UP() in gen7_urb.c code.
Kenneth Graunke [Mon, 30 Nov 2015 23:37:44 +0000 (15:37 -0800)]
i965: Use DIV_ROUND_UP() in gen7_urb.c code.

This is a newer convention, which we prefer over ALIGN(x, n) / n.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Kristian Høgsberg <krh@bitplanet.net>
8 years agoi965: Make TES inputs match TCS outputs.
Kenneth Graunke [Thu, 10 Dec 2015 05:42:56 +0000 (21:42 -0800)]
i965: Make TES inputs match TCS outputs.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
8 years agoi965: Force VS -> TCS varyings to use the SSO VUE map layout.
Kenneth Graunke [Thu, 10 Dec 2015 05:42:21 +0000 (21:42 -0800)]
i965: Force VS -> TCS varyings to use the SSO VUE map layout.

The compact VUE map only works when varying packing is in use.
Unfortunately, varying packing is disabled for TCS inputs.

This is needed to fix Piglit's tcs-input-read-array-interface test.

v2: Make lines fit in 80 columns (caught by Jordan Justen).

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
8 years agoi965: Handle TCS outputs and TES inputs.
Kenneth Graunke [Thu, 10 Dec 2015 05:41:35 +0000 (21:41 -0800)]
i965: Handle TCS outputs and TES inputs.

TCS outputs and TES inputs both refer to a common "patch URB entry"
shared across all invocations.  First, there are some number of
per-patch entries.  Then, there are per-vertex entries accessed via
an offset for the variable and a stride times the vertex index.

Because these calculations need to be done in both the vec4 and scalar
backends, it's simpler to just compute the offset calculations in NIR.
It doesn't necessarily make much sense to use per-vertex intrinsics
afterwards, but that at least means we don't lose the per-patch vs.
per-vertex information.

v2: Use is_input/is_output helpers (suggested by Jordan Justen).

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
8 years agoi965: Handle TCS inputs and TES outputs.
Kenneth Graunke [Thu, 10 Dec 2015 05:39:27 +0000 (21:39 -0800)]
i965: Handle TCS inputs and TES outputs.

TES outputs work exactly like VS outputs, so we can simply add a case
statement for those.

TCS inputs are very similar to geometry shaders - they're arrays of
per-vertex data.  We use the same method I used for the scalar GS
backend.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
8 years agoi965: Add tessellation shader VUE map code.
Kenneth Graunke [Tue, 10 Nov 2015 09:17:04 +0000 (01:17 -0800)]
i965: Add tessellation shader VUE map code.

Based on a patch by Chris Forbes, but largely rewritten by Ken.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
8 years agoi965: Fix partial variable access for geometry shaders in SSO mode.
Kenneth Graunke [Thu, 10 Dec 2015 02:26:19 +0000 (18:26 -0800)]
i965: Fix partial variable access for geometry shaders in SSO mode.

Without varying packing, if a VS writes a compound variable, and the GS
only reads part of it, the base location of the variable may not
actually be in the VUE map.

To cope with this, we do lowering in terms of varying slots, add any
constant offsets to the base, and then do the VUE map remapping.  This
ensures we only look up VUE map entries for slots which actually exist.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
8 years agoi965: Separate base offset/constant offset combining from remapping.
Kenneth Graunke [Wed, 9 Dec 2015 10:37:52 +0000 (02:37 -0800)]
i965: Separate base offset/constant offset combining from remapping.

My tessellation branch has two additional remap functions.  I don't want
to replicate this logic there.

v2: Handle inputs/outputs separately (suggested by Jason Ekstrand).

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
8 years agonir: Fix number of indices on shared variable store intrinsics.
Kenneth Graunke [Mon, 14 Dec 2015 09:45:55 +0000 (01:45 -0800)]
nir: Fix number of indices on shared variable store intrinsics.

Shared variables and input reworks landed around the same time.
Presumably, this was some sort of mistake in rebase conflict resolution.

This really only affects the num_indices field in nir_intrinsic_infos,
which is rarely used.  However, it's used by the printer.

Found by inspection.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
8 years agometa/generate_mipmap: Work-around GLES 1.x problem with GL_DRAW_FRAMEBUFFER
Ian Romanick [Thu, 3 Dec 2015 20:22:23 +0000 (12:22 -0800)]
meta/generate_mipmap: Work-around GLES 1.x problem with GL_DRAW_FRAMEBUFFER

GL_DRAW_FRAMEBUFFER does not exist in OpenGL ES 1.x, and since
_mesa_meta_begin hasn't been called yet, we have to work-around API
difficulties.  The whole reason that GL_DRAW_FRAMEBUFFER is used instead
of GL_FRAMEBUFFER is that the read framebuffer may be different.  This
is moot in OpenGL ES 1.x.

I have another patch series that would also fix this (by removing the
calls to _mesa_BindFramebuffer and friends), but it's not quite ready
yet... and I think it may be a bit heavy for some stable branches.
Consider this a stop-gap fix.

Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=93215
Cc: "11.0 11.1" <mesa-stable@lists.freedesktop.org>
Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com>
8 years agonvc0: check return value of nvc0_program_validate()
Samuel Pitoiset [Mon, 14 Dec 2015 17:07:33 +0000 (18:07 +0100)]
nvc0: check return value of nvc0_program_validate()

Spotted by Coverity.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
8 years agonv50: check return value of nouveau_object_new()
Samuel Pitoiset [Mon, 14 Dec 2015 16:51:59 +0000 (17:51 +0100)]
nv50: check return value of nouveau_object_new()

When ret == 0, obj is not NULL. Spotted by Coverity.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
8 years agonv50,nvc0: make use of unreachable() when invalid texture target happens
Samuel Pitoiset [Mon, 14 Dec 2015 16:51:57 +0000 (17:51 +0100)]
nv50,nvc0: make use of unreachable() when invalid texture target happens

Spotted by Coverity.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
8 years agost/va: handle default post process regions
Christian König [Mon, 7 Dec 2015 19:21:57 +0000 (20:21 +0100)]
st/va: handle default post process regions

Avoid referencing NULL pointers.

Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Julien Isorce <j.isorce@samsung.com>
Tested-by: Julien Isorce <j.isorce@samsung.com>
8 years agost/va: fix unused variable warning
Christian König [Mon, 7 Dec 2015 19:36:21 +0000 (20:36 +0100)]
st/va: fix unused variable warning

Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Julien Isorce <j.isorce@samsung.com>
8 years agost/va: clean up post process includes
Christian König [Sat, 5 Dec 2015 12:42:28 +0000 (13:42 +0100)]
st/va: clean up post process includes

Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Julien Isorce <j.isorce@samsung.com>
Tested-by: Julien Isorce <j.isorce@samsung.com>
8 years agost/va: cleanup filter color standard handling
Christian König [Fri, 4 Dec 2015 13:25:10 +0000 (14:25 +0100)]
st/va: cleanup filter color standard handling

Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Julien Isorce <j.isorce@samsung.com>
Tested-by: ulien Isorce <j.isorce@samsung.com>
8 years agometa: clear_state structure cleanup
Tapani Pälli [Fri, 11 Dec 2015 08:45:28 +0000 (10:45 +0200)]
meta: clear_state structure cleanup

Remove unused variables from clear_state and use a hardcoded location
for color uniform to get rid of 2 more variables. Modify shaders to use
explicit location for vertex attribute too as extension is enabled.

Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Kristian Høgsberg <krh@bitplanet.net>
8 years agoglsl: assign varying locations to tess shaders when doing SSO
Ilia Mirkin [Sun, 13 Dec 2015 08:23:13 +0000 (03:23 -0500)]
glsl: assign varying locations to tess shaders when doing SSO

GRID Autosport uses SSO shaders. When a tessellation evaluation shader
is passed through this, it triggers assertion failures down the line
with unassigned varying locations. Make sure to do this when the first
shader in the pipeline is not a vertex shader.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Timothy Arceri <timothy.arceri@collabora.com>
Cc: "11.0 11.1" <mesa-stable@lists.freedesktop.org>
8 years agoi965: Use MESA_FORMAT_B8G8R8X8_SRGB for RGB visuals
Neil Roberts [Fri, 11 Dec 2015 12:32:18 +0000 (12:32 +0000)]
i965: Use MESA_FORMAT_B8G8R8X8_SRGB for RGB visuals

Previously if the visual didn't have an alpha channel then it would
pick a format that is not sRGB-capable. I don't think there's any
reason not to always have an sRGB-capable visual. Since 28090b30 there
are now visuals advertised without an alpha channel which means that
games that don't request alpha bits in the config would end up without
an sRGB-capable visual. This was breaking supertuxkart which assumes
the winsys buffer is always sRGB-capable.

The previous code always used an RGBA format if the visual config
itself was marked as sRGB-capable regardless of whether the visual has
alpha bits. I think we don't actually advertise any sRGB-capable
visuals (but we just use sRGB formats anyway) so it shouldn't make any
difference. However this patch also changes it to use RGBX if an
sRGB-capable visual is requested without alpha bits for consistency.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=92759
Cc: "11.0 11.1" <mesa-stable@lists.freedesktop.org>
Cc: Ilia Mirkin <imirkin@alum.mit.edu>
Suggested-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Kristian Høgsberg <krh@bitplanet.net>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
8 years agoi965: Add B8G8R8X8_SRGB to the alpha format override
Neil Roberts [Fri, 11 Dec 2015 12:32:17 +0000 (12:32 +0000)]
i965: Add B8G8R8X8_SRGB to the alpha format override

brw_init_surface_formats overrides the render format for RGBX formats
which aren't supported for rendering so that they internally use RGBA
instead. However, B8G8R8X8_SRGB was missing so it wasn't marked as a
renderable format. This patch just adds it.

Cc: "11.0 11.1" <mesa-stable@lists.freedesktop.org>
Cc: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
8 years agoi965: Add MESA_FORMAT_B8G8R8X8_SRGB to brw_format_for_mesa_format
Neil Roberts [Fri, 11 Dec 2015 12:32:16 +0000 (12:32 +0000)]
i965: Add MESA_FORMAT_B8G8R8X8_SRGB to brw_format_for_mesa_format

This will be used in a subsequent patch as the format for RGB visuals.

Cc: "11.0 11.1" <mesa-stable@lists.freedesktop.org>
Cc: Ilia Mirkin <imirkin@alum.mit.edu>
Suggested-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
8 years agogk104/ir: simplify and fool-proof texbar algorithm
Ilia Mirkin [Thu, 10 Dec 2015 23:19:44 +0000 (18:19 -0500)]
gk104/ir: simplify and fool-proof texbar algorithm

With the current algorithm, we only look at tex uses. However there's a
write-after-write hazard where we might decide to, on some path, not use
a texture's output at all, but instead to write a different value to
that register. However without the barrier, the texture might complete
later and overwrite that value.

This fixes Unreal Elemental demo on GK110/GK208, flightgear on GK10x,
and likely other random-looking failures.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Cc: "11.1" <mesa-stable@lists.freedesktop.org>
8 years agonv50/ir: combine sequences of conversions
Ilia Mirkin [Thu, 10 Dec 2015 20:24:47 +0000 (15:24 -0500)]
nv50/ir: combine sequences of conversions

In some cases shaders want non-default rounding when converting float to
integer. This can be done in one go, so merge the two ops. This comes up
in the packUnorm4x8 & co functions, as well as a few random shaders.
Overall shader-db impact is minimal, helping a handful of witcher2 and
other misc shaders.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
8 years agonv50/ir: manually optimize multiplication expansion logic
Ilia Mirkin [Fri, 11 Dec 2015 05:40:15 +0000 (00:40 -0500)]
nv50/ir: manually optimize multiplication expansion logic

The conversion of 32-bit integer multiplies into 16-bit ones happens
after the regular optimization loop. However it's fairly common to
multiply by a small integer, rendering some of the expansion pointless.

Firstly, propagate immediates when possible into mul ops, secondly just
remove the ops when they are unnecessary.

Including the change to generate imad immediates, the effect is:

total instructions in shared programs : 6365463 -> 6351898 (-0.21%)
total gprs used in shared programs    : 728684 -> 728684 (0.00%)
total local used in shared programs   : 9904 -> 9904 (0.00%)
total bytes used in shared programs   : 44001576 -> 44036120 (0.08%)

                local        gpr       inst      bytes
    helped           0           0        3288           4
      hurt           0           0           0         842

It's easy for this to hurt bytes since we end up always generating the
8-byte form, while we can't always get rid of the immediate in question.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
8 years agonv50/ir: fix imul emission in the presence of an immediate
Ilia Mirkin [Fri, 11 Dec 2015 05:39:47 +0000 (00:39 -0500)]
nv50/ir: fix imul emission in the presence of an immediate

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
8 years agonv50/ir: teach post-ra immediate folding into mad about integers
Ilia Mirkin [Fri, 11 Dec 2015 03:50:31 +0000 (22:50 -0500)]
nv50/ir: teach post-ra immediate folding into mad about integers

There will usually be a split before the mad op, peer through that and
pick out the right word of the immediate.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
8 years agonv50/ir: add short imad support
Ilia Mirkin [Fri, 11 Dec 2015 02:20:32 +0000 (21:20 -0500)]
nv50/ir: add short imad support

Support emission of the short imad, but also include it in the various
logic that tries to make it possible to emit.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
8 years agonv50/ir: can't have predication and immediates
Ilia Mirkin [Thu, 10 Dec 2015 17:18:51 +0000 (12:18 -0500)]
nv50/ir: can't have predication and immediates

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Cc: "11.0 11.1" <mesa-stable@lists.freedesktop.org>
8 years agonv50/ir: fix texture grad for cubemaps
Ilia Mirkin [Wed, 9 Dec 2015 06:47:19 +0000 (01:47 -0500)]
nv50/ir: fix texture grad for cubemaps

We were ignoring the partial derivatives on the last dim.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
8 years agonv50/ir: fix assumption that prog->maxGPR is in 32-bit reg units
Ilia Mirkin [Wed, 9 Dec 2015 04:55:18 +0000 (23:55 -0500)]
nv50/ir: fix assumption that prog->maxGPR is in 32-bit reg units

On NV50, we use 16-bit reg units (to make it all work with half-regs). A
few places assumed that it was always in 32-bit units.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
8 years agogallium/ddebug: regularly log the total number of draw calls
Nicolai Hähnle [Tue, 8 Dec 2015 22:56:23 +0000 (17:56 -0500)]
gallium/ddebug: regularly log the total number of draw calls

This helps in the use of GALLIUM_DDEBUG_SKIP: first run a target application
with skip set to a very large number and note how many draw calls happen
before the bug. Then re-run, skipping the corresponding number of calls.
Despite the additional run, this can still be much faster than not skipping
anything.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
8 years agogallium/ddebug: add GALLIUM_DDEBUG_SKIP option
Nicolai Hähnle [Tue, 8 Dec 2015 11:49:12 +0000 (06:49 -0500)]
gallium/ddebug: add GALLIUM_DDEBUG_SKIP option

When we know that hangs occur only very late in a reproducible run (e.g.
apitrace), we can save a lot of debugging time by skipping the flush and hang
detection for earlier draw calls.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
8 years agollvmpipe: fix layer/vp input into fs when not written by prior stages
Roland Scheidegger [Wed, 9 Dec 2015 03:56:15 +0000 (04:56 +0100)]
llvmpipe: fix layer/vp input into fs when not written by prior stages

ARB_fragment_layer_viewport requires that if a fs reads layer or viewport
index but it wasn't output by gs (or vs with other extensions), then it reads
0. This never worked for llvmpipe, and is surprisingly non-trivial to fix.
The problem is the mechanism to handle non-existing outputs in draw is rather
crude, it will simply redirect them to whatever is at output 0, thus later
stages will just get garbage. So, rather than trying to fix this up (which
looks non-trivial), fix this up in llvmpipe setup by detecting this case there
and output a fixed zero directly.
While here, also optimize the hw vertex layout a bit - previously if the gs
outputted layer (or vp) and the fs read those inputs, we'd add them twice
to the vertex layout, which is unnecessary.
And do some minor cleanup, slots don't require that many bits, there was some
bogus (but harmless) float/int mixup for psize slot too, make the slots all
unsigned (we always put pos at pos zero thus everything else has to be positive
if it exists), and make sure they are properly initialized (layer and vp index
slot were not which looked fishy as they might not have got set back to zero
when changing from a gs which outputs them to one which does not).

This fixes the failures in piglit's arb_fragment_layer_viewport group
(3 each for layer and vp).

Reviewed-by: Jose Fonseca <jfonseca@vmware.com>
8 years agosvga: avoid emitting redundant SetSamplers() commands
Brian Paul [Thu, 10 Dec 2015 21:55:33 +0000 (14:55 -0700)]
svga: avoid emitting redundant SetSamplers() commands

This greatly reduces the number of SetSamplers() commands for some
applications.

Reviewed-by: José Fonseca <jfonseca@vmware.com>
Reviewed-by: Charmaine Lee <charmainel@vmware.com>
8 years agosvga: avoid emitting redundant SetIndexBuffer commands
Brian Paul [Wed, 9 Dec 2015 19:54:35 +0000 (12:54 -0700)]
svga: avoid emitting redundant SetIndexBuffer commands

Reviewed-by: Charmaine Lee <charmainel@vmware.com>
Reviewed-by: José Fonseca <jfonseca@vmware.com>
8 years agost/mesa: trivial indentation fix
Brian Paul [Thu, 10 Dec 2015 19:25:22 +0000 (12:25 -0700)]
st/mesa: trivial indentation fix

8 years agoutil/blitter: minor formatting fixes
Brian Paul [Thu, 10 Dec 2015 19:25:04 +0000 (12:25 -0700)]
util/blitter: minor formatting fixes

8 years agoi965/fs: Use the correct source for local memory load offsets
Jason Ekstrand [Fri, 11 Dec 2015 19:59:53 +0000 (11:59 -0800)]
i965/fs: Use the correct source for local memory load offsets

The offset for loads is in src[0].  This was a copy+paste error in the
nir_intrinsic_load/store refactoring.  This commit fixes a segfault in
ES31-CTS.compute_shader.work-group-size.  I have no idea how piglit failed
to catch this...

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=93348
Reviewed-by: Kristian Høgsberg <krh@bitplanet.net>
8 years agoi965: Add Gen8+ tessellation control shader state (3DSTATE_HS).
Kenneth Graunke [Thu, 12 Nov 2015 07:22:06 +0000 (23:22 -0800)]
i965: Add Gen8+ tessellation control shader state (3DSTATE_HS).

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
8 years agoi965: Add Gen7+ tessellation engine state (3DSTATE_TE).
Kenneth Graunke [Thu, 12 Nov 2015 07:15:23 +0000 (23:15 -0800)]
i965: Add Gen7+ tessellation engine state (3DSTATE_TE).

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
8 years agoi965: Add Gen8+ tessellation evaluation shader state (3DSTATE_DS).
Kenneth Graunke [Tue, 10 Nov 2015 22:35:27 +0000 (14:35 -0800)]
i965: Add Gen8+ tessellation evaluation shader state (3DSTATE_DS).

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
8 years agoi965: Add tessellation shader push constant support.
Kenneth Graunke [Thu, 1 Oct 2015 00:04:23 +0000 (17:04 -0700)]
i965: Add tessellation shader push constant support.

Based on a patch by Chris Forbes.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
8 years agoi965: Add tessellation shader sampler support.
Kenneth Graunke [Sat, 10 Oct 2015 00:07:23 +0000 (17:07 -0700)]
i965: Add tessellation shader sampler support.

Based on code by Chris Forbes and Fabian Bieler.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
8 years agoi965: Add tessellation shader surface support.
Kenneth Graunke [Wed, 30 Sep 2015 22:42:54 +0000 (15:42 -0700)]
i965: Add tessellation shader surface support.

This is brw_gs_surface_state.c copy and pasted twice with search and
replace.

brw_binding_table.c code is similarly copy and pasted.

v2: Drop dword_pitch related fields.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Acked-by: Jason Ekstrand <jason.ekstrand@intel.com>
8 years agoi965: Make fs_visitor::emit_urb_writes set EOT for TES as well.
Kenneth Graunke [Wed, 2 Dec 2015 01:52:58 +0000 (17:52 -0800)]
i965: Make fs_visitor::emit_urb_writes set EOT for TES as well.

Tessellation evaluation shaders work almost identically to vertex
shaders - we have a set of URB writes at the end of the program, and the
last one should terminate it.

Geometry shaders really are the special case, where multiple
EmitVertex() calls trigger URB writes in the middle of the program.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
Reviewed-by: Kristian Høgsberg <krh@bitplanet.net>
8 years agoi965: Don't hardcode g1 for URB handles in fs_visitor::emit_urb_writes().
Kenneth Graunke [Wed, 2 Dec 2015 01:51:33 +0000 (17:51 -0800)]
i965: Don't hardcode g1 for URB handles in fs_visitor::emit_urb_writes().

Tessellation evaluation shaders will use g4 instead.  For now, make an
fs_reg called urb_handle and use that in place of hardcoding g1.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
Reviewed-by: Kristian Høgsberg <krh@bitplanet.net>
8 years agoi965: Make brw_set_message_descriptor() non-static.
Kenneth Graunke [Wed, 2 Dec 2015 02:20:54 +0000 (18:20 -0800)]
i965: Make brw_set_message_descriptor() non-static.

I want to use this directly from brw_vec4_generator.cpp.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
Reviewed-by: Kristian Høgsberg <krh@bitplanet.net>
8 years agoi965: Move brw_cs_fill_local_id_payload() to libi965_compiler
Kristian Høgsberg Kristensen [Fri, 11 Dec 2015 19:18:18 +0000 (11:18 -0800)]
i965: Move brw_cs_fill_local_id_payload() to libi965_compiler

This is a helper function for setting up the local invocation ID
payload according to the cs_prog_data generated by the compiler. It's
intended to be available to users of libi965_compiler so move it there.

8 years agovc4: Add quick algebraic optimization for clamping of unpacked values.
Eric Anholt [Fri, 11 Dec 2015 05:54:41 +0000 (21:54 -0800)]
vc4: Add quick algebraic optimization for clamping of unpacked values.

GL likes to saturate your incoming color, but if that color's coming from
unpacking from unorms, there's no point.  Ideally we'd have a range
propagation pass that cleans these up in NIR, but that doesn't seem to be
going to land soon.  It seems like we could do a one-off optimization in
nir_opt_algebraic, except that doesn't want to operate on expressions
involving unpack_unorm_4x8, since it's sized.

total instructions in shared programs: 87879 -> 87761 (-0.13%)
instructions in affected programs:     6044 -> 5926 (-1.95%)
total estimated cycles in shared programs: 349457 -> 349252 (-0.06%)
estimated cycles in affected programs:     6172 -> 5967 (-3.32%)

No SSPD on openarena (which had the biggest gains, in its VS/CSes), n=15.

8 years agovc4: When doing algebraic optimization into a MOV, use the right MOV.
Eric Anholt [Fri, 11 Dec 2015 06:02:30 +0000 (22:02 -0800)]
vc4: When doing algebraic optimization into a MOV, use the right MOV.

If there were src unpacks, changing to the integer MOV instead of float
(for example) would change the unpack operation.

8 years agovc4: Fix handling of src packs on in qir_follow_movs().
Eric Anholt [Fri, 11 Dec 2015 06:23:10 +0000 (22:23 -0800)]
vc4: Fix handling of src packs on in qir_follow_movs().

The caller isn't going to expect it from a return, so it would probably
get misinterpreted.  If the caller had an unpack in its reg, that's fine,
but don't lose track of it.

8 years agovc4: Add missing progress note in opt_algebraic.
Eric Anholt [Fri, 11 Dec 2015 05:51:03 +0000 (21:51 -0800)]
vc4: Add missing progress note in opt_algebraic.

8 years agovc4: Add debugging of the estimated time to run the shader to shader-db.
Eric Anholt [Wed, 9 Dec 2015 01:55:36 +0000 (17:55 -0800)]
vc4: Add debugging of the estimated time to run the shader to shader-db.

8 years agovc4: Fix handling of sample_mask output.
Eric Anholt [Wed, 9 Dec 2015 01:18:37 +0000 (17:18 -0800)]
vc4: Fix handling of sample_mask output.

I apparently broke this in a late refactor, in such a way that I decided
its tests were some of those interminable ones that I should just
blacklist from my testing.  As a result, the refactors related to it were
totally wrong.

8 years agosoftpipe: enable GL_ARB_viewport_array support, update GL3.txt doc
Edward O'Callaghan [Fri, 11 Dec 2015 11:43:31 +0000 (22:43 +1100)]
softpipe: enable GL_ARB_viewport_array support, update GL3.txt doc

Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
8 years agosoftpipe: implement some support for multiple viewports
Edward O'Callaghan [Fri, 11 Dec 2015 11:43:30 +0000 (22:43 +1100)]
softpipe: implement some support for multiple viewports

Mostly related to making sure the rasterizer can correctly
pick out the correct scissor box for the current viewport.

Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
8 years agodraw: don't assume fixed offset for data in struct vertex_info
Roland Scheidegger [Fri, 11 Dec 2015 03:53:21 +0000 (04:53 +0100)]
draw: don't assume fixed offset for data in struct vertex_info

Otherwise, if struct vertex_info is changed, you're in for some surprises...

Reviewed-by: Jose Fonseca <jfonseca@vmware.com>
8 years agoi965/gen9: Don't do fast clears when GL_FRAMEBUFFER_SRGB is enabled
Neil Roberts [Wed, 25 Nov 2015 11:14:37 +0000 (12:14 +0100)]
i965/gen9: Don't do fast clears when GL_FRAMEBUFFER_SRGB is enabled

When GL_FRAMEBUFFER_SRGB is enabled any single-sampled renderbuffers
are resolved in intel_update_state because the hardware can't cope
with fast clears on SRGB buffers. In that case it's pointless to do a
fast clear because it will just be immediately resolved.

Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
8 years agoi965/gen9: Allow fast clears for non-MSRT SRGB buffers
Neil Roberts [Tue, 24 Nov 2015 15:34:46 +0000 (16:34 +0100)]
i965/gen9: Allow fast clears for non-MSRT SRGB buffers

SRGB buffers are not marked as losslessly compressible so previously
they would not be used for fast clears. However in practice the
hardware will never actually see that we are using SRGB buffers for
fast clears if we use the linear equivalent format when clearing and
make sure to resolve the buffer as a linear format before sampling
from it.

This is an important use case because by default the window system
framebuffers are created as SRGB so without this fast clears won't be
used there.

Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
8 years agoi965/gen9: Resolve SRGB color buffers when GL_FRAMEBUFFER_SRGB enabled
Neil Roberts [Tue, 24 Nov 2015 18:23:14 +0000 (19:23 +0100)]
i965/gen9: Resolve SRGB color buffers when GL_FRAMEBUFFER_SRGB enabled

SKL can't cope with the CCS buffer for SRGB buffers. Normally the
hardware won't see the SRGB formats because when GL_FRAMEBUFFER_SRGB
is disabled these get mapped to their linear equivalents. In order to
avoid relying on the CCS buffer when it is enabled this patch now
makes it flush the renderbuffers.

Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
8 years agoi965/gen8+: Don't upload the MCS buffer for single-sampled textures
Neil Roberts [Tue, 24 Nov 2015 16:59:28 +0000 (17:59 +0100)]
i965/gen8+: Don't upload the MCS buffer for single-sampled textures

For single-sampled textures the MCS buffer is only used to implement
fast clears. However the surface always needs to be resolved before
being used as a texture anyway so the the MCS buffer doesn't actually
achieve anything. This is important for Gen9 because in that case SRGB
surfaces are not supported for fast clears and we don't want the
hardware to see the MCS buffer in that case.

Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
8 years agoi965/meta-fast-clear: Disable GL_FRAMEBUFFER_SRGB during clear
Neil Roberts [Tue, 24 Nov 2015 16:01:03 +0000 (17:01 +0100)]
i965/meta-fast-clear: Disable GL_FRAMEBUFFER_SRGB during clear

Adds MESA_META_FRAMEBUFFER_SRGB to the meta save state so that
GL_FRAMEBUFFER_SRGB will be disabled when performing the fast clear.
That way the render surface state will be programmed with the linear
equivalent format during the clear. This is important for Gen9 because
the SRGB formats are not marked as losslessly compressible so in
theory they aren't support for fast clears. It shouldn't make any
difference whether GL_FRAMEBUFFER_SRGB is enabled for the fast clear
operation because the color is not actually written to the framebuffer
so there is no chance for the hardware to apply the SRGB conversion on
it anyway.

Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
8 years agowinsys/amdgpu: clear the buffer cache on mmap failure and try again
Marek Olšák [Wed, 9 Dec 2015 21:45:56 +0000 (22:45 +0100)]
winsys/amdgpu: clear the buffer cache on mmap failure and try again

Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
8 years agowinsys/radeon: clear the buffer cache on mmap failure and try again
Marek Olšák [Wed, 9 Dec 2015 21:45:56 +0000 (22:45 +0100)]
winsys/radeon: clear the buffer cache on mmap failure and try again

Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
8 years agowinsys/amdgpu: clear the buffer cache on allocation failure and try again
Marek Olšák [Wed, 9 Dec 2015 21:36:26 +0000 (22:36 +0100)]
winsys/amdgpu: clear the buffer cache on allocation failure and try again

Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
8 years agowinsys/radeon: clear the buffer cache on allocation failure and try again
Marek Olšák [Wed, 9 Dec 2015 21:36:26 +0000 (22:36 +0100)]
winsys/radeon: clear the buffer cache on allocation failure and try again

Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
8 years agogallium/radeon: remove radeon_winsys_cs_handle
Marek Olšák [Sun, 6 Dec 2015 23:00:59 +0000 (00:00 +0100)]
gallium/radeon: remove radeon_winsys_cs_handle

"radeon_winsys_cs_handle *cs_buf" is now equivalent to "pb_buffer *buf".

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
8 years agowinsys/radeon: use pb_cache instead of pb_cache_manager
Marek Olšák [Sun, 6 Dec 2015 19:57:05 +0000 (20:57 +0100)]
winsys/radeon: use pb_cache instead of pb_cache_manager

This is a prerequisite for the removal of radeon_winsys_cs_handle.

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
8 years agowinsys/radeon: use radeon_bomgr less
Marek Olšák [Sun, 6 Dec 2015 21:48:45 +0000 (22:48 +0100)]
winsys/radeon: use radeon_bomgr less

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
8 years agowinsys/radeon: rename radeon_bomgr_init_functions
Marek Olšák [Sun, 6 Dec 2015 21:34:01 +0000 (22:34 +0100)]
winsys/radeon: rename radeon_bomgr_init_functions

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
8 years agowinsys/radeon: move variables from radeon_bomgr to radeon_drm_winsys
Marek Olšák [Sun, 6 Dec 2015 21:32:33 +0000 (22:32 +0100)]
winsys/radeon: move variables from radeon_bomgr to radeon_drm_winsys

radeon_bomgr is going away.

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
8 years agowinsys/radeon: remove redundant radeon_bomgr::va
Marek Olšák [Sun, 6 Dec 2015 21:10:04 +0000 (22:10 +0100)]
winsys/radeon: remove redundant radeon_bomgr::va

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
8 years agowinsys/amdgpu: don't use the "rws" abbreviation for amdgpu_winsys
Marek Olšák [Sun, 6 Dec 2015 21:19:38 +0000 (22:19 +0100)]
winsys/amdgpu: don't use the "rws" abbreviation for amdgpu_winsys

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
8 years agowinsys/amdgpu: use pb_cache instead of pb_cache_manager
Marek Olšák [Sun, 6 Dec 2015 19:57:05 +0000 (20:57 +0100)]
winsys/amdgpu: use pb_cache instead of pb_cache_manager

This is a prerequisite for the removal of radeon_winsys_cs_handle.

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
8 years agogallium/pb_bufmgr_cache: use the new pb_cache module
Marek Olšák [Sun, 6 Dec 2015 23:23:06 +0000 (00:23 +0100)]
gallium/pb_bufmgr_cache: use the new pb_cache module

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Acked-by: Michel Dänzer <michel.daenzer@amd.com>
8 years agogallium/pb_cache: add a copy of cache bufmgr independent of pb_manager
Marek Olšák [Sun, 6 Dec 2015 18:38:26 +0000 (19:38 +0100)]
gallium/pb_cache: add a copy of cache bufmgr independent of pb_manager

This simplified (basically duplicated) version of pb_cache_manager will
allow removing some ugly hacks from radeon and amdgpu winsyses and
flatten simplify their design.

The difference is that winsyses must manually add buffers to the cache
in "destroy" functions and the cache doesn't know about the buffers before
that. The integration is therefore trivial and the impact on the winsys
design is negligible.

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Acked-by: Michel Dänzer <michel.daenzer@amd.com>
8 years agoradeonsi: implement fast stencil clear
Marek Olšák [Thu, 10 Dec 2015 00:37:39 +0000 (01:37 +0100)]
radeonsi: implement fast stencil clear

Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
8 years agoradeonsi: re-enable Hyper-Z for stencil
Marek Olšák [Tue, 8 Dec 2015 16:33:55 +0000 (17:33 +0100)]
radeonsi: re-enable Hyper-Z for stencil

Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
8 years agor600g: remove a Hyper-Z workaround that's likely not needed anymore
Marek Olšák [Thu, 10 Dec 2015 00:46:17 +0000 (01:46 +0100)]
r600g: remove a Hyper-Z workaround that's likely not needed anymore

FORCE_OFF == 0, no need to set that

Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
8 years agor600g: re-enable Hyper-Z for stencil on Evergreen & Cayman
Marek Olšák [Thu, 10 Dec 2015 00:40:14 +0000 (01:40 +0100)]
r600g: re-enable Hyper-Z for stencil on Evergreen & Cayman

Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
8 years agogallium/radeon: fix Hyper-Z hangs by programming PA_SC_MODE_CNTL_1 correctly
Marek Olšák [Wed, 9 Dec 2015 19:26:21 +0000 (20:26 +0100)]
gallium/radeon: fix Hyper-Z hangs by programming PA_SC_MODE_CNTL_1 correctly

This is the recommended setting according to hw people and it makes Hyper-Z
stable. Just the two magic states.

This fixes Evergreen, Cayman, SI, CI, VI (using the Cayman code).

Cc: 11.0 11.1 <mesa-stable@lists.freedesktop.org>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
8 years agoradeonsi: don't use the CP DMA workaround on Fiji and newer
Marek Olšák [Fri, 4 Dec 2015 20:24:46 +0000 (21:24 +0100)]
radeonsi: don't use the CP DMA workaround on Fiji and newer

Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
8 years agoradeonsi: apply the streamout workaround to Fiji as well
Marek Olšák [Fri, 4 Dec 2015 20:24:21 +0000 (21:24 +0100)]
radeonsi: apply the streamout workaround to Fiji as well

Cc: 11.0 11.1 <mesa-stable@lists.freedesktop.org>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
8 years agoradeonsi: also print hexadecimal values for register fields in the IB parser
Marek Olšák [Wed, 9 Dec 2015 22:39:45 +0000 (23:39 +0100)]
radeonsi: also print hexadecimal values for register fields in the IB parser

Reviewed-by: Michel Dänzer <michel.daenzer@amd.com
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
8 years agoradeonsi: implement RB+ for Stoney (v2)
Marek Olšák [Tue, 1 Dec 2015 13:56:54 +0000 (14:56 +0100)]
radeonsi: implement RB+ for Stoney (v2)

v2: fix dual source blending

Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
8 years agoradeonsi: don't call of u_prims_for_vertices for patches and rectangles
Marek Olšák [Wed, 9 Dec 2015 21:14:32 +0000 (22:14 +0100)]
radeonsi: don't call of u_prims_for_vertices for patches and rectangles

Both caused a crash due to a division by zero in that function.
This is an alternative fix.

Cc: 11.0 11.1 <mesa-stable@lists.freedesktop.org>
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
8 years agoradeonsi: use tgsi_shader_info::colors_written
Marek Olšák [Thu, 10 Dec 2015 12:16:58 +0000 (13:16 +0100)]
radeonsi: use tgsi_shader_info::colors_written

Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
8 years agor600g: write all MRTs only if there is exactly one output (fixes a hang)
Marek Olšák [Thu, 10 Dec 2015 12:19:45 +0000 (13:19 +0100)]
r600g: write all MRTs only if there is exactly one output (fixes a hang)

This fixes a hang in
piglit/arb_blend_func_extended-fbo-extended-blend-pattern_gles2 on REDWOOD.

Cc: 11.0 11.1 <mesa-stable@lists.freedesktop.org>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
8 years agotgsi/scan: add flag colors_written
Marek Olšák [Thu, 10 Dec 2015 12:15:50 +0000 (13:15 +0100)]
tgsi/scan: add flag colors_written

This is a prerequisite for the following r600g fix.

Cc: 11.0 11.1 <mesa-stable@lists.freedesktop.org>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
8 years agoRevert "radeonsi: disable DCC on Stoney"
Marek Olšák [Fri, 11 Dec 2015 14:08:00 +0000 (15:08 +0100)]
Revert "radeonsi: disable DCC on Stoney"

This reverts commit 32f05fadbbdf2a3fb60055e610bbbdcd82dd3ce5.

It turned out the problem with Stoney was caused by incorrect handling of
a non-power-two VRAM size in the kernel driver.
This is an optional BIOS setting and can be worked around by choosing
a different VRAM size in the BIOS.

Cc: 11.1 <mesa-stable@lists.freedesktop.org>