Jieming Yin [Mon, 21 Nov 2016 20:41:30 +0000 (15:41 -0500)]
ruby: Fix potential bugs in garnet2.0
1. Delete unused variable from struct LinkEntry
2. Correct GarnetExtLink and GarnetIntLink inheritance
Tony Gutierrez [Mon, 21 Nov 2016 20:40:03 +0000 (15:40 -0500)]
gpu-compute: fix segfault when constructing GPUExecContext
the GPUExecContext context currently stores a reference to its parent WF's
GPUISA object, however there are some special instructions that do not have
an associated WF. when these objects are constructed they set their WF pointer
to null, which causes the GPUExecContext to segfault when trying to
dereference
the WF pointer to get at the WF's GPUISA object. here we change the GPUISA
reference in the GPUExecContext class to a pointer so that it may be set to
null.
Tony Gutierrez [Mon, 21 Nov 2016 20:38:30 +0000 (15:38 -0500)]
gpu-compute: init valid field of GpuTlbEntry in default ctor
valid field for GpuTlbEntry is not set in the default ctor, which can
lead to strange behavior, and is also flagged by UBSAN.
Tony Gutierrez [Mon, 21 Nov 2016 20:37:07 +0000 (15:37 -0500)]
ruby: add default ctor for MachineID type
not all uses of MachineID initialize its fields, so here we add a default
ctor.
Tony Gutierrez [Mon, 21 Nov 2016 20:35:56 +0000 (15:35 -0500)]
x86: fix issue with casting in Cvtf2i
UBSAN flags this operation because it detects that arg is being cast directly
to an unsigned type, argBits. this patch fixes this by first casting the
value to a signed int type, then reintrepreting the raw bits of the signed
int into argBits.
Sooraj Puthoor [Sat, 19 Nov 2016 17:39:04 +0000 (12:39 -0500)]
ruby: init MessageSizeType of SequencerMsg to Request_Control
SequencerMsg is autogenerated by slicc scripts and the MessageSizeType is
initialized to the max enume value by default. The DMASequencer pushes this
message to the mandatory queue and since the MessageSizeType is unitialized,
string_to_MessageSizeType() function used by traces to print the message fails
with a panic. This patch avoids this problem by initializing MessageSizeType
of SequencerMsg to Request_Control.
Tony Gutierrez [Sat, 19 Nov 2016 17:35:14 +0000 (12:35 -0500)]
x86: fix loading/storing of Float80 types
Andreas Sandberg [Fri, 18 Nov 2016 18:08:20 +0000 (18:08 +0000)]
ext: Update fputils to rev
13589cd
This patch updates fputils to the latest revision (
13589cd) from the
upstream repository (github.com/andysan/fputils).
Andreas Hansson [Thu, 17 Nov 2016 09:54:18 +0000 (04:54 -0500)]
stats, alpha: Update ALPHA stats
Reflect the removal of the syscall tracking.
Andreas Hansson [Thu, 17 Nov 2016 09:54:16 +0000 (04:54 -0500)]
tests, ruby: Move rubytests from ALPHA (linux) to NULL (none)
This patch avoids compiling ALPHA six times as part of running
'util/regress', and instead relis on NULL with different protocols to
run the rubytest. All we need is the memory system, so there is really
no need to compile the ISA over and over again.
The one downside is the removal of running 'hello' for the variuos
ALPHA and protocol combinations, but if this is a concern we should
rather beef up the synthetic tests for the variuos protocols.
--HG--
rename : build_opts/NULL => build_opts/NULL_MESI_Two_Level
rename : build_opts/NULL => build_opts/NULL_MOESI_CMP_directory
rename : build_opts/NULL => build_opts/NULL_MOESI_CMP_token
rename : build_opts/NULL => build_opts/NULL_MOESI_hammer
rename : tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_Two_Level/config.ini => tests/quick/se/60.rubytest/ref/null/none/rubytest-ruby-MESI_Two_Level/config.ini
rename : tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_Two_Level/simerr => tests/quick/se/60.rubytest/ref/null/none/rubytest-ruby-MESI_Two_Level/simerr
rename : tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_Two_Level/simout => tests/quick/se/60.rubytest/ref/null/none/rubytest-ruby-MESI_Two_Level/simout
rename : tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_Two_Level/stats.txt => tests/quick/se/60.rubytest/ref/null/none/rubytest-ruby-MESI_Two_Level/stats.txt
rename : tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/config.ini => tests/quick/se/60.rubytest/ref/null/none/rubytest-ruby-MOESI_CMP_directory/config.ini
rename : tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/simerr => tests/quick/se/60.rubytest/ref/null/none/rubytest-ruby-MOESI_CMP_directory/simerr
rename : tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/simout => tests/quick/se/60.rubytest/ref/null/none/rubytest-ruby-MOESI_CMP_directory/simout
rename : tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/stats.txt => tests/quick/se/60.rubytest/ref/null/none/rubytest-ruby-MOESI_CMP_directory/stats.txt
rename : tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/config.ini => tests/quick/se/60.rubytest/ref/null/none/rubytest-ruby-MOESI_CMP_token/config.ini
rename : tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/simerr => tests/quick/se/60.rubytest/ref/null/none/rubytest-ruby-MOESI_CMP_token/simerr
rename : tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/simout => tests/quick/se/60.rubytest/ref/null/none/rubytest-ruby-MOESI_CMP_token/simout
rename : tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/stats.txt => tests/quick/se/60.rubytest/ref/null/none/rubytest-ruby-MOESI_CMP_token/stats.txt
rename : tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/config.ini => tests/quick/se/60.rubytest/ref/null/none/rubytest-ruby-MOESI_hammer/config.ini
rename : tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/simerr => tests/quick/se/60.rubytest/ref/null/none/rubytest-ruby-MOESI_hammer/simerr
rename : tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/simout => tests/quick/se/60.rubytest/ref/null/none/rubytest-ruby-MOESI_hammer/simout
rename : tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/stats.txt => tests/quick/se/60.rubytest/ref/null/none/rubytest-ruby-MOESI_hammer/stats.txt
rename : tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby/config.ini => tests/quick/se/60.rubytest/ref/null/none/rubytest-ruby/config.ini
rename : tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby/simerr => tests/quick/se/60.rubytest/ref/null/none/rubytest-ruby/simerr
rename : tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby/simout => tests/quick/se/60.rubytest/ref/null/none/rubytest-ruby/simout
rename : tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby/stats.txt => tests/quick/se/60.rubytest/ref/null/none/rubytest-ruby/stats.txt
Andreas Hansson [Thu, 17 Nov 2016 09:54:14 +0000 (04:54 -0500)]
alpha: Remove ALPHA tru64 support and associated tests
No one appears to be using it, and it is causing build issues
and increases the development and maintenance effort.
Tony Gutierrez [Thu, 27 Oct 2016 02:48:45 +0000 (22:48 -0400)]
hsail,gpu-compute: fixes to appease clang++
fixes to appease clang++. tested on:
Ubuntu clang version 3.5.0-4ubuntu2~trusty2
(tags/RELEASE_350/final) (based on LLVM 3.5.0)
Ubuntu clang version 3.6.0-2ubuntu1~trusty1
(tags/RELEASE_360/final) (based on LLVM 3.6.0)
the fixes address the following five issues:
1) the exec continuations in gpu_static_inst.hh were marked
as protected when they should be public. here we mark
them as public
2) the Abs instruction uses std::abs() in its execute method.
because Abs is templated, it can also operate on U32 and U64,
types, which cause Abs::execute() to pass uint32_t and uint64_t
types to std::abs() respectively. this triggers a warning
because std::abs() has no effect in this case. to rememdy this
we add template specialization for the execute() method of Abs
when its template paramter is U32 or U64.
3) Some potocols that utilize the code in cprintf.hh were missing
includes to BoolVec.hh, which defines operator<< for the BoolVec
type. This would cause issues when the generated code would try
to pass a BoolVec type to a method in cprintf.hh that used
operator<< on an instance of a BoolVec.
4) Surprise, clang doesn't like it when you clobber all the bits
in a newly allocated object. I.e., this code:
tlb = new GpuTlbEntry\[size\];
std::memset(tlb, 0, sizeof(GpuTlbEntry) \* size);
Let's use std::vector to track the TLB entries in the GpuTlb now...
5) There were a few variables used only in DPRINTFs, so we mark them
with M5_VAR_USED.
Michael LeBeane [Thu, 27 Oct 2016 02:48:40 +0000 (22:48 -0400)]
dev: Add m5 op to toggle synchronization for dist-gem5.
This patch adds the ability for an application to request dist-gem5 to begin/
end synchronization using an m5 op. When toggling on sync, all nodes agree
on the next sync point based on the maximum of all nodes' ticks. CPUs are
suspended until the sync point to avoid sending network messages until sync has
been enabled. Toggling off sync acts like a global execution barrier, where
all CPUs are disabled until every node reaches the toggle off point. This
avoids tricky situations such as one node hitting a toggle off followed by a
toggle on before the other nodes hit the first toggle off.
Michael LeBeane [Thu, 27 Oct 2016 02:48:37 +0000 (22:48 -0400)]
ruby: Allow multiple outstanding DMA requests
DMA sequencers and protocols can currently only issue one DMA access at
a time. This patch implements the necessary functionality to support
multiple outstanding DMA requests in Ruby.
mlebeane [Thu, 27 Oct 2016 02:48:33 +0000 (22:48 -0400)]
dev: Add 'simLength' parameter in EthPacketData
Currently, all the network devices create a 16K buffer for the 'data' field
in EthPacketData, and use 'length' to keep track of the size of the packet
in the buffer. This patch introduces the 'simLength' parameter to
EthPacketData, which is used to hold the effective length of the packet used
for all timing calulations in the simulator. Serialization is performed using
only the useful data in the packet ('length') and not necessarily the entire
original buffer.
Tony Gutierrez [Thu, 27 Oct 2016 02:48:28 +0000 (22:48 -0400)]
gpu-compute: support in-order data delivery in GM pipe
this patch adds an ordered response buffer to the GM pipeline
to ensure in-order data delivery. the buffer is implemented as
a stl ordered map, which sorts the request in program order by
using their sequence ID. when requests return to the GM pipeline
they are marked as done. only the oldest request may be serviced
from the ordered buffer, and only if is marked as done.
the FIFO response buffers are kept and used in OoO delivery mode
Tony Gutierrez [Thu, 27 Oct 2016 02:47:49 +0000 (22:47 -0400)]
gpu-compute, hsail: pass GPUDynInstPtr to getRegisterIndex()
for HSAIL an operand's indices into the register files may be calculated
trivially, because the operands are always read from a register file, or are
an immediate.
for machine ISA, however, an op selector may specify special registers, or
may specify special SGPRs with an alias op selector value. the location of
some of the special registers values are dependent on the size of the RF
in some cases. here we add a way for the underlying getRegisterIndex()
method to know about the size of the RFs, so that it may find the relative
positions of the special register values.
Tony Gutierrez [Thu, 27 Oct 2016 02:47:47 +0000 (22:47 -0400)]
gpu-compute: use System cache line size in the GPU
Tony Gutierrez [Thu, 27 Oct 2016 02:47:43 +0000 (22:47 -0400)]
gpu-compute, hsail: make the PC a byte address, not an instruction index
currently the PC is incremented on an instruction granularity, and not as an
instruction's byte address. machine ISA instructions assume the PC is a byte
address, and is incremented accordingly. here we make the GPU model, and the
HSAIL instructions treat the PC as a byte address as well.
Tony Gutierrez [Thu, 27 Oct 2016 02:47:38 +0000 (22:47 -0400)]
gpu-compute: add gpu_isa.hh to switch hdrs, add GPUISA to WF
the GPUISA class is meant to encapsulate any ISA-specific behavior - special
register accesses, isa-specific WF/kernel state, etc. - in a generic enough
way so that it may be used in ISA-agnostic code.
gpu-compute: use the GPUISA object to advance the PC
the GPU model treats the PC as a pointer to individual instruction objects -
which are store in a contiguous array - and not a byte address to be fetched
from the real memory system. this is ok for HSAIL because all instructions
are considered by the model to be the same size.
in machine ISA, however, instructions may be 32b or 64b, and branches are
calculated by advancing the PC by the number of words (4 byte chunks) it
needs to advance in the real instruction stream. because of this there is
a mismatch between the PC we use to index into the instruction array, and
the actual byte address PC the ISA expects. here we move the PC advance
calculation to the ISA so that differences in the instrucion sizes may be
accounted for in generic way.
Tony Gutierrez [Thu, 27 Oct 2016 02:47:30 +0000 (22:47 -0400)]
gpu-compute: add instruction mix stats for the gpu
Tony Gutierrez [Thu, 27 Oct 2016 02:47:27 +0000 (22:47 -0400)]
gpu-compute, hsail: call discardFetch() from the WF
because every taken branch causes fetch to be discarded, we move the call
to the WF to avoid to have to call it from each and every branch instruction
type.
Tony Gutierrez [Thu, 27 Oct 2016 02:47:19 +0000 (22:47 -0400)]
hsail, gpu-compute: remove doGm/SmReturn add completeAcc
we are removing doGmReturn from the GM pipe, and adding completeAcc()
implementations for the HSAIL mem ops. the behavior in doGmReturn is
dependent on HSAIL and HSAIL mem ops, however the completion phase
of memory ops in machine ISA can be very different, even amongst individual
machine ISA mem ops. so we remove this functionality from the pipeline and
allow it to be implemented by the individual instructions.
Tony Gutierrez [Thu, 27 Oct 2016 02:47:11 +0000 (22:47 -0400)]
gpu-compute: remove inst enums and use bit flag for attributes
this patch removes the GPUStaticInst enums that were defined in GPU.py.
instead, a simple set of attribute flags that can be set in the base
instruction class are used. this will help unify the attributes of HSAIL
and machine ISA instructions within the model itself.
because the static instrution now carries the attributes, a GPUDynInst
must carry a pointer to a valid GPUStaticInst so a new static kernel launch
instruction is added, which carries the attributes needed to perform a
the kernel launch.
Tony Gutierrez [Thu, 27 Oct 2016 02:47:05 +0000 (22:47 -0400)]
gpu-compute: move disassemle() implementation to GPUStaticInst
Tony Gutierrez [Thu, 27 Oct 2016 02:47:01 +0000 (22:47 -0400)]
gpu-compute, arch: add some methods to the base inst classes for ISA support
Tony Gutierrez [Thu, 27 Oct 2016 02:46:58 +0000 (22:46 -0400)]
ruby: make a RequestDesc class instead of std::pair
the RequestDesc was previously implemented as a std::pair, which made
the implementation overly complex and error prone. here we encapsulate the
packet, primary, and secondary types all in a single data structure with
all members properly intialized in a ctor
Andreas Hansson [Wed, 26 Oct 2016 18:50:54 +0000 (14:50 -0400)]
config: Break out base options for usage with NULL ISA
This patch breaks out the most basic configuration options into a set
of base options, to allow them to be used also by scripts that do not
involve any ISA, and thus no actual CPUs or devices.
The patch also fixes a few modules so that they can be imported in a
NULL build, and avoid dragging in FSConfig every time Options is
imported.
Andreas Hansson [Wed, 19 Oct 2016 10:20:04 +0000 (06:20 -0400)]
stats: Update stats to reflect recent changes to floats
Mostly just splitting out the floats ops and corresponding
reads/writes.
Shawn Rosti [Sat, 15 Oct 2016 20:11:07 +0000 (15:11 -0500)]
arm: Fix for ARM's Streamline conversion script
tracked down issue with ARM's version of gem5 using the "cluster" name.
The public/github version of ARM Gem5 does not use the "cluster" naming
mechanism.
Signed-off-by: Dam Sunwoo <dam.sunwoo@arm.com>
Signed-off-by: Jason Lowe-Power <jason@lowepower.com>
Bjoern A. Zeeb [Sat, 15 Oct 2016 20:11:04 +0000 (15:11 -0500)]
arm, dev: pl011 console interactivity
Improve PL011 console interactivity
Signed-off-by: Jason Lowe-Power <jason@lowepower.com>
Nicolas Derumigny [Sat, 15 Oct 2016 20:06:24 +0000 (15:06 -0500)]
syscall: read() should not write anything if reading EOF.
Read() should not write anything when returning 0 (EOF).
This patch does not correct the same bug occuring for :
nbr_read=read(file, buf, nbytes)
When nbr_read<nbytes, nbytes bytes are copied into the virtual
RAM instead of nbr_read. If buf is smaller than nbytes, a
page fault occurs, even if buf is in fact bigger than nbr_read.
Signed-off-by: Jason Lowe-Power <jason@lowepower.com>
Fernando Endo [Sat, 15 Oct 2016 19:58:45 +0000 (14:58 -0500)]
cpu, arm: Distinguish Float* and SimdFloat*, create FloatMem* opClass
Modify the opClass assigned to AArch64 FP instructions from SimdFloat* to
Float*. Also create the FloatMemRead and FloatMemWrite opClasses, which
distinguishes writes to the INT and FP register banks.
Change the latency of (Simd)FloatMultAcc to 5, based on the Cortex-A72,
where the "latency" of FMADD is 3 if the next instruction is a FMADD and
has only the augend to destination dependency, otherwise it's 7 cycles.
Signed-off-by: Jason Lowe-Power <jason@lowepower.com>
Andreas Hansson [Fri, 14 Oct 2016 14:37:38 +0000 (10:37 -0400)]
config: Make configs/common a Python package
Continue along the same line as the recent patch that made the
Ruby-related config scripts Python packages and make also the
configs/common directory a package.
All affected config scripts are updated (hopefully).
Note that this change makes it apparent that the current organisation
and naming of the config directory and its subdirectories is rather
chaotic. We mix scripts that are directly invoked with scripts that
merely contain convenience functions. While it is not addressed in
this patch we should follow up with a re-organisation of the
config structure, and renaming of some of the packages.
Jason Lowe-Power [Fri, 14 Oct 2016 14:02:03 +0000 (09:02 -0500)]
stats: Add more information to uninitialized error
ClockedObject was changed to require its regStats() to be called from every
child class. If you forget to do this, the error was indecipherable. This
patch makes the error more clear.
Curtis Dunham [Thu, 13 Oct 2016 22:21:40 +0000 (23:21 +0100)]
stats: update references
Omar Naji [Thu, 13 Oct 2016 18:22:11 +0000 (19:22 +0100)]
mem: add DRAM powerdown current
Change-Id: I763cffe0c69f5ebbbf6a6eb12bec5c13d5d0161d
Reviewed-by: Andreas Hansson <andreas.hansson@arm.com>
Reviewed-by: Radhika Jagtap <radhika.jagtap@arm.com>
Wendy Elsasser [Thu, 13 Oct 2016 18:22:11 +0000 (19:22 +0100)]
mem: Add DRAM low-power functionality
Added power-down state transitions to the DRAM controller model.
Added per rank parameter, outstandingEvents, which tracks the number
of outstanding command events and is used to determine when the
controller should transition to a low power state.
The controller will only transition when there are no outstanding events
scheduled and the number of command entries for the given rank is 0.
The outstandingEvents parameter is incremented for every RD/WR burst,
PRE, and REF event scheduled. ACT is implicitly covered by RD/WR
since burst will always issue and complete after a required ACT.
The parameter is decremented when the event is serviced (completed).
The controller will automatically transition to ACT power down,
PRE power down, or SREF.
Transition to ACT power down state scheduled from:
1) The RespondEvent, where read data is received from the memory.
ACT power-down entry will be scheduled when one or more banks is
open, all commands for the rank have completed (no more commands
scheduled), and there are no commands in queue for the rank
Transition to PRE power down scheduled from:
1) respondEvent, when all banks are closed, all commands have
completed, and there are no commands in queue for the rank
2) prechargeEvent when all banks are closed, all commands have
completed, and there are no commands in queue for the rank
3) refreshEvent, after the refresh is complete when the previous
state was ACT power-down
4) refreshEvent, after the refresh is complete when the previous
state was PRE power-down and there are commands in the queue.
Transition to SREF will be scheduled from:
1) refreshEvent, after the refresh is completes when the previous
state was PRE power-down with no commands in queue
Power-down exit commands are scheduled from:
1) The refreshEvent, prior to issuing a refresh
2) doDRAMAccess, to wake-up the rank for RD/WR command issue.
Self-refresh exit commands are scheduled from:
1) The next request event, when the queue has commands for the rank
in the readQueue or there are commands for the rank in the
writeQueue and the bus state is WRITE.
Change-Id: I6103f660776e36c686655e71d92ec7b5b752050a
Reviewed-by: Radhika Jagtap <radhika.jagtap@arm.com>
Wendy Elsasser [Thu, 13 Oct 2016 18:22:11 +0000 (19:22 +0100)]
mem: Add callback to compute stats prior to dump event
The per rank statistics are periodically updated based on
state transition and refresh events.
Add a method to update these when a dump event occurs to
ensure they reflect accurate values.
Specifically, need to ensure that the low-power state
durations, power, and energy are logged correctly.
Change-Id: Ib642a6668340de8f494a608bb34982e58ba7f1eb
Reviewed-by: Radhika Jagtap <radhika.jagtap@arm.com>
Wendy Elsasser [Thu, 13 Oct 2016 18:22:11 +0000 (19:22 +0100)]
mem: Modify drain to ensure banks and power are idled
Add constraint that all ranks have to be in PWR_IDLE
before signaling drain complete
This will ensure that the banks are all closed and the rank
has exited any low-power states.
On suspend, update the power stats to sync the DRAM power logic
The logic maintains the location of the signalDrainDone
method, which is still triggered from either:
1) Read response event
2) Next request event
This ensures that the drain will complete in the READ bus
state and minimizes the changes required.
Change-Id: If1476e631ea7d5999fe50a0c9379c5967a90e3d1
Reviewed-by: Radhika Jagtap <radhika.jagtap@arm.com>
Wendy Elsasser [Thu, 13 Oct 2016 18:22:10 +0000 (19:22 +0100)]
mem: Sort memory commands and update DRAMPower
Add local variable to stores commands to be issued.
These commands are in order within a single bank but will be out
of order across banks & ranks.
A new procedure, flushCmdList, sorts commands across banks / ranks,
and flushes the sorted list, up to curTick() to DRAMPower.
This is currently called in refresh, once all previous commands are
guaranteed to have completed. Could be called in other events like
the powerEvent as well.
By only flushing commands up to curTick(), will not get out of sync
when flushed at a periodic stats dump (done in subsequent patch).
Change-Id: I4ac65a52407f64270db1e16a1fb04cfe7f638851
Reviewed-by: Radhika Jagtap <radhika.jagtap@arm.com>
Omar Naji [Thu, 13 Oct 2016 18:22:10 +0000 (19:22 +0100)]
mem: update DDR3 die revision
Change-Id: I8992ddc1664c3ed4b2d36d8a34e4ce8be113b9de
Reviewed-by: Radhika Jagtap <radhika.jagtap@arm.com>
Omar Naji [Thu, 13 Oct 2016 18:22:10 +0000 (19:22 +0100)]
mem: add DRAM powerdown timing
Omar Naji [Thu, 13 Oct 2016 18:22:10 +0000 (19:22 +0100)]
mem: make DDR4 x16
Mitch Hayenga [Thu, 13 Oct 2016 18:22:10 +0000 (19:22 +0100)]
isa,arm: Add missing AArch32 FP instructions
This commit adds missing non-predicated, scalar floating point
instructions. Specifically VRINT* floating point integer rounding
instructions and VSEL* floating point conditional selects.
Change-Id: I23cbd1389f151389ac8beb28a7d18d5f93d000e7
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Nathanael Premillieu <nathanael.premillieu@arm.com>
Andreas Hansson [Thu, 13 Oct 2016 07:17:19 +0000 (03:17 -0400)]
ruby: Fix regressions and make Ruby configs Python packages
This patch moves the addition of network options into the Ruby module
to avoid the regressions all having to add it explicitly. Doing this
exposes an issue in our current config system though, namely the fact
that addtoPath is relative to the Python script being executed. Since
both example and regression scripts use the Ruby module we would end
up with two different (relative) paths being added. Instead we take a
first step at turning the config modules into Python packages, simply
by adding a __init__.py in the configs/ruby, configs/topologies and
configs/network subdirectories.
As a result, we can now add the top-level configs directory to the
Python search path, and then use the package names in the various
modules. The example scripts are also updated, and the messy
path-deducing variations in the scripts are unified.
Tushar Krishna [Sat, 8 Oct 2016 03:56:48 +0000 (23:56 -0400)]
config: fix typo in cluster topology.
Andreas Sandberg [Fri, 7 Oct 2016 13:14:44 +0000 (14:14 +0100)]
dev, arm: Make GenericTimer param handling more robust
The generic timer needs a pointer to an ArmSystem to wire itself to the
system register handler. This was previously specified as an instance
of System that was later cast to ArmSystem. Make this more robust by
specifying it as an ArmSystem in the Python interface and add a check
to make sure that it is non-NULL.
Change-Id: I989455e666f4ea324df28124edbbadfd094b0d02
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Tushar Krishna [Fri, 7 Oct 2016 01:06:00 +0000 (21:06 -0400)]
ruby: Add M5_VAR_USED before variables used only inside assert in garnet2.0.
This removes errors when building gem5.fast
Tushar Krishna [Thu, 6 Oct 2016 18:35:22 +0000 (14:35 -0400)]
ruby: garnet2.0
Revamped version of garnet with more optimized single-cycle routers,
more configurability, and cleaner code.
Tushar Krishna [Thu, 6 Oct 2016 18:35:21 +0000 (14:35 -0400)]
ruby: remove the original garnet code.
Only garnet2.0 will be supported henceforth.
Tushar Krishna [Thu, 6 Oct 2016 18:35:20 +0000 (14:35 -0400)]
config: add port directions and per-router delay in topology.
This patch adds port direction names to the links during topology
creation, which can be used for better printed names for the links
or for users to code up their own adaptive routing algorithms.
It also adds support for every router to have an independent latency
value to support heterogeneous topologies with the subsequent
garnet2.0 patch.
Tushar Krishna [Thu, 6 Oct 2016 18:35:18 +0000 (14:35 -0400)]
config: make internal links in network topology unidirectional.
This patch makes the internal links within the network topology
unidirectional, thus allowing any deadlock-free routing algorithms to
be specified from the topology itself using weights.
This patch also renames Mesh.py and MeshDirCorners.py to
Mesh_XY.py and MeshDirCorners_XY.py (Mesh with XY routing).
It also adds a Mesh_westfirst.py and CrossbarGarnet.py topologies.
Tushar Krishna [Thu, 6 Oct 2016 18:35:17 +0000 (14:35 -0400)]
config: add a separate config file for the network.
This patch adds a new file configs/network/Network.py to setup the network,
instead of doing that within Ruby.py.
Tushar Krishna [Thu, 6 Oct 2016 18:35:16 +0000 (14:35 -0400)]
ruby: rename networktest to garnet_synthetic_traffic.
networktest is essentially a collection of synthetic traffic patterns
for the network. The protocol name and the tester having the same name
led to multiple python configuration files with the same name, adding
confusion. This patch renames networktest to garnet_synthetic_traffic,
and also adds more synthetic traffic patterns.
Tushar Krishna [Thu, 6 Oct 2016 18:35:14 +0000 (14:35 -0400)]
ruby: rename ALPHA_Network_test protocol to Garnet_standalone.
Over the past 6 years, we realized that the protocol is essentially used
to run the garnet network in a standalone manner, and feed standard synthetic
traffic patterns through it.
Alexandru Dutu [Tue, 4 Oct 2016 17:06:05 +0000 (13:06 -0400)]
kvm: Adding details to kvm page fault in x86
Adding details, e.g. rip, rsp etc. to the kvm pagefault exit when in SE mode.
Alexandru Dutu [Tue, 4 Oct 2016 17:04:19 +0000 (13:04 -0400)]
misc: Adds a warning in case gdb is attached multiple times
Instead of scheduling another event, this patch adds a warning in case gdb
is attached multiple times and the first attachement event has not been
processed yet.
Alexandru Dutu [Tue, 4 Oct 2016 17:03:52 +0000 (13:03 -0400)]
gpu-compute: Added method to compute the actual workgroup size
This patch adds a method to the Wavefront class to compute the actual workgroup
size. This can be different from the maximum workgroup size specified when
launching the kernel through the NDRange object. Current solution is still not
optimal, as we are computing these for each wavefront and the dispatcher also
needs to have this information and can't actually call
Wavefront::computeActuallWgSz before the wavefronts are being created. A long
term solution would be to have a Workgroup class that deals with all these
details.
Andreas Hansson [Tue, 4 Oct 2016 14:44:52 +0000 (15:44 +0100)]
config: Fix lat_mem_rd example script
Adjust the traffic generator time-out so that the script works out of
the box
Change-Id: I6b3b6b11f98b094ae3acdbe09488c26e4aeb0ab4
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Andreas Sandberg [Tue, 4 Oct 2016 10:22:16 +0000 (11:22 +0100)]
sim: Add a checkpoint function to test for entries
When loading a checkpoint, it's sometimes desirable to be able to test
whether an entry within a secion exists. This is currently done
automatically in the UNSERIALIZE_OPT_SCALAR macro, but it isn't
possible to do for arrays, containers, or enums. Instead of adding
even more macros, add a helper function (CheckpointIn::entryExists())
that tests for the presence of an entry.
Change-Id: I4b4646b03276b889fd3916efefff3bd552317dbc
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Brad Beckmann [Thu, 29 Sep 2016 05:06:52 +0000 (01:06 -0400)]
ruby: correct size for partial memory writes
Fixed AbstractController::queueMemoryWritePartial to specify the
correct size for partial memory writes.
Brad Beckmann [Thu, 29 Sep 2016 05:06:33 +0000 (01:06 -0400)]
mem: minor dprintf fix to abstract mem
print number of bytes written as a decimal number, not hex
Curtis Dunham [Thu, 22 Sep 2016 13:46:37 +0000 (14:46 +0100)]
arm: disable GIC extensions
Change-Id: If19b9c593b48ded1ea848f2d3710d4369ec8a221
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Andreas Sandberg [Thu, 22 Sep 2016 11:10:47 +0000 (12:10 +0100)]
tests, arm: Reinstate accidentally removed switcheroo tests
Two of the switcheroo tests were accidentally removed due to
unexpected Mercurial behavior.
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Rekai Gonzalez-Alberquilla [Thu, 22 Sep 2016 09:49:10 +0000 (10:49 +0100)]
cpu: Fix the O3 CPU Drain
The drain did not wait until stages were ready again. Therefore, as a
result of messages in the TimeBuffer being drain, the state after the
drain was not consistent and asserts fired in some places when the
draining happened after a stage got blocked, but before the notification
arrived to the previous stages.
Change-Id: Ib50b3b40b7f745b62c1eba2931dec76860824c71
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Andreas Sandberg [Thu, 22 Sep 2016 09:49:09 +0000 (10:49 +0100)]
test: Make the memtest and memcheck tests functional only
The memtest and memcheck are not designed to test timing. Make them
functional only to make ref diffs less noisy in the future.
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Andreas Sandberg [Thu, 22 Sep 2016 09:49:08 +0000 (10:49 +0100)]
tests: Make remaining switcheroo tests functional only
The switcheroo tests only really serve to check functional
correctness. Checking for stat differences in them just increases the
size of reference diffs.
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Curtis Dunham [Tue, 20 Sep 2016 14:51:24 +0000 (15:51 +0100)]
ext: update SST test config
Align configuration with new SST change [1] requiring units for
memHierarchy's backend.mem_size parameter.
[1] https://github.com/sstsimulator/sst-elements/commit/
c901abb4e79644ff18f5222c94f5dae012772e1e
Change-Id: I19fa09bec8aa453dc52d154598a4ebb20ea304d8
Tony Gutierrez [Fri, 16 Sep 2016 18:47:19 +0000 (14:47 -0400)]
gpu-compute: fix typo in GPUDispatcher
Alexandru Dutu [Fri, 16 Sep 2016 16:36:20 +0000 (12:36 -0400)]
hsail: Fix disassembly of load instruction with 3 destination operands
Alexandru Dutu [Fri, 16 Sep 2016 16:32:36 +0000 (12:32 -0400)]
gpu-compute: Adding context serialization methods to Wavefront
This patch adds methods to serialize the context of a particular wavefront
to the simulated system memory. Context serialization is used when a wavefront
is preempeted (i.e. context switch).
Alexandru Dutu [Fri, 16 Sep 2016 16:31:46 +0000 (12:31 -0400)]
gpu-compute: Refactoring Wavefront::dynWaveId
Alexandru Dutu [Fri, 16 Sep 2016 16:30:05 +0000 (12:30 -0400)]
gpu-compute: Adding vector register file debug messages
This patch introduces DPRINTFs for reading and writing to and from the vector
register file.
Alexandru Dutu [Fri, 16 Sep 2016 16:29:01 +0000 (12:29 -0400)]
gpu-compute: Changing reconvergenceStack type
std::stack has no iterators, therefore the reconvergence stack can't be
iterated without poping elements off. We will be using std::list instead to be
able to iterate for saving and restoring purposes.
Alexandru Dutu [Fri, 16 Sep 2016 16:27:56 +0000 (12:27 -0400)]
gpu-compute: Adding ioctl for HW context size
Adding runtime support for determining the memory required by a SIMD engine
when executing a particular wavefront.
Alexandru Dutu [Fri, 16 Sep 2016 16:26:52 +0000 (12:26 -0400)]
gpu-compute: Wavefront refactoring
Renaming members of the Wavefront class in accordance with the style guide.
Alexandru Dutu [Fri, 16 Sep 2016 16:26:03 +0000 (12:26 -0400)]
gpu-compute: Remove WFContext
WFContext struct is currently unused and it has been rendered not useful in
saving and restoring the context of a Wavefront. Wavefront class should be
sufficient for that purpose and the runtime can figure out the memory size
it will need to allocate for a Wavefront through an IOCTL.
Andreas Sandberg [Fri, 16 Sep 2016 08:14:31 +0000 (09:14 +0100)]
tests, arm: Make switcheroo and checkpoint tests functional
Switcheroo and checkpoint tests should generally be considered to be
successful if they run to completion. Remove all reference output
files from the switcheroo and checkopint tests to make them purely
functional.
Change-Id: I70b47853bd662b7a33716d9e0d2154b16077f9dc
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Curtis Dunham <curtis.dunham@arm.com>
Andreas Sandberg [Fri, 16 Sep 2016 08:04:20 +0000 (09:04 +0100)]
tests: Add support for functional only tests
Modify the ClassicTest class to only emit a stat verification test
unit if there is a reference stat file. This makes it possible to
design tests that don't care about stat changes.
To generate purely functional tests, we need to be able to create
empty test reference directories. This does not work well with many
revision control systems. As a workaround, add a file named EMPTY to
the list of ignored files in the test harness. This file can be used
as a placeholder in otherwise empty test directories.
Change-Id: I583c8c4e55479f0d48fa99d0b0d1eac9221e6652
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Curtis Dunham <curtis.dunham@arm.com>
Curtis Dunham [Thu, 15 Sep 2016 17:21:38 +0000 (18:21 +0100)]
base: eliminate ipython warning
Change-Id: I3e282baeb969b6bb9534813a2f433d68246c0669
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Ricardo Alves [Thu, 15 Sep 2016 17:21:24 +0000 (18:21 +0100)]
arm: Add m5_fail support for aarch64
Change-Id: Id2acbc09772be310a0eb9e33295afab07e08a4fa
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Radhika Jagtap [Thu, 15 Sep 2016 17:01:20 +0000 (18:01 +0100)]
cpu: Support exit when any one Trace CPU completes replay
This change adds a Trace CPU param to exit simulation early,
i.e. when the first (any one) trace execution is complete. With
this change the user gets a choice to configure exit as either
when the last CPU finishes (default) or first CPU finishes
replay. Configuring an early exit enables simulating and
measuring stats strictly when memory-system resources are being
stressed by all Trace CPUs.
Change-Id: I3998045fdcc5cd343e1ca92d18dd7f7ecdba8f1d
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Radhika Jagtap [Thu, 15 Sep 2016 17:01:16 +0000 (18:01 +0100)]
cpu: Adjust for trace offset and fix stats
This change subtracts the time offset present in the trace from
all the event times when nodes and request are sent so that the
replay starts immediately when the simulation starts. This makes
the stats accurate when the time offset in traces is large, for
example when traces are generated in the middle of a workload
execution. It also solves the problem of unnecessary DRAM
refresh events that would keep occuring during the large time
offset before even a single request is replayed into the system.
Change-Id: Ie0898842615def867ffd5c219948386d952af7f7
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Radhika Jagtap [Thu, 15 Sep 2016 17:01:09 +0000 (18:01 +0100)]
cpu: Add frequency scaling to the Trace CPU
This change adds a simple feature to scale the frequency of
the Trace CPU.
The compute delays in the input traces provide timing. This
change adds a freqency multiplier parameter to the Trace CPU
set to 1.0 by default. The compute delay is manipulated to
effectively achieve the frequency at which the nodes become
ready and thus scale the frequency of the Trace CPU.
Change-Id: Iaabbd57806941ad56094fcddbeb38fcee1172431
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Gabor Dozsa [Thu, 15 Sep 2016 17:00:59 +0000 (18:00 +0100)]
arm, config: Fixups for the example big.LITTLE(tm) configuration
This patch refactors the configuration file to use a more
object-oriented design.
Change-Id: I44ac2d063c2b5901f385544fb6ce3f259459cb05
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Gabor Dozsa <gabor.dozsa@arm.com>
Michael LeBeane [Wed, 14 Sep 2016 03:20:03 +0000 (23:20 -0400)]
kvm: Support timing accesses for KVM cpu
This patch enables timing accesses for KVM cpu. A new state,
RunningMMIOPending, is added to indicate that there are outstanding timing
requests generated by KVM in the system. KVM's tick() is disabled and the
simulation does not enter into KVM until all outstanding timing requests have
completed. The main motivation for this is to allow KVM CPU to perform MMIO
in Ruby, since Ruby does not support atomic accesses.
Michael LeBeane [Wed, 14 Sep 2016 03:18:34 +0000 (23:18 -0400)]
x86: Force strict ordering for memory mapped m5ops
Normal MMAPPED_IPR requests are allowed to execute speculatively under the
assumption that they have no side effects. The special case of m5ops that are
treated like MMAPPED_IPR should not be allowed to execute speculatively, since
they can have side-effects. Adding the STRICT_ORDER flag to these requests
blocks execution until the associated instruction hits the ROB head.
Michael LeBeane [Wed, 14 Sep 2016 03:17:42 +0000 (23:17 -0400)]
sim: Refactor quiesce and remove FS asserts
The quiesce family of magic ops can be simplified by the inclusion of
quiesceTick() and quiesce() functions on ThreadContext. This patch also
gets rid of the FS guards, since suspending a CPU is also a valid
operation for SE mode.
Michael LeBeane [Wed, 14 Sep 2016 03:16:06 +0000 (23:16 -0400)]
config: move dist-gem5 options to common config
dist-gem5 should not be restricted to FullSystem mode.
Michael LeBeane [Wed, 14 Sep 2016 03:14:24 +0000 (23:14 -0400)]
dev: Add a DmaCallback class to DmaDevice
This patch introduces the DmaCallback helper class, which registers a callback
to fire after a sequence of (potentially non-contiguous) DMA transfers on a
DmaPort completes.
Michael LeBeane [Wed, 14 Sep 2016 03:12:46 +0000 (23:12 -0400)]
sim, syscall_emul: Add mmap to EmulatedDriver
Add support for calling mmap on an EmulatedDriver file descriptor.
Michael LeBeane [Wed, 14 Sep 2016 03:11:20 +0000 (23:11 -0400)]
gpu-compute: Fix bug with return in cfg
Connecting basic blocks would stop too early in kernels where ret was not the
last instruction. This patch allows basic blocks after the ret instruction
to be properly connected.
Michael LeBeane [Wed, 14 Sep 2016 03:08:34 +0000 (23:08 -0400)]
dev: Exit correctly in dist-gem5
The receiver thread in dist_iface is allowed to directly exit the simulation.
This can cause exit to be called twice if the main thread simultaneously wants
to exit the simulation. Therefore, have the receiver thread enqueue a request
to exit on the primary event queue for the main simulation thread to handle.
Michael LeBeane [Wed, 14 Sep 2016 03:06:32 +0000 (23:06 -0400)]
misc: Remove FullSystem check for networking components
Ethernet devices are currently only hooked up if running in FS mode. Much of
the Ethernet networking code is generic and can be used to build non-Ethernet
device models. Some of these device models do not require a complex driver
stack and can be built to use an EmulatedDriver in SE mode. This patch enables
etherent interfaces to properly connect regardless of whether the simulation
is in FS or SE mode.
Matt Poremba [Wed, 14 Sep 2016 03:06:18 +0000 (23:06 -0400)]
base: Output all AddrRange parameters to config.ini
Currently only 'start' and 'end' of AddrRange are printed in config.ini.
This causes address ranges to be overlapping when loading a c++-only
config with interleaved addresses using CxxConfigManger. This patch adds
prints for the interleave and XOR bits to config.ini such that address
ranges are properly setup with cxx config.
Andreas Sandberg [Tue, 6 Sep 2016 09:22:38 +0000 (10:22 +0100)]
dev, arm: Add a customizable NoMali GPU model
Add a customizable NoMali GPU model and an example Mali T760
configuration. Unlike the normal NoMali model (NoMaliGpu), the
NoMaliCustopmGpu model exposes all the important GPU ID registers to
Python. This makes it possible to implement custom GPU configurations
by without changing the underlying NoMali library.
Change-Id: I4fdba05844c3589893aa1a4c11dc376ec33d4e9e
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Andreas Hansson <andreas.hansson@arm.com>
Curtis Dunham [Fri, 2 Sep 2016 13:58:15 +0000 (14:58 +0100)]
ext: eliminate warnings in SST connector
Now compiles completely clean.
Curtis Dunham [Wed, 24 Aug 2016 13:20:53 +0000 (14:20 +0100)]
commit
15c633eea52f21dae8cb3a195823b3cdec7be491
Author: Curtis Dunham <Curtis.Dunham@arm.com>
ext: update SST connector for SST 6.0
David Hashe [Mon, 22 Aug 2016 15:43:44 +0000 (11:43 -0400)]
config: KVM acceleration for apu_se.py
Add support for using KVM to accelerate APU simulations. The intended use
case is to fast-forward through runtime initialization until the first
kernel launch.