cpu: Make the NonCachingSimpleCPU use a back door for fetch.

If the memory system can provide a back door to memory, store that, and
use it for subsequent accesses to the range it covers. For now, this
covers only fetch. That's because fetch will generally happen more than
loads and stores, and because it's relatively simple to implement since
we can ignore atomic operations, etc.

Some limitted benchmarking suggests that this speeds up x86 linux boot
by about 20%, although my modifications to the config to remove caching
(which blocks the back door mechanism) also made gem5 crash, so it's
hard to say for sure if that's a valid result. The crash happened in the
same way before and after, so it's probably at least relatively
representative.

While this gives a pretty substantial performance boost, it will prevent
statistics from being collected at the memory, or on intermediate objects
in the interconnect like the bus. That is to be expected with this
memory mode, however.

Change-Id: I73f73017e454300fd4d61f58462eb4ec719b8d85
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/36979
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

util: Update python version for GCN3

The Python version installed in the Dockerfile for GCN3 by apt-get is
too old to build gem5. This bumps the version to the most recent Python
to avoid needing to update this file too much.

Python 3.9 is install via PPA since it is not available in the official
Ubuntu 16.04 repository. Likewise, pip is installed from "source" as it
is not available for Python 3.9 in from neither the PPA nor Ubuntu.

Change-Id: Ia919f31cf9c9063e1df091cea15590526715739b
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/37219
Reviewed-by: Matt Sinclair <mattdsinclair@gmail.com>
Reviewed-by: Daniel Gerzhoy <daniel.gerzhoy@gmail.com>
Maintainer: Matt Sinclair <mattdsinclair@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

base: Fix `AddrRange::addIntlvBits(Addr)` and new test.

The methods `AddrRange::removeIntlvBits(Addr)` and
`AddrRange::addIntlvBits(Addr)` should be the inverse of one another,
but the latter did not insert the blanks for filling the removed bits in
the correct positions.  Since the masks are ordered increasingly by the
position of the least significant bit of each mask, the lowest bit that
has to be inserted at each iteration is always `intlv_bit`, not needing
to be shifted to the left or right.  The bits that need to be copied
from the input address are `intlv_bit-1..0` at each iteration.

The test `AddrRangeTest.AddRemoveInterleavBitsAcrossRange` has been
updated have masks below bit 12, making the old code not pass the test.
A new `AddrRangeTest.AddRemoveInterleavBitsAcrossContiguousRange` test
has been added to include a case in which the previous code fails.  The
corrected code passes both tests.

This function is not used anywhere other than the tests and the class
`ChannelAddr`.  However, it is needed to efficiently implement
interleaved caches in the classic mode.

Change-Id: I7d626a1f6ecf09a230fc18810d2dad2104d1a865
Signed-off-by: Isaac Sánchez Barrera <isaac.sanchez@bsc.es>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/37175
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>

tests: Add realview64-kvm.py test to quick regressions

By using the valid_host parameter we can make sure the test is
run on a aarch64 host only

Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Change-Id: I3cdb35967e85377f26adf73ad147cb2479162ca1
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/31219
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>

tests: Add realview64-kvm.py testing platform

Change-Id: If9952563413b4c7462a3ddf46c40358023d5bc60
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/31218
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

tests: Update guest binaries used by regressions

The new tarball (aarch-system-20200611.tar.bz2) contains the
m5_exit_addr.squashfs.arm64 disk image to be used by KVM regressions

This disk image is based on a memory mapped m5 exit

Change-Id: I23c4a2fa8f969c98dd319cbfa51bca0bcbc9e890
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/37177
Reviewed-by: Ciro Santilli <ciro.santilli@arm.com>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>

arch-x86, kvm: clean up x86 long regresion kvm code

This commit cleans up the code for x86 kvm long regressions.
Somehow the old version went is as the last patchset.
This is the intended code, which should match the last comments.

Change-Id: I9af02a51ce8ed5098887fb0a6b9240db95227bc3
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/37120
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

arch-x86: include system syscall header in syscall table files

The getdents syscall is only implemented on hosts that define
SYS_getdents, which is located in <sys/syscall.h>.

That header was missed when splitting the syscall tables into their own
files; this patch adds the header to the syscall table files.

Change-Id: I28d54f6ea2874aa533c89ed7520561e19fe5e5f9
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/37195
Reviewed-by: Matt Sinclair <mattdsinclair@gmail.com>
Reviewed-by: Matthew Poremba <matthew.poremba@amd.com>
Maintainer: Matt Sinclair <mattdsinclair@gmail.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

util: Specify version of rocm-cmake in gcn3 Dockerfile

This patch updates the gcn3 Dockerfile to use the version of rocm-cmake
that MIOpen specifies in its dev-requirements.txt. This fixes a build
conflict with newer versions of rocm-cmake that require a higher version
of SCons than we have in the Dockerfile.

Change-Id: I70887fd91807b77e5015037830cfe96560ac8a31
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/37155
Maintainer: Gabe Black <gabe.black@gmail.com>
Maintainer: Matt Sinclair <mattdsinclair@gmail.com>
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Reviewed-by: Matt Sinclair <mattdsinclair@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

arch-x86, cpu-kvm: add x86 kvm test to long regression

revised patch based on reviews

Change-Id: I18d219080ff8ab1c42c9e1a12aadd89606802b25
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/34855
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: mike upton <michaelupton@gmail.com>

misc: Convert MAINTAINERS to YAML

Convert MAINTAINERS to YAML and rename it to MAINTAINERS.yaml.

Change-Id: I0965b89e7afceb53f6c2a6a183cc1514f5a9d7a0
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/37035
Reviewed-by: Hoa Nguyen <hoanguyen@ucdavis.edu>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

mem,sim: Get the page size from the page table in SE mode.

The page table already knows the size of a page without having to
directly use any ISA specific constants.

Change-Id: I68b575e194697065620a2097d972076886766f74
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/34172
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Maintainer: Gabe Black <gabe.black@gmail.com>

cpu: Style fixes in the AtomicSimpleCPU.

Change-Id: I42391e5a75c55022077f1ef78df97c54fa70f198
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/36976
Reviewed-by: Gabe Black <gabe.black@gmail.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

util: Updated compiler-test.sh for Python3

In our Ubuntu 18.04 Docker Images, we require gem5 to be build using
`/usr/bin/env python3 /usr/bin/scons ...`.

Change-Id: I4dd3bca1602247575769e6c250337c3ee4a40780
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/36884
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Hoa Nguyen <hoanguyen@ucdavis.edu>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>

util,misc: Altered cpt_upgrader.py shebang to Python3

This script is necessisary for compilation yet is dependent on Python2.
On a pure Python3 system, this results in a compilation failure.

This script works fine with Python3.

Change-Id: Ib1470a76d65455e727041686788c08f385e7251a
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/36715
Tested-by: kokoro <noreply+kokoro@google.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Hoa Nguyen <hoanguyen@ucdavis.edu>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>

mem,scons: Changed assert to panic_if in MessageBuffer

The variable 'm_allow_zero_latency' was only used in an assert message in
`src/mem/ruby/network/MessageBuffer.cc`. This assert is stripped when
compiling to gem5.fast, resulting in the compilation failing with an
unused variable error.

This assert is better as a panic_if, which will not be stripped out
during the .fast compilation.

Change-Id: I5de74982fa42b3291899ddcf73f7140079e1ec3f
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/36697
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>

mem: Added missing override to cache_blk function

This was causing a compilation warning/error when compiling with clang.

Change-Id: Ic6cf59c002656ba2ab05d8b58766613c289e7db0
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/36695
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

util: Updated the Dockerfiles for Python3

For the next release of gem5, we are dropping support for Python2. The
Ubuntu 18.04 Docker images were running with Python2. This has been
updated.

It should be noted that there is, at present, no eligant solution to the
issue that older versions of Scons (such as that obtainable via APT in
Ubuntu 18.04) use Python2. Those wishing to compile with these Docker
Images should use
`/usr/bin/env python3 $(which scons) build/X86/gem5.op5`

Change-Id: Ic36ecc7196688daff21af2bb3a76381966f38f60
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/36595
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>

mem: Expose the underlyig DRAM or NVM's memory back door.

Use the AbstractMem's new getBackdoor call to implement the
recvAtomicBackdoor call in the memory controller's port.

Change-Id: I10a7d22edb62afc3b77a2d462f297572c04f020d
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/36978
Maintainer: Gabe Black <gabe.black@gmail.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

mem: Minor refactor of how the abstract mem backdoor is exposed.

Previously the SimpleMem depended on the fact that it inherited from the
AbstractMem in order to access and export it's back door. Now, the
AbstractMem has a method which will set a back door pointer if
appropriate, which the SimpleMem can use, or anything else which uses an
AbstractMem as its backing store.

Also, make the AbstractMem invalidate any existing back doors and refuse
to give out any new ones while some bit of memory is locked. That's
because if the storage is accessed directly, the AbstractMem will have
no change to manage its bookkeeping, and locking won't work properly.

Change-Id: If8c2a63e0827bb88b583f27ab4151d6b761e116e
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/36977
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>

arch,cpu: Enforce using accessors to get at src/destRegIdx.

There were accessors for reading these indexes, but they were not
consistently used. This change makes them private to StaticInst, and
changes places that were accessing them directly to instead use the
accessors. New accessors are added for code generated by the ISA parser
and some ARM code to set the indexes without accessing them directly.

By forcing these values to be behind accessors, it will be much simpler
to change how those values are stored and retrieved.

Change-Id: Icca80023d7f89e29504fac6b194881f88aedeec2
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/36875
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

arch-gcn3: Fix operand size reporting for Flat insts

Some Flat instructions were reporting their operand sizes in bits
instead of bytes. This lead to panics occuring in
StaticRegisterManagerPolicy::mapVgpr.

This patch updates those insts to report their operand sizes in bytes.

Change-Id: I48f485e638864a1f2a1a3be66ed20893e73e9705
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/36275
Reviewed-by: Matt Sinclair <mattdsinclair@gmail.com>
Reviewed-by: Alexandru Duțu <alexandru.dutu@amd.com>
Maintainer: Matt Sinclair <mattdsinclair@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

misc: Update maintainers file

Change-Id: I19810801f0acd5a35dde59a70166339e00b97eca
Signed-off-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/36886
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-by: Srikant Bharadwaj <srikant.bharadwaj@amd.com>
Reviewed-by: Gabe Black <gabe.black@gmail.com>
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Reviewed-by: Boris Shingarov <shingarov@gmail.com>
Reviewed-by: Hoa Nguyen <hoanguyen@ucdavis.edu>
Reviewed-by: ZHENGRONG WANG <seanyukigeek@gmail.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Matthew Poremba <matthew.poremba@amd.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

misc: create C declarations for the _addr and _semi m5ops

Symbols such as m5_exit_addr are already present in the libm5.a, but were
not previously exposed in a header. This commit allows external C programs
to use those versions of the functions as well.

Change-Id: I925e3af7bd6cb23e06fb744d453153323afb9310
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/36896
Reviewed-by: Gabe Black <gabe.black@gmail.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

util: add update-copyright utility to update copyright on commits

The utility can automatically update copyright for the chosen
organization on all files touched in the selected range of git commits.

Change-Id: I4e1803e53f4530f88fb344f56e08ea29fbfcd41d
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/35535
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

configs,tests: Add tokens to GPU VIPER tester

This patch integrates tokens into the VIPER tester by adding a
GMTokenPort to the tester, having the tester acquire tokens for
requests that use tokens, and checking for available tokens
before issuing any requests.

Change-Id: Id317d703e4765dd5fa7de0d16f5eb595aab7096c
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/35135
Maintainer: Matthew Poremba <matthew.poremba@amd.com>
Maintainer: Matt Sinclair <mattdsinclair@gmail.com>
Reviewed-by: Matt Sinclair <mattdsinclair@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

configs,mem-ruby: Remove old GPU ptls

These protocols are no longer supported, either
because they are not representative of GPU
protocols, or because the have not been updated
to work with GCN3.

Change-Id: I989eeb6826c69225766aaab209302fe638b22719
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/34197
Reviewed-by: Matt Sinclair <mattdsinclair@gmail.com>
Maintainer: Matt Sinclair <mattdsinclair@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

gpu-compute,mem-ruby: Replace ACQUIRE and RELEASE request flags

This patch replaces ACQUIRE and RELEASE flags which are HSA-specific.
ACQUIRE flag becomes INV_L1 in VIPER protocol. RELEASE flag is removed.
Future protocols may support extra cache coherence flags like INV_L2 and
WB_L2.

Change-Id: I3d60c9d3625c898f4110a12d81742b6822728533
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/32859
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Matt Sinclair <mattdsinclair@gmail.com>
Maintainer: Matt Sinclair <mattdsinclair@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

tests,configs,mem-ruby: Adding Ruby tester for GPU_VIPER

This patch adds the GPU protocol tester that uses data-race-free
operation to discover bugs in GPU protocols including GPU_VIPER. For
more information please see the following paper and the README:

T. Ta, X. Zhang, A. Gutierrez and B. M. Beckmann, "Autonomous
Data-Race-Free GPU Testing," 2019 IEEE International Symposium on
Workload Characterization (IISWC), Orlando, FL, USA, 2019, pp. 81-92,
doi: 10.1109/IISWC47752.2019.9042019.

Change-Id: Ic9939d131a930d1e7014ed0290601140bdd1499f
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/32855
Reviewed-by: Matt Sinclair <mattdsinclair@gmail.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Matt Sinclair <mattdsinclair@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

arm: Get rid of some unused instruction templates.

These were defined but not used.

Change-Id: Ib81e86c8b8640e2f47ff7ad84d287367462e04a5
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/36975
Reviewed-by: Gabe Black <gabe.black@gmail.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

mips: Fix the build after the MMU changes.

Change-Id: I2bd1a6a8607fe1da056182ca840036db35b53c36
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/36995
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

configs: Add dtb-gen to fs_bigLITTLE.py

Change-Id: I1956e98d0fa507cc342e926b61d69fb967a64556
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/36955
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

arch-arm: Do not use _flushMva for TLBI IPA

This is just a cosmetic change

Change-Id: If9ea1114ed7e20d5c952f401935532cf3335c501
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/35246
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

arch-arm: TlbEntry flush to be considered as functional lookup

Otherwise we are unnecessarily shifting the TLB entry to the
MRU position before invalidating it

Change-Id: I43ee04cd5267829ab7357f4fe1ff745023adc598
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/35244
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

arch-arm: Fix implementation of TLBI_VMALL instructions

Same as 73dfc5f89b81e622a2330b1b52e055cafcc9178b: there's a difference
on how AArch64 and AArch32 treat stage2 invalidation.

Change-Id: I6fede4d9cb82e4bae9163326d38db9351d2a3880
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/35243
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

arch-arm: Add el2Enabled cached variable

Several TLB invalidation instructions rely on VMID matching.  This is
only applicable is EL2 is implemented and enabled in the current state.

The code prior to this patch was making the now invalid assumption that
we shouldn't consider the VMID if we are doing a secure lookup. This is
because in the past if we were in secure mode we were sure EL2 was not
enabled.
This is fishy and not valid anymore anyway after the introduction of
secure EL2.

Change-Id: I9a1368f8ed19279ed3c4b2da9fcdf0db799bc514
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/35242
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

cpu, fastmodel: Remove the old getDTBPtr/getITBPtr virtual methods

JIRA: https://gem5.atlassian.net/browse/GEM5-790

Change-Id: I6c6cdeaa3ae1433624e4e5b30b031d49e822f0e0
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/34984
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com>

configs: Do not require default options for caches

This change is useful when using custom simulation scripts that do not
rely on configs/common/Options.py.
Without this change, the custom script always needed to provide some
value for cache sizes and HW prefetchers configuration; with this change
it is possible to provide no value and use what is defined in the core
configuration as default.

Change-Id: Id0e807c3fa224180d682f366c7307941bab8ce59
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/36776
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

arch: Clean up the __init__s in (Sub)OperandList.

These had a lot of for loops and ifs and nesting. Python lets you avoid
that, which makes the code easier to read and more intuitive to
understand.

Change-Id: I576bf1de9e5b2268717a535ca42f2db669d83ed2
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/35818
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

dev: Convert the x86 i8237 DMA controller to use RegBank.

This gets rid of the requirement to only modify one byte register at a
time, and builds some structure around individual DMA channels.

The one small feature of the i8237 that was implemented is still
implemented, but now with a method of the i8237.

Change-Id: Ibc2b2d75f2a3b860da3f28ae649c6f1a099bdf7d
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/36815
Reviewed-by: Matthew Poremba <matthew.poremba@amd.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

util: Add a unit test for the "addr" call type in the m5 util.

This verifies that the slightly more complex --addr command line option
behaves as expected.

Also, like the inst and semi call type unit tests, it will either
attempt to successfully perform a call to the "sum" m5 op if it's told
it's running under gem5, or it will attempt to catch itself failing to
run that command by using mprotect to block its access to the mmap-ed
region and then looks at the siginfo_t to make sure the attempted access
was to the right place, etc.

It also will attempt to verify the details of the mmap if possible by
looking up information about its own mmap-ings in /proc. If the file it
would expect to find the mappings in doesn't exist, it prints a warning
and gives up. If it does, it looks through it to find the line
corresponding to the m5 ops, and then checks some details of the mapping
like its size and its offset in the target file. The offset would
correspond to the physical address if using the real /dev/mem.

Change-Id: Icc14cd9ac02eae93c56f1f2aa78fd67d8540a2f2
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/27751
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

dev-arm: Fix VExpressFastmodel timer configs

generic_timer is no longer in the return value of _on_chip_devices. We
should correct the _on_chip_devices. Furthermore, to prevent the timer
conflict with the fastmodel, we should remove unwanted timer.

Change-Id: I6ec7f9749546df3e8f125a5b96e7ed83cab2ea56
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/36379
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

arch-x86: Make CPUID vendor string a param

Modern libraries such as ROCm, MPI, and libnuma use files in Linux'
sysfs to determine the system topology such as number of CPUs, cache
size, cache associativity, etc. If Linux does not recognize the vendor
string returned by CPUID in x86 it will do a generic initialization
which does not include creating these files. In the case of ROCm
(specifically ROCt) this causes failures when getting device properties.

This can be solved by setting the vendor string to, for example,
AuthenticAMD (as qemu does) so that Linux will create the relevant sysfs
files. Unfortunately, simply changing the string in cpuid.cc to
AuthenticAMD causes simulation slowdown and may not be desirable to all
users. This change creates a parameter, defaulting to M5 Simulator as it
currently is, which can be set in python configuration files to change
the vendor string. Example of how to configure this is:

for i in range(len(self.cpus)):
    for j in range(len(self.cpus[i].isa)):
        self.cpus[i].isa[j].vendor_string = "AuthenticAMD"

Change-Id: I8de26d5a145867fa23518718a799dd96b5b9bffa
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/36156
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

dev-arm: Instantiate SCMI in VExpress_GEM5 platforms

JIRA: https://gem5.atlassian.net/browse/GEM5-768

Change-Id: If5c03aed43f6a521c657e0c9b1dfa95fa4c72413
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/34380
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

dev-arm: SCMI Implementation

JIRA: https://gem5.atlassian.net/browse/GEM5-768

Change-Id: I8a60418c1edc79c3f403905618af3bc7989f114e
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/34379
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

dev-arm: Implement Arm MHU (Message Handling Unit)

JIRA: https://gem5.atlassian.net/browse/GEM5-768

Change-Id: I895eba1a3421746a602e6a4f88916da9054169a8
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/34378
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

tests: System is expecting a kvm_vm param for KvmVM

Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Change-Id: I607b7a7c5a7dec5395267b0fc0a7371032037b16
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/31217
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

kvm, arm: Add parameter to force simulation of Gicv2

By setting simulate_gic to True it will be possible to prevent
the simulation from using the host interrupt controller

Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Change-Id: I7c7df798e07bfaddbc2f1e7dd981b6aff621a9d1
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/36795
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Hsuan Hsu <kugwa2000@gmail.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

dev-arm: Add doorbell interface class

JIRA: https://gem5.atlassian.net/browse/GEM5-768

Change-Id: I0d264a74cbf8ca0f780314ad01fb0dd0765a0464
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/34377
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

dev-arm: Define a ParentMem object for DTB autogen

A memory willing to autogenerate child nodes can do that directly in
the generateDeviceTree method.  However sometimes portions of memory
(child nodes) are tagged for specific applications. Hardcoding the
child node in the parent memory class is not flexible, so we delegate
this to the application model, which is registering the generator
helper via the ParentMem interface

JIRA: https://gem5.atlassian.net/browse/GEM5-768

Change-Id: I5fa5bac0decf5399dbaa3804569998dc5e6d7bc0
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/34376
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Richard Cooper <richard.cooper@arm.com>

dev: Add a new RegisterBank which helps handle device registers.

This change includes both the RegisterBank class and register classes,
and a unit test which exercises them.

Change-Id: I28ef0c0b9192ad786625ac83f096f69d8e5af00f
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/35856
Reviewed-by: Matthew Poremba <matthew.poremba@amd.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

misc: Delete the now unnecessary create methods.

Most create() methods are no longer necessary. This change deletes them,
and occasionally moves some code from them into the constructors they
call.

Change-Id: Icbab29ba280144b892f9b12fac9e29a0839477e5
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/36536
Reviewed-by: Gabe Black <gabe.black@gmail.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

arch: Move many of the generic files outside an NULL guard.

These files can be compiled successfully even if the ISA is the NULL
ISA.

Change-Id: I67133ea674f678f33b0aa1ef55af719f2869241d
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/34169
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Gabe Black <gabe.black@gmail.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

arch,sim: Handle KVM SE page faults with workload events.

The event in KVM x86 SE mode plays double duty, triggering a system call
or a page fault depending on where it's called from (the system call
handler vs page fault handler).

This means we can eliminate the page fault gem5 op and the
pseudo_inst.hh switching header file.

This change touches a lot of things, but there wasn't really a good
place to split it up which still made sense and was consistent and
functional.

Change-Id: Ic414829917bcbd421893aa6c89d78273e4926b78
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/34165
Reviewed-by: Gabe Black <gabe.black@gmail.com>
Reviewed-by: Alexandru Duțu <alexandru.dutu@amd.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

python: Make standard Params::create() optional.

The *vast* majority of SimObjects use the standard boilerplate version
of their Params::create() method which just returns new
ClassName(*this); Rather than force every class to define this method,
or annoy and frustrate users who forget and then get linker errors, this
change automates the default while leaving the possibility of defining a
custom create() method for non-default cases.

The situations this mechanism handles can be first broken down by
whether the SimObject class has a constructor of the normal form, ie one
that takes a const Params reference as its only parameter.

If no, then no default create() implementation is defined, and one
*must* be defined by the user.

If yes, then a default create() implementation is defined as a weak
symbol. If the user still wants to define their own create method for
some reason, perhaps to add debugging info, to keep track of instances
in c++, etc., then they can and it will override the weak symbol and
take precedence.

The way this is implemented is not straightforward. A set of classes are
defined which use SFINAE which either map in the real Params type or a
dummy based on whether the normal constructor exists in the SimObject
class. Then those classes are used to define *a* create method.
Depending on how the SFINAE works out, that will either be *the* create
method on the real Params struct, or a create method on a dummy class
set up to just absorb the definition and then go away. In either case the
create() method is a weak symbol, but in the dummy case it
doesn't/shouldn't matter.

Annoyingly the compiler insists that the weak symbol be visible. While
that makes total sense normally, we don't actually care what happens to
the weak symbol if it's attached to the dummy class. Unfortunately that
means we need to make the dummy class globally visible, although we put
it in a namespace to keep it from colliding with anything useful.

Change-Id: I3767a8dc8dc03665a72d5e8c294550d96466f741
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/35942
Reviewed-by: Gabe Black <gabe.black@gmail.com>
Reviewed-by: Richard Cooper <richard.cooper@arm.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

sim: Remove the syscall gem5 op.

This is now handled by the workload "event" gem5 op.

Change-Id: Ibc195fde14a6174d1978bf280c349ca895e7fda3
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/34164
Reviewed-by: Gabe Black <gabe.black@gmail.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

x86,kvm: Use the new workload event to trigger KVM system calls.

While events are only used for SE mode for now, this moves to using the
common mechanism and gets rid of the need for the system call specific
pseudo inst.

Change-Id: I53468103d7f046b85cc25cbff94b12dbc946f4f0
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/34163
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Gabe Black <gabe.black@gmail.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

sim: Add a new gem5 op for workload events.

This is a way to send a very generic poke to the workload so it can do
something. It's up to the workload to know what information to look for
to interpret an event, such as what PC it came from, what register
values are, or the context of the workload itself (is this SE mode? which
OS is running?).

Change-Id: Ifa4bdf3b5c5a934338c50600747d0b65f4b5eb2b
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/34162
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

mips: Implement an SE workload for Linux.

Change-Id: I78f6048cfe06be1b08d54dc7d24cb3518e97be0f
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/34158
Reviewed-by: Gabe Black <gabe.black@gmail.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

riscv: Implement an SE workload for Linux.

Change-Id: Ieb7058007e56ce0c8d153c1853e4b92237e98ab8
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/34156
Reviewed-by: Gabe Black <gabe.black@gmail.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

x86,scons: De-indent the main x86 SConscript file.

Rather than put all the declaration of sources in the body of an "if", if
the "if" wouldn't happen, exit from the SConscript entirely. Then the
other parts of the SConscript can be totally unindented. Also wrap some
lines which were longer than 80 characters.

Change-Id: I113d649cdd051da02d5ab14a4547b26113d2f7ef
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/34161
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Reviewed-by: Gabe Black <gabe.black@gmail.com>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

x86: Separate system call tables into their own files.

These tables take up a lot of space and obscure what's going on in the
file around them. This change moves them into their own files (one for
32 bit and one for 64 bit). It also moves the x86 local definitions of
some system calls into their own file, and creates a SConscript file for
the linux subdirectory.

Change-Id: Ib0978005783b41789ea59695ad95b0336f6353eb
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/34160
Reviewed-by: Gabe Black <gabe.black@gmail.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

arm: Implement an SE workload for Linux and FreeBSD.

Change-Id: I3bac27ca8d5ed9fa11b519ea29b73c6d09260157
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/34159
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

arch: Re-add copyrights that were accidentally removed.

The partial contents of some files were moved into other files, but the
copyright wasn't moved over with them. This propogates the copyright.

Change-Id: I8612e88ffb7584b15924cf747f671ca3cdefbe55
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/36716
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

sim: Add a missing include to sim/syscall_abi.hh.

This must have been included indirectly in the past.

Change-Id: I8be3a11ca386e420f04d57e51a89c47e6a747e18
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/36616
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

sim: Replace any getDTBPtr/getITBPtr usage

JIRA: https://gem5.atlassian.net/browse/GEM5-790

Change-Id: Ibd78bef263d186889f4533583ff30f46a0a8643f
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/34981
Tested-by: kokoro <noreply+kokoro@google.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>

tests: fix dezip of ubuntu images in long regr

needed to change output open from 'w' to 'wb'
to write binary format

Change-Id: Ia176d86a8ab8cc083ffc9508e051b667936eca2c
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/36615
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>

arch-x86: Replace any getDTBPtr/getITBPtr usage

The getMMUPtr should be used instead

JIRA: https://gem5.atlassian.net/browse/GEM5-790

Change-Id: I363c2b50abdd5d2d8442ebf5892eaf17c99c129a
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/34979
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>

arch-sparc: Replace any getDTBPtr/getITBPtr usage

JIRA: https://gem5.atlassian.net/browse/GEM5-790

Change-Id: I931b7b4203b9ae18f46e2d985c7c7b5b339cb9e6
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/34982
Reviewed-by: Gabe Black <gabe.black@gmail.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

arch-riscv: Replace any getDTBPtr/getITBPtr usage

The getMMUPtr should be used instead

JIRA: https://gem5.atlassian.net/browse/GEM5-790

Change-Id: I46282b43b53b7dc9f9c6bb959d4aa23ee6808a6b
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/34980
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

sparc: Remove support for Solaris SE mode.

In SPARC and SE mode, system calls are triggered by a trap exception
with the appropriate trap number, and then a handler within the Workload
(formerly the Process) object recognizes the trap number and triggers
the system call.

For Linux, this special handling happens in the Linux specific Workload,
and other types of traps are passed through to the base SPARC SE
Workload class. For Solaris however, no special handling is implemented.
That means that it's actually impossible for a Solaris SE mode program
to actually trigger a system call, and so while there is some code
written for Solaris SE mode, this feature does not actually work at all.

Also, while it's relatively easy to build binaries for Linux on various
architectures using, for instance, the crosstool-ng configs in util/,
there is no ready made option that I could find for building a SPARC
Solaris cross compiler which would run on x86 linux.

Given that the support that exists isn't actually hooked up properly,
SPARC is not one of the most popular ISAs within gem5, Solaris is not a
widely used operating system, we have (to my knowledge) no test binary
to run, and setting up a cross compiler would be non-trivial, it makes
the most sense to me to remove this support.

Change-Id: I896b5abc4bf337bd4e4c06c49de7111a3b2b784c
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/33996
Reviewed-by: Gabe Black <gabe.black@gmail.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

sparc: Implement an SE workload for Linux and Solaris.

I don't have a binary to test Solaris SE mode, but this *should* still
work.

Change-Id: Iaacc2ddd5193d7341bc65b9fdd5657c26d231cf1
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/33995
Reviewed-by: Gabe Black <gabe.black@gmail.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

gpu: Use X86ISA instead of TheISA in src/gpu-compute.

These files are nominally not tied to the X86ISA, but in reality they
are because they reach into the GPU TLB, which is defined unchangeably in
the X86ISA namespaces, and uses data structures within it. Rather than try
to pretend that these structures are generic, we'll instead just use X86ISA
instead of TheISA. If this really does become generic in the future, a
base class with the ISA agnostic essentials defined in it can be used
instead, and the ISA specific TLBs can defined their own derived class
which has whatever else they need. Really the compute unit shouldn't be
communicating with the TLB using sender state since those are supposed
to be little notes for the sender to keep with a transaction, not for
communicating between entities across a port.

Change-Id: Ie6573396f6c77a9a02194f5f4595eefa45d6d66b
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/34174
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>

power: Implement an SE workload for Linux.

Change-Id: Ie242698b7f9e6ffffd4abdcbb483ee81d64802d9
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/34157
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Sandipan Das <sandipan@linux.ibm.com>

x86: Delegate process loading to the EmuLinux workload.

This is still triggered by the generic mechanism that tries out all
paths to go from an object file to a process. That's not entirely
necessary since the only loader that should be used when using the
X86ISA::EmuLinux workload is the one it provides, but the rest of gem5
isn't ready for that change yet.

This removes the last lingering reason to keep around the
arch/x86/linux/process.(hh|cc) files, so they have been deleted.

Change-Id: I425b95c9c730f31291790d63bc842e2c0092960d
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/33904
Reviewed-by: Gabe Black <gabe.black@gmail.com>
Reviewed-by: Alexandru Duțu <alexandru.dutu@amd.com>
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

mem: Replace any getDTBPtr/getITBPtr usage

JIRA: https://gem5.atlassian.net/browse/GEM5-790

Change-Id: I0759baec87b3682a057239a6b3b8f79fe3f5592c
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/34983
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

fastmodel: Fix up for the new standardized create() methods.

Change-Id: I2e3610b5cad37b67d32907a2c2568b504d5ed113
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/36155
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

mem-cache: Implement FPC cache compressor

Implementation of Frequent Pattern Compression, proposed
by Alameldeen et al. in "Frequent Pattern Compression: A
Significance-Based Compression Scheme for L2 Caches".

Change-Id: I6dca8ca6b3043b561140bc681dbdbe9f7cef27d7
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/36395
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

mem-cache: Make (de)compression latencies params

Add 4 params to calculate compression and decompression latencies.
A pair of params informs how many chunks are parsed per cycle, and
the other pair informs how many extra cycles are needed after the
chunks are parsed to finish the (de)compression.

Change-Id: Ie67b0c298f06a08011f553789e3a9a1d89dd7c4f
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/36497
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

python: Add support for Proxy division

Allow proxies to use python3's division operations. The dividends
and divisors can be either a proxy or a constant.

Change-Id: I96b854355b8f593edfb1ea52a52548b855b05fc0
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/36496
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

mem-cache: Undefine compression ratio of perfect compression

Commit c0d67b2263aab6a729368373d9cdef9883870241 assumes that the
cache contains a parameter for its compression ratio. This is not
the case upstream, so force the user to provide it instead.

Change-Id: Ic7b4878bede6b0a34e4adfe7e0aa65a0ee48d1f6
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/36495
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

util: Fix an incorrect print statement in git pre-commit hook

Change-Id: I13d0a705b6cfab654635380e2adbf36243344a62
Signed-off-by: Hoa Nguyen <hoanguyen@ucdavis.edu>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/36516
Reviewed-by: Gabe Black <gabe.black@gmail.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

arch-arm: Fix implementation of TLBI ALLEx instructions

The TLBIALL op in gem5 was designed after the AArch32 TLBIALL instruction.
and was reused by the TLBI ALLEL1, ALLE2, ALLE3 logic.

This is not correct for the following reasons:

- TLBI ALLEx invalidates regardless of the VMID
- TLBI ALLEx (AArch64) is "target regime" oriented, whereas TLBIALL
  (AArch32) is "current regime" oriented

TLBIALL has a different behaviour depending on the current exception
level: if issued at EL1 it will invalidate stage1 translations only; if
at EL2, it will invalidate stage2 translations as well.

TLBI ALLEx is more standard; every TLBI ALLE1 will invalidate stage1 and
stage2 translations. This is because the instruction is not executable
from the guest (EL1)

So for TLBIALL the condition for stage2 forwarding will be:

if (!isStage2 && isHyp) {

Whereas for TLBI ALLEx will be:

if (!isStage2 && target_el == EL1) {

Change-Id: I282f2cfaecbfc883e173770e5d2578b41055bb7a
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/35241
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

arch-arm: Rewrite the TLB flushing interface

We are now using an overloaded flush method which has
different TLBI ops as arguments.

This is simplifying the interface and it is allowing us to
encode some state in the TLBIOp which will then be passed
to the TLB. This is a step towards making the TLB a stateless
cache of translations

Change-Id: Ic4fbae72dc3cfe756047148b1cf5f144298c8b08
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/35240
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Richard Cooper <richard.cooper@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

arch-arm: Reimplement TLB::flushAll

flushAll is a non architectural flush command; this is not based on
flushAllSecurity anymore. flushAll should always flush stage1 and stage2,
whereas flushAllSecurity is checking for the current state
(vmid, and if we are in Hyp)

Change-Id: I6b81ebfba387e646f256ecbecb7b5ee720745358
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/35239
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Richard Cooper <richard.cooper@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

arch-arm: TLBIALL/TLBIASID/TLBIMVA base classes for I/D flavours

This will be exploited by the incoming patchset

Change-Id: Ic10a8d64910a04d4153b0f2abb133dfd56dbaf62
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/35238
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Richard Cooper <richard.cooper@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

scons: Don't check for Python 2

The build system will now refuse to build gem5 if Python 2.x is
detected. Remove Python 2 specific python-config variants from the
list of candidates we try.

Change-Id: Id59be4a2969ce180848e5df02afdfb4a5b8125c1
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/36535
Reviewed-by: Gabe Black <gabe.black@gmail.com>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

scons: Test if binaries can embed the Python interpreter

Add some more stringent Python tests that ensure that we can link with
and run applications that embed Python. This is implemented by running
building a small c++ program that embeds Python using PyBind11. The
program is run by the build system and prints the version of the
Python interpreter. The version information is then used by the build
system to ensure that the installed version is supported.

Change-Id: I727e0832f171362f5506247c022bea365068a0f6
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/36383
Reviewed-by: Gabe Black <gabe.black@gmail.com>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

misc: Replace enable_if<>::type with enable_if_t<>.

This new abreviated form was added for C++14. Now that we're using that
version of the standard, we can move over to it.

Change-Id: Ia291d2b1e73e503c37593b1e1c4c1b3011abc63b
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/36477
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

dev-arm: Fix VExpressFastmodel interrupt configs

HDLcd interrupt params should receive ArmSPI class

Change-Id: I4a5dacdfe5803511d19f2ed789017fb3b1857bdb
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/36455
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

x86: Move syscall handling for Linux into the EmuLinux workload.

Change-Id: I3fe1997e62491e9576b787660b7fae5ae99fb5c9
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/33903
Reviewed-by: Gabe Black <gabe.black@gmail.com>
Reviewed-by: Alexandru Duțu <alexandru.dutu@amd.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

x86: Create an SEWorkload for x86 linux.

This doesn't do anything interesting yet, but soon it will take over
system call duties from the x86 linux processes.

Change-Id: Ic126fc80def0b458de51d3a9c96120c58e5a75ad
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/33902
Reviewed-by: Gabe Black <gabe.black@gmail.com>
Reviewed-by: Alexandru Duțu <alexandru.dutu@amd.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

base,sim: Move BitUnion serialization support to bitunion.hh.

This keeps the BitUnion code centralized and out of the generic
serialization code.

Change-Id: I297638df4f8908096b7c439298fbaf03236f9011
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/36283
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

sim: Move the serialization backend handlers to their own header.

This way other types which want to enable serialization can include just
these handlers and specialize them as necessary without bringing in all
the other dependencies of the serialization mechanism.

Change-Id: I7310e7741615e23ac0fc762e951bf5eac00aaa74
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/36281
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

sim: Refactor how serialization types are handled in the backend.

The parseParam and showParam functions partially worked using template
specialization, and partially worked using function overloading. The
template specialization could be resolved later once other functions
were added, but the regular function overloads could not. That meant
that it was practically impossible to add new definitions of those two
functions local to the types they worked with.

Also, because C++ does not allow partial specialization of template
functions, it would not be possible to truly use specialization to wire
in BitUnion types.

To fix these problems, these functions have been turned into structs
which wrap static functions. These can be partially specialized as
desired, making them compatible with BitUnions. Also, it's not possible
to overload structures like it is with functions, so only specialization
is considered, not overloading.

While making these changes, these functions (now structs) were also
reworked so that they share implementation more, and are generally
more streamlined.

Given the fact that the previous parseParam and showParam functions
could not actually be expanded beyond serialize.hh, and were not
actually called directly by any code outside of that file, they should
have never been considered part of the API.

Now that these structs actually *can* be specialized outside of this
file, they should be considered part of the interface.

Change-Id: Ic8e677b97fda8378ee1da1f3cf6001e02783fde3
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/36280
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Richard Cooper <richard.cooper@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

base: Narrow the applicability of the default to_number.

That template only works for integral (except bool), floating point,
or enum types, so restrict it to those types. That makes it easier to
detect what types will work with that function.

Change-Id: Ib29a9a0ea75dd617e28bb6850d60be905f93182f
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/36279
Reviewed-by: Gabe Black <gabe.black@gmail.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

sim: Fix API comments for optParamIn.

The top level comment was correct, but the parameter comments talked
about writing parameters instead of reading them. Also simplified the
wording of the return value comment.

Change-Id: I156aba5b69c281ee2f34297bf3f75fd0acfb2b6e
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/36278
Maintainer: Gabe Black <gabe.black@gmail.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

sim: Generalize the arrayParamOut and arrayParamIn functions.

These had been written specifically for the vector, list, set, and C
style array types. This change reworks them to share an implementation,
and to work with more general types. The arrayParamOut method requires
std::begin() and std::end() to accept that type, and the arrayParamIn
method requires either insert or push_back, or the type to be an array.

Also fix up a couple of files which accidentally depended on includes in
the serialize headers which are no longer necessary.

Change-Id: I6ec4fe3bb900603bbb4e35c4efa620c249942452
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/36277
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

mem-ruby: L1/L2 hit/miss tracking for MOESI_AMD_BASE/GPU_VIPER

L1 and L2 access tracking was not fully implemented.
This patch adds the missing tracking actions, and corrects
several errors for the ones that were there.

Change-Id: I69a59283274c08e94b6650ab5f586cbfe5432503
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/33915
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Matt Sinclair <mattdsinclair@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Matt Sinclair <mattdsinclair@gmail.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>

mem-ruby: L3 hit/miss tracking to MOESI_AMD_BASE-dir

L3 access tracking added to the directory controller.

This commit adds L3 hit/miss tracking to the controller.
Hit/miss status is decided when the tag array of the
L3 Cache is checked for the first time for any given request.

Change-Id: Icac122f59509d79135265fb38b112d3f47419b6f
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/33314
Reviewed-by: Matt Sinclair <mattdsinclair@gmail.com>
Maintainer: Matt Sinclair <mattdsinclair@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>