Eddie Hung [Wed, 18 Dec 2019 18:55:44 +0000 (13:55 -0500)]
Merge pull request #1572 from nakengelhardt/scratchpad_pass
add a command to read/modify scratchpad contents
Eddie Hung [Wed, 18 Dec 2019 17:53:45 +0000 (12:53 -0500)]
Merge pull request #1584 from YosysHQ/mwk/xilinx-flaky-test
tests/xilinx: fix flaky mux test
Marcin Kościelnicki [Wed, 18 Dec 2019 14:53:20 +0000 (15:53 +0100)]
tests/xilinx: fix flaky mux test
Marcin Kościelnicki [Wed, 18 Dec 2019 12:42:26 +0000 (13:42 +0100)]
xilinx: Add xilinx_dffopt pass (#1557)
Marcin Kościelnicki [Thu, 21 Nov 2019 05:30:06 +0000 (06:30 +0100)]
xilinx: Improve flip-flop handling.
This adds support for infering more kinds of flip-flops:
- FFs with async set/reset and clock enable
- FFs with sync set/reset
- FFs with sync set/reset and clock enable
Some passes have been moved (and some added) in order for dff2dffs to
work correctly.
This gives us complete coverage of Virtex 6+ and Spartan 6 flip-flop
capabilities (though not latch capabilities). Older FPGAs also support
having both a set and a reset input, which will be handled at a later
data.
Clifford Wolf [Wed, 18 Dec 2019 12:06:34 +0000 (13:06 +0100)]
Send people to symbioticeda.com instead of verific.com
Signed-off-by: Clifford Wolf <clifford@clifford.at>
N. Engelhardt [Wed, 18 Dec 2019 11:30:30 +0000 (12:30 +0100)]
use extra_args
Eddie Hung [Tue, 17 Dec 2019 05:48:21 +0000 (21:48 -0800)]
Merge pull request #1574 from YosysHQ/eddie/xilinx_lutram
xilinx: add LUTRAM rules for RAM32M, RAM64M
Eddie Hung [Tue, 17 Dec 2019 05:48:02 +0000 (21:48 -0800)]
Merge pull request #1521 from dh73/diego/memattr
Adding support for Xilinx memory attribute 'block' in single port mode.
Eddie Hung [Tue, 17 Dec 2019 01:06:30 +0000 (17:06 -0800)]
Enforce non-existence
Eddie Hung [Mon, 16 Dec 2019 22:48:53 +0000 (14:48 -0800)]
Update doc
Eddie Hung [Mon, 16 Dec 2019 21:57:55 +0000 (13:57 -0800)]
Add another test
Eddie Hung [Mon, 16 Dec 2019 21:56:45 +0000 (13:56 -0800)]
More sloppiness, thanks @dh73 for spotting
Eddie Hung [Mon, 16 Dec 2019 21:31:47 +0000 (13:31 -0800)]
Accidentally commented out tests
Eddie Hung [Mon, 16 Dec 2019 21:31:15 +0000 (13:31 -0800)]
Add unconditional match blocks for force RAM
Eddie Hung [Mon, 16 Dec 2019 21:31:05 +0000 (13:31 -0800)]
Oops
Eddie Hung [Mon, 16 Dec 2019 21:01:51 +0000 (13:01 -0800)]
Merge blockram tests
Eddie Hung [Mon, 16 Dec 2019 21:00:58 +0000 (13:00 -0800)]
Update xc7/xcu bram rules
Eddie Hung [Mon, 16 Dec 2019 20:58:13 +0000 (12:58 -0800)]
Implement 'attributes' grammar
Eddie Hung [Mon, 16 Dec 2019 20:07:49 +0000 (12:07 -0800)]
Merge branch 'diego/memattr' of https://github.com/dh73/yosys into diego/memattr
Eddie Hung [Mon, 16 Dec 2019 20:06:47 +0000 (12:06 -0800)]
Merge branch 'eddie/xilinx_lutram' of github.com:YosysHQ/yosys into eddie/xilinx_lutram
Eddie Hung [Mon, 16 Dec 2019 19:56:26 +0000 (11:56 -0800)]
Populate DID/DOD even if unused
Eddie Hung [Mon, 16 Dec 2019 18:41:13 +0000 (10:41 -0800)]
Rename *RAM{32,64}M rules to RAM{32X2,64X1}Q
Diego H [Mon, 16 Dec 2019 16:23:45 +0000 (10:23 -0600)]
Fixing compiler warning/issues. Moving test script to the correct place
N. Engelhardt [Mon, 16 Dec 2019 12:09:31 +0000 (13:09 +0100)]
add assert option to scratchpad command
Diego H [Mon, 16 Dec 2019 05:51:58 +0000 (23:51 -0600)]
Removing fixed attribute value to !ramstyle rules
Diego H [Mon, 16 Dec 2019 05:33:09 +0000 (23:33 -0600)]
Merging attribute rules into a single match block; Adding tests
Eddie Hung [Mon, 16 Dec 2019 03:00:34 +0000 (19:00 -0800)]
Merge pull request #1575 from rodrigomelo9/master
Fixed some missing "verilog_" in documentation
Eddie Hung [Mon, 16 Dec 2019 02:59:55 +0000 (18:59 -0800)]
Merge pull request #1577 from gromero/for-yosys
manual: Fix text in Abstract section
Eddie Hung [Mon, 16 Dec 2019 02:59:36 +0000 (18:59 -0800)]
Merge pull request #1578 from noopwafel/eqneq-debug
Fix opt_expr.eqneq.cmpzero debug print
Alyssa Milburn [Sun, 15 Dec 2019 19:40:38 +0000 (20:40 +0100)]
Fix opt_expr.eqneq.cmpzero debug print
Diego H [Fri, 13 Dec 2019 21:43:24 +0000 (15:43 -0600)]
Refactoring memory attribute matching based on IEEE 1364.1 and Tool specific
Eddie Hung [Fri, 13 Dec 2019 20:01:03 +0000 (12:01 -0800)]
Merge pull request #1533 from dh73/bram_xilinx
Adjust Xilinx xc7/xcu BRAM min bits threshold for RAMB18E1
Eddie Hung [Fri, 13 Dec 2019 18:28:13 +0000 (10:28 -0800)]
Disable RAM16X1D test
Eddie Hung [Fri, 13 Dec 2019 16:59:17 +0000 (08:59 -0800)]
Disable RAM16X1D match rule; carry-over from LUT4 arches
Eddie Hung [Fri, 13 Dec 2019 16:54:19 +0000 (08:54 -0800)]
RAM64M8 to also have [5:0] for address
Diego H [Fri, 13 Dec 2019 15:33:18 +0000 (09:33 -0600)]
Renaming BRAM memory tests for the sake of uniformity
Rodrigo Alejandro Melo [Fri, 13 Dec 2019 13:17:05 +0000 (10:17 -0300)]
Fixed some missing "verilog_" in documentation
N. Engelhardt [Fri, 13 Dec 2019 09:28:34 +0000 (10:28 +0100)]
add periods and newlines to help message
Eddie Hung [Fri, 13 Dec 2019 03:00:26 +0000 (19:00 -0800)]
Remove extraneous synth_xilinx call
Eddie Hung [Fri, 13 Dec 2019 02:52:48 +0000 (18:52 -0800)]
Add tests for these new models
Eddie Hung [Fri, 13 Dec 2019 02:52:28 +0000 (18:52 -0800)]
Add RAM32X6SDP and RAM64X3SDP modes
Eddie Hung [Fri, 13 Dec 2019 02:52:03 +0000 (18:52 -0800)]
Fix RAM64M model to have 6 bit address bus
Eddie Hung [Fri, 13 Dec 2019 01:49:55 +0000 (17:49 -0800)]
Add #1460 testcase
Eddie Hung [Fri, 13 Dec 2019 01:44:59 +0000 (17:44 -0800)]
Add memory rules for RAM16X1D, RAM32M, RAM64M
Eddie Hung [Fri, 13 Dec 2019 01:44:37 +0000 (17:44 -0800)]
Rename memory tests to lutram, add more xilinx tests
Diego H [Thu, 12 Dec 2019 23:32:58 +0000 (17:32 -0600)]
Fixing citation in xc7_xcu_brams.txt file. Fixing RAMB36E1 test.
Eddie Hung [Thu, 12 Dec 2019 22:56:15 +0000 (14:56 -0800)]
abc9_map.v: fix Xilinx LUTRAM
Diego H [Thu, 12 Dec 2019 22:06:46 +0000 (16:06 -0600)]
Adding a note (TODO) in the memory_params.ys check file
N. Engelhardt [Thu, 12 Dec 2019 19:51:59 +0000 (20:51 +0100)]
add test and make help message more verbose
Diego H [Thu, 12 Dec 2019 19:50:36 +0000 (13:50 -0600)]
Updating RAMB36E1 thresholds. Adding test for both RAMB18E1/RAMB36E1
Diego H [Thu, 12 Dec 2019 19:40:05 +0000 (13:40 -0600)]
Merge https://github.com/YosysHQ/yosys into bram_xilinx
N. Engelhardt [Thu, 12 Dec 2019 15:14:20 +0000 (16:14 +0100)]
add a command to read/modify scratchpad contents
Eddie Hung [Thu, 12 Dec 2019 00:38:43 +0000 (16:38 -0800)]
Update README.md :: abc_ -> abc9_
Eddie Hung [Wed, 11 Dec 2019 21:02:07 +0000 (13:02 -0800)]
Fix bitwidth mismatch; suppresses iverilog warning
Gustavo Romero [Wed, 11 Dec 2019 11:09:48 +0000 (08:09 -0300)]
manual: Fix text in Abstract section
David Shah [Wed, 11 Dec 2019 08:46:10 +0000 (08:46 +0000)]
Merge pull request #1564 from ZirconiumX/intel_housekeeping
Intel housekeeping
Dan Ravensloft [Tue, 10 Dec 2019 13:40:32 +0000 (13:40 +0000)]
synth_intel: a10gx -> arria10gx
Dan Ravensloft [Tue, 10 Dec 2019 13:31:45 +0000 (13:31 +0000)]
synth_intel: cyclone10 -> cyclone10lp
Eddie Hung [Tue, 10 Dec 2019 01:38:48 +0000 (17:38 -0800)]
Merge pull request #1545 from YosysHQ/eddie/ice40_wrapcarry_attr
Preserve SB_CARRY name and attributes when using $__ICE40_CARRY_WRAPPER
Eddie Hung [Mon, 9 Dec 2019 22:29:29 +0000 (14:29 -0800)]
ice40_opt to restore attributes/name when unwrapping
Eddie Hung [Mon, 9 Dec 2019 22:28:54 +0000 (14:28 -0800)]
ice40_wrapcarry -unwrap to preserve 'src' attribute
Eddie Hung [Mon, 9 Dec 2019 22:20:35 +0000 (14:20 -0800)]
unmap $__ICE40_CARRY_WRAPPER in test
Eddie Hung [Mon, 9 Dec 2019 21:27:09 +0000 (13:27 -0800)]
-unwrap to create $lut not SB_LUT4 for opt_lut
Eddie Hung [Mon, 9 Dec 2019 20:45:22 +0000 (12:45 -0800)]
Sensitive to direct inst of $__ICE40_CARRY_WRAPPER; recreate SB_LUT4
Eddie Hung [Mon, 9 Dec 2019 19:48:28 +0000 (11:48 -0800)]
ice40_wrapcarry to really preserve attributes via -unwrap option
Eddie Hung [Sat, 7 Dec 2019 07:04:04 +0000 (23:04 -0800)]
Merge pull request #1555 from antmicro/fix-macc-xilinx-test
tests: arch: xilinx: Change order of arguments in macc.sh
Eddie Hung [Sat, 7 Dec 2019 01:27:47 +0000 (17:27 -0800)]
Drop keep=0 attributes on SB_CARRY
Jan Kowalewski [Fri, 6 Dec 2019 08:01:16 +0000 (09:01 +0100)]
tests: arch: xilinx: Change order of arguments in macc.sh
Clifford Wolf [Thu, 5 Dec 2019 16:24:24 +0000 (08:24 -0800)]
Merge pull request #1551 from whitequark/manual-cell-operands
Clarify semantics of comb cells, in particular shifts
Eddie Hung [Thu, 5 Dec 2019 15:01:18 +0000 (07:01 -0800)]
Merge SB_CARRY+SB_LUT4's attributes when creating $__ICE40_CARRY_WRAPPER
Eddie Hung [Thu, 5 Dec 2019 15:01:02 +0000 (07:01 -0800)]
Add WIP test for unwrapping $__ICE40_CARRY_WRAPPER
whitequark [Wed, 4 Dec 2019 11:59:36 +0000 (11:59 +0000)]
kernel: require \B_SIGNED=0 on $shl, $sshl, $shr, $sshr.
Before this commit, these cells would accept any \B_SIGNED and in
case of \B_SIGNED=1, would still treat the \B input as unsigned.
Also fix the Verilog frontend to never emit such constructs.
whitequark [Wed, 4 Dec 2019 11:06:05 +0000 (11:06 +0000)]
manual: document behavior of many comb cells more precisely.
Marcin Kościelnicki [Wed, 4 Dec 2019 08:44:00 +0000 (09:44 +0100)]
xilinx: Add tristate buffer mapping. (#1528)
Fixes #1225.
Marcin Kościelnicki [Wed, 4 Dec 2019 07:44:08 +0000 (08:44 +0100)]
iopadmap: Refactor and fix tristate buffer mapping. (#1527)
The previous code for rerouting wires when inserting tristate buffers
was overcomplicated and didn't handle all cases correctly (in
particular, only cell connections were rewired — internal connections
were not).
Marcin Kościelnicki [Wed, 4 Dec 2019 05:31:09 +0000 (06:31 +0100)]
xilinx: Add models for LUTRAM cells. (#1537)
Eddie Hung [Tue, 3 Dec 2019 22:51:39 +0000 (14:51 -0800)]
Check SB_CARRY name also preserved
Eddie Hung [Tue, 3 Dec 2019 22:49:10 +0000 (14:49 -0800)]
$__ICE40_CARRY_WRAPPER to use _TECHMAP_REPLACE_ for SB_CARRY to preserve
name and attr
Eddie Hung [Tue, 3 Dec 2019 22:48:39 +0000 (14:48 -0800)]
ice40_opt to ignore (* keep *) -ed cells
Eddie Hung [Tue, 3 Dec 2019 22:48:11 +0000 (14:48 -0800)]
ice40_wrapcarry to preserve SB_CARRY's attributes
Eddie Hung [Tue, 3 Dec 2019 22:48:00 +0000 (14:48 -0800)]
Add testcase
Clifford Wolf [Tue, 3 Dec 2019 16:43:18 +0000 (08:43 -0800)]
Merge pull request #1524 from pepijndevos/gowindffinit
Gowin: add and test DFF init values
Pepijn de Vos [Tue, 3 Dec 2019 15:56:15 +0000 (16:56 +0100)]
update test
Pepijn de Vos [Tue, 3 Dec 2019 14:12:25 +0000 (15:12 +0100)]
Use -match-init to not synth contradicting init values
David Shah [Mon, 2 Dec 2019 10:20:21 +0000 (10:20 +0000)]
Merge pull request #1542 from YosysHQ/dave/abc9-loop-fix
abc9: Fix breaking of SCCs
Clifford Wolf [Mon, 2 Dec 2019 00:30:48 +0000 (16:30 -0800)]
Merge pull request #1539 from YosysHQ/mwk/ilang-bounds-check
read_ilang: do bounds checking on bit indices
David Shah [Sun, 1 Dec 2019 20:44:56 +0000 (20:44 +0000)]
abc9: Fix breaking of SCCs
Signed-off-by: David Shah <dave@ds0.me>
Miodrag Milanović [Fri, 29 Nov 2019 16:33:41 +0000 (17:33 +0100)]
Merge pull request #1540 from YosysHQ/mwk/xilinx-bufpll
xilinx: Add missing blackbox cell for BUFPLL.
Marcin Kościelnicki [Fri, 29 Nov 2019 15:55:29 +0000 (15:55 +0000)]
xilinx: Add missing blackbox cell for BUFPLL.
Eddie Hung [Thu, 28 Nov 2019 05:55:56 +0000 (21:55 -0800)]
Revert "Fold loop"
This reverts commit
a30d5e1cc35791a98b2269c5e587c566fe8b0a35.
Marcin Kościelnicki [Wed, 27 Nov 2019 21:24:39 +0000 (22:24 +0100)]
read_ilang: do bounds checking on bit indices
Diego H [Tue, 26 Nov 2019 23:14:41 +0000 (17:14 -0600)]
Adjusting Vivado's BRAM min bits threshold for RAMB18E1
Eddie Hung [Wed, 27 Nov 2019 16:00:22 +0000 (08:00 -0800)]
Merge pull request #1536 from YosysHQ/eddie/xilinx_dsp_muladd
xilinx_dsp: consider sign and zero-extension when packing post-multiplier adder
Clifford Wolf [Wed, 27 Nov 2019 10:25:23 +0000 (11:25 +0100)]
Merge pull request #1501 from YosysHQ/dave/mem_copy_attr
memory_collect: Copy attr from RTLIL::Memory to cell
Clifford Wolf [Wed, 27 Nov 2019 10:23:16 +0000 (11:23 +0100)]
Merge pull request #1534 from YosysHQ/mwk/opt_share-fix
opt_share: Fix handling of fine cells.
Eddie Hung [Wed, 27 Nov 2019 09:04:29 +0000 (01:04 -0800)]
Merge pull request #1535 from YosysHQ/eddie/write_xaiger_improve
write_xaiger improvements
Eddie Hung [Wed, 27 Nov 2019 07:08:14 +0000 (23:08 -0800)]
No need for -abc9
Marcin Kościelnicki [Tue, 26 Nov 2019 23:46:21 +0000 (00:46 +0100)]
opt_share: Fix handling of fine cells.
Fixes #1525.
Eddie Hung [Wed, 27 Nov 2019 06:59:05 +0000 (22:59 -0800)]
latch -> box